2 //***************************************************************************
4 // InstrSelectionSupport.h
7 // Target-independent instruction selection code.
8 // See SparcInstrSelection.cpp for usage.
11 // 10/10/01 - Vikram Adve - Created
12 //**************************************************************************/
14 #include "llvm/CodeGen/InstrSelectionSupport.h"
15 #include "llvm/CodeGen/InstrSelection.h"
16 #include "llvm/CodeGen/MachineInstr.h"
17 #include "llvm/Target/TargetMachine.h"
18 #include "llvm/Target/MachineRegInfo.h"
19 #include "llvm/ConstPoolVals.h"
20 #include "llvm/Instruction.h"
21 #include "llvm/Type.h"
22 #include "llvm/iMemory.h"
25 //*************************** Local Functions ******************************/
28 static TmpInstruction*
29 InsertCodeToLoadConstant(Value* opValue,
31 vector<MachineInstr*>& loadConstVec,
32 TargetMachine& target)
34 vector<TmpInstruction*> tempVec;
36 // Create a tmp virtual register to hold the constant.
37 TmpInstruction* tmpReg =
38 new TmpInstruction(TMP_INSTRUCTION_OPCODE, opValue, NULL);
39 vmInstr->getMachineInstrVec().addTempValue(tmpReg);
41 target.getInstrInfo().CreateCodeToLoadConst(opValue, tmpReg,
42 loadConstVec, tempVec);
44 // Register the new tmp values created for this m/c instruction sequence
45 for (unsigned i=0; i < tempVec.size(); i++)
46 vmInstr->getMachineInstrVec().addTempValue(tempVec[i]);
48 // Record the mapping from the tmp VM instruction to machine instruction.
49 // Do this for all machine instructions that were not mapped to any
50 // other temp values created by
51 // tmpReg->addMachineInstruction(loadConstVec.back());
57 //---------------------------------------------------------------------------
58 // Function GetConstantValueAsSignedInt
60 // Convenience function to get the value of an integer constant, for an
61 // appropriate integer or non-integer type that can be held in an integer.
62 // The type of the argument must be the following:
63 // Signed or unsigned integer
67 // isValidConstant is set to true if a valid constant was found.
68 //---------------------------------------------------------------------------
71 GetConstantValueAsSignedInt(const Value *V,
72 bool &isValidConstant)
74 if (!isa<ConstPoolVal>(V))
76 isValidConstant = false;
80 isValidConstant = true;
82 if (V->getType() == Type::BoolTy)
83 return (int64_t) ((ConstPoolBool*)V)->getValue();
85 if (V->getType()->isIntegral())
87 if (V->getType()->isSigned())
88 return ((ConstPoolSInt*)V)->getValue();
90 assert(V->getType()->isUnsigned());
91 uint64_t Val = ((ConstPoolUInt*)V)->getValue();
92 if (Val < INT64_MAX) // then safe to cast to signed
96 isValidConstant = false;
101 //---------------------------------------------------------------------------
102 // Function: FoldGetElemChain
105 // Fold a chain of GetElementPtr instructions into an equivalent
106 // (Pointer, IndexVector) pair. Returns the pointer Value, and
107 // stores the resulting IndexVector in argument chainIdxVec.
108 //---------------------------------------------------------------------------
111 FoldGetElemChain(const InstructionNode* getElemInstrNode,
112 vector<ConstPoolVal*>& chainIdxVec)
114 MemAccessInst* getElemInst = (MemAccessInst*)
115 getElemInstrNode->getInstruction();
117 // Initialize return values from the incoming instruction
118 Value* ptrVal = getElemInst->getPtrOperand();
119 chainIdxVec = getElemInst->getIndexVec(); // copies index vector values
121 // Now chase the chain of getElementInstr instructions, if any
122 InstrTreeNode* ptrChild = getElemInstrNode->leftChild();
123 while (ptrChild->getOpLabel() == Instruction::GetElementPtr ||
124 ptrChild->getOpLabel() == GetElemPtrIdx)
126 // Child is a GetElemPtr instruction
127 getElemInst = (MemAccessInst*)
128 ((InstructionNode*) ptrChild)->getInstruction();
129 const vector<ConstPoolVal*>& idxVec = getElemInst->getIndexVec();
131 // Get the pointer value out of ptrChild and *prepend* its index vector
132 ptrVal = getElemInst->getPtrOperand();
133 chainIdxVec.insert(chainIdxVec.begin(), idxVec.begin(), idxVec.end());
135 ptrChild = ptrChild->leftChild();
142 //------------------------------------------------------------------------
143 // Function Set2OperandsFromInstr
144 // Function Set3OperandsFromInstr
146 // For the common case of 2- and 3-operand arithmetic/logical instructions,
147 // set the m/c instr. operands directly from the VM instruction's operands.
148 // Check whether the first or second operand is 0 and can use a dedicated "0"
150 // Check whether the second operand should use an immediate field or register.
151 // (First and third operands are never immediates for such instructions.)
154 // canDiscardResult: Specifies that the result operand can be discarded
155 // by using the dedicated "0"
157 // op1position, op2position and resultPosition: Specify in which position
158 // in the machine instruction the 3 operands (arg1, arg2
159 // and result) should go.
161 // RETURN VALUE: unsigned int flags, where
162 // flags & 0x01 => operand 1 is constant and needs a register
163 // flags & 0x02 => operand 2 is constant and needs a register
164 //------------------------------------------------------------------------
167 Set2OperandsFromInstr(MachineInstr* minstr,
168 InstructionNode* vmInstrNode,
169 const TargetMachine& target,
170 bool canDiscardResult,
174 Set3OperandsFromInstr(minstr, vmInstrNode, target,
175 canDiscardResult, op1Position,
176 /*op2Position*/ -1, resultPosition);
181 Set3OperandsFromInstr(MachineInstr* minstr,
182 InstructionNode* vmInstrNode,
183 const TargetMachine& target,
184 bool canDiscardResult,
189 assert(op1Position >= 0);
190 assert(resultPosition >= 0);
193 minstr->SetMachineOperand(op1Position, MachineOperand::MO_VirtualRegister,
194 vmInstrNode->leftChild()->getValue());
196 // operand 2 (if any)
197 if (op2Position >= 0)
198 minstr->SetMachineOperand(op2Position, MachineOperand::MO_VirtualRegister,
199 vmInstrNode->rightChild()->getValue());
201 // result operand: if it can be discarded, use a dead register if one exists
202 if (canDiscardResult && target.getRegInfo().getZeroRegNum() >= 0)
203 minstr->SetMachineOperand(resultPosition,
204 target.getRegInfo().getZeroRegNum());
206 minstr->SetMachineOperand(resultPosition,
207 MachineOperand::MO_VirtualRegister, vmInstrNode->getValue());
211 MachineOperand::MachineOperandType
212 ChooseRegOrImmed(Value* val,
213 MachineOpCode opCode,
214 const TargetMachine& target,
216 unsigned int& getMachineRegNum,
217 int64_t& getImmedValue)
219 MachineOperand::MachineOperandType opType =
220 MachineOperand::MO_VirtualRegister;
221 getMachineRegNum = 0;
224 // Check for the common case first: argument is not constant
226 ConstPoolVal *CPV = dyn_cast<ConstPoolVal>(val);
227 if (!CPV) return opType;
229 if (CPV->getType() == Type::BoolTy)
231 ConstPoolBool *CPB = (ConstPoolBool*)CPV;
232 if (!CPB->getValue() && target.getRegInfo().getZeroRegNum() >= 0)
234 getMachineRegNum = target.getRegInfo().getZeroRegNum();
235 return MachineOperand::MO_MachineRegister;
239 return MachineOperand::MO_SignExtendedImmed;
242 if (!CPV->getType()->isIntegral()) return opType;
244 // Now get the constant value and check if it fits in the IMMED field.
245 // Take advantage of the fact that the max unsigned value will rarely
246 // fit into any IMMED field and ignore that case (i.e., cast smaller
247 // unsigned constants to signed).
250 if (CPV->getType()->isSigned())
252 intValue = ((ConstPoolSInt*)CPV)->getValue();
256 uint64_t V = ((ConstPoolUInt*)CPV)->getValue();
257 if (V >= INT64_MAX) return opType;
258 intValue = (int64_t)V;
261 if (intValue == 0 && target.getRegInfo().getZeroRegNum() >= 0)
263 opType = MachineOperand::MO_MachineRegister;
264 getMachineRegNum = target.getRegInfo().getZeroRegNum();
266 else if (canUseImmed &&
267 target.getInstrInfo().constantFitsInImmedField(opCode, intValue))
269 opType = MachineOperand::MO_SignExtendedImmed;
270 getImmedValue = intValue;
277 //---------------------------------------------------------------------------
278 // Function: FixConstantOperandsForInstr
281 // Special handling for constant operands of a machine instruction
282 // -- if the constant is 0, use the hardwired 0 register, if any;
283 // -- if the constant fits in the IMMEDIATE field, use that field;
284 // -- else create instructions to put the constant into a register, either
285 // directly or by loading explicitly from the constant pool.
287 // In the first 2 cases, the operand of `minstr' is modified in place.
288 // Returns a vector of machine instructions generated for operands that
289 // fall under case 3; these must be inserted before `minstr'.
290 //---------------------------------------------------------------------------
292 vector<MachineInstr*>
293 FixConstantOperandsForInstr(Instruction* vmInstr,
294 MachineInstr* minstr,
295 TargetMachine& target)
297 vector<MachineInstr*> loadConstVec;
299 const MachineInstrDescriptor& instrDesc =
300 target.getInstrInfo().getDescriptor(minstr->getOpCode());
302 for (unsigned op=0; op < minstr->getNumOperands(); op++)
304 const MachineOperand& mop = minstr->getOperand(op);
306 // skip the result position (for efficiency below) and any other
307 // positions already marked as not a virtual register
308 if (instrDesc.resultPos == (int) op ||
309 mop.getOperandType() != MachineOperand::MO_VirtualRegister ||
310 mop.getVRegValue() == NULL)
315 Value* opValue = mop.getVRegValue();
316 bool constantThatMustBeLoaded = false;
318 if (isa<ConstPoolVal>(opValue))
320 unsigned int machineRegNum;
322 MachineOperand::MachineOperandType opType =
323 ChooseRegOrImmed(opValue, minstr->getOpCode(), target,
324 /*canUseImmed*/ (op == 1),
325 machineRegNum, immedValue);
327 if (opType == MachineOperand::MO_MachineRegister)
328 minstr->SetMachineOperand(op, machineRegNum);
329 else if (opType == MachineOperand::MO_VirtualRegister)
330 constantThatMustBeLoaded = true; // load is generated below
332 minstr->SetMachineOperand(op, opType, immedValue);
335 if (constantThatMustBeLoaded || isa<GlobalValue>(opValue))
336 { // opValue is a constant that must be explicitly loaded into a reg.
337 TmpInstruction* tmpReg = InsertCodeToLoadConstant(opValue, vmInstr,
338 loadConstVec, target);
339 minstr->SetMachineOperand(op, MachineOperand::MO_VirtualRegister,
345 // Also, check for implicit operands used (not those defined) by the
346 // machine instruction. These include:
347 // -- arguments to a Call
348 // -- return value of a Return
349 // Any such operand that is a constant value needs to be fixed also.
350 // The current instructions with implicit refs (viz., Call and Return)
351 // have no immediate fields, so the constant always needs to be loaded
354 for (unsigned i=0, N=minstr->getNumImplicitRefs(); i < N; ++i)
355 if (isa<ConstPoolVal>(minstr->getImplicitRef(i)) ||
356 isa<GlobalValue>(minstr->getImplicitRef(i)))
358 TmpInstruction* tmpReg =
359 InsertCodeToLoadConstant(minstr->getImplicitRef(i), vmInstr,
360 loadConstVec, target);
361 minstr->setImplicitRef(i, tmpReg);
368 #undef SAVE_TO_MOVE_BACK_TO_SPARCISSCPP
369 #ifdef SAVE_TO_MOVE_BACK_TO_SPARCISSCPP
371 FixConstantOperands(const InstructionNode* vmInstrNode,
372 TargetMachine& target)
374 Instruction* vmInstr = vmInstrNode->getInstruction();
375 MachineCodeForVMInstr& mvec = vmInstr->getMachineInstrVec();
377 for (unsigned i=0; i < mvec.size(); i++)
379 vector<MachineInsr*> loadConstVec =
380 FixConstantOperandsForInstr(mvec[i], target);
384 // Finally, inserted the generated instructions in the vector
387 unsigned numNew = loadConstVec.size();
390 // Insert the new instructions *before* the old ones by moving
391 // the old ones over `numNew' positions (last-to-first, of course!).
392 // We do check *after* returning that we did not exceed the vector mvec.
393 for (int i=numInstr-1; i >= 0; i--)
394 mvec[i+numNew] = mvec[i];
396 for (unsigned i=0; i < numNew; i++)
397 mvec[i] = loadConstVec[i];
400 return (numInstr + numNew);
402 #endif SAVE_TO_MOVE_BACK_TO_SPARCISSCPP