2 //***************************************************************************
4 // InstrSelectionSupport.h
7 // Target-independent instruction selection code.
8 // See SparcInstrSelection.cpp for usage.
11 // 10/10/01 - Vikram Adve - Created
12 //**************************************************************************/
14 #include "llvm/CodeGen/InstrSelectionSupport.h"
15 #include "llvm/CodeGen/InstrSelection.h"
16 #include "llvm/CodeGen/MachineInstr.h"
17 #include "llvm/Target/TargetMachine.h"
18 #include "llvm/Target/MachineRegInfo.h"
19 #include "llvm/ConstPoolVals.h"
20 #include "llvm/Method.h"
21 #include "llvm/BasicBlock.h"
22 #include "llvm/Instruction.h"
23 #include "llvm/Type.h"
24 #include "llvm/iMemory.h"
27 //*************************** Local Functions ******************************/
30 static TmpInstruction*
31 InsertCodeToLoadConstant(Value* opValue,
33 vector<MachineInstr*>& loadConstVec,
34 TargetMachine& target)
36 vector<TmpInstruction*> tempVec;
38 // Create a tmp virtual register to hold the constant.
39 TmpInstruction* tmpReg =
40 new TmpInstruction(TMP_INSTRUCTION_OPCODE, opValue, NULL);
41 vmInstr->getMachineInstrVec().addTempValue(tmpReg);
43 target.getInstrInfo().CreateCodeToLoadConst(opValue, tmpReg,
44 loadConstVec, tempVec);
46 // Register the new tmp values created for this m/c instruction sequence
47 for (unsigned i=0; i < tempVec.size(); i++)
48 vmInstr->getMachineInstrVec().addTempValue(tempVec[i]);
50 // Record the mapping from the tmp VM instruction to machine instruction.
51 // Do this for all machine instructions that were not mapped to any
52 // other temp values created by
53 // tmpReg->addMachineInstruction(loadConstVec.back());
59 //---------------------------------------------------------------------------
60 // Function GetConstantValueAsSignedInt
62 // Convenience function to get the value of an integer constant, for an
63 // appropriate integer or non-integer type that can be held in an integer.
64 // The type of the argument must be the following:
65 // Signed or unsigned integer
69 // isValidConstant is set to true if a valid constant was found.
70 //---------------------------------------------------------------------------
73 GetConstantValueAsSignedInt(const Value *V,
74 bool &isValidConstant)
76 if (!isa<ConstPoolVal>(V))
78 isValidConstant = false;
82 isValidConstant = true;
84 if (V->getType() == Type::BoolTy)
85 return (int64_t) ((ConstPoolBool*)V)->getValue();
87 if (V->getType()->isIntegral())
89 if (V->getType()->isSigned())
90 return ((ConstPoolSInt*)V)->getValue();
92 assert(V->getType()->isUnsigned());
93 uint64_t Val = ((ConstPoolUInt*)V)->getValue();
94 if (Val < INT64_MAX) // then safe to cast to signed
98 isValidConstant = false;
103 //---------------------------------------------------------------------------
104 // Function: FoldGetElemChain
107 // Fold a chain of GetElementPtr instructions into an equivalent
108 // (Pointer, IndexVector) pair. Returns the pointer Value, and
109 // stores the resulting IndexVector in argument chainIdxVec.
110 //---------------------------------------------------------------------------
113 FoldGetElemChain(const InstructionNode* getElemInstrNode,
114 vector<ConstPoolVal*>& chainIdxVec)
116 MemAccessInst* getElemInst = (MemAccessInst*)
117 getElemInstrNode->getInstruction();
119 // Initialize return values from the incoming instruction
120 Value* ptrVal = getElemInst->getPointerOperand();
121 chainIdxVec = getElemInst->getIndices(); // copies index vector values
123 // Now chase the chain of getElementInstr instructions, if any
124 InstrTreeNode* ptrChild = getElemInstrNode->leftChild();
125 while (ptrChild->getOpLabel() == Instruction::GetElementPtr ||
126 ptrChild->getOpLabel() == GetElemPtrIdx)
128 // Child is a GetElemPtr instruction
129 getElemInst = (MemAccessInst*)
130 ((InstructionNode*) ptrChild)->getInstruction();
131 const vector<ConstPoolVal*>& idxVec = getElemInst->getIndices();
133 // Get the pointer value out of ptrChild and *prepend* its index vector
134 ptrVal = getElemInst->getPointerOperand();
135 chainIdxVec.insert(chainIdxVec.begin(), idxVec.begin(), idxVec.end());
137 ptrChild = ptrChild->leftChild();
144 //------------------------------------------------------------------------
145 // Function Set2OperandsFromInstr
146 // Function Set3OperandsFromInstr
148 // For the common case of 2- and 3-operand arithmetic/logical instructions,
149 // set the m/c instr. operands directly from the VM instruction's operands.
150 // Check whether the first or second operand is 0 and can use a dedicated "0"
152 // Check whether the second operand should use an immediate field or register.
153 // (First and third operands are never immediates for such instructions.)
156 // canDiscardResult: Specifies that the result operand can be discarded
157 // by using the dedicated "0"
159 // op1position, op2position and resultPosition: Specify in which position
160 // in the machine instruction the 3 operands (arg1, arg2
161 // and result) should go.
163 // RETURN VALUE: unsigned int flags, where
164 // flags & 0x01 => operand 1 is constant and needs a register
165 // flags & 0x02 => operand 2 is constant and needs a register
166 //------------------------------------------------------------------------
169 Set2OperandsFromInstr(MachineInstr* minstr,
170 InstructionNode* vmInstrNode,
171 const TargetMachine& target,
172 bool canDiscardResult,
176 Set3OperandsFromInstr(minstr, vmInstrNode, target,
177 canDiscardResult, op1Position,
178 /*op2Position*/ -1, resultPosition);
183 Set3OperandsFromInstr(MachineInstr* minstr,
184 InstructionNode* vmInstrNode,
185 const TargetMachine& target,
186 bool canDiscardResult,
191 assert(op1Position >= 0);
192 assert(resultPosition >= 0);
195 minstr->SetMachineOperand(op1Position, MachineOperand::MO_VirtualRegister,
196 vmInstrNode->leftChild()->getValue());
198 // operand 2 (if any)
199 if (op2Position >= 0)
200 minstr->SetMachineOperand(op2Position, MachineOperand::MO_VirtualRegister,
201 vmInstrNode->rightChild()->getValue());
203 // result operand: if it can be discarded, use a dead register if one exists
204 if (canDiscardResult && target.getRegInfo().getZeroRegNum() >= 0)
205 minstr->SetMachineOperand(resultPosition,
206 target.getRegInfo().getZeroRegNum());
208 minstr->SetMachineOperand(resultPosition,
209 MachineOperand::MO_VirtualRegister, vmInstrNode->getValue());
213 MachineOperand::MachineOperandType
214 ChooseRegOrImmed(Value* val,
215 MachineOpCode opCode,
216 const TargetMachine& target,
218 unsigned int& getMachineRegNum,
219 int64_t& getImmedValue)
221 MachineOperand::MachineOperandType opType =
222 MachineOperand::MO_VirtualRegister;
223 getMachineRegNum = 0;
226 // Check for the common case first: argument is not constant
228 ConstPoolVal *CPV = dyn_cast<ConstPoolVal>(val);
229 if (!CPV) return opType;
231 if (CPV->getType() == Type::BoolTy)
233 ConstPoolBool *CPB = (ConstPoolBool*)CPV;
234 if (!CPB->getValue() && target.getRegInfo().getZeroRegNum() >= 0)
236 getMachineRegNum = target.getRegInfo().getZeroRegNum();
237 return MachineOperand::MO_MachineRegister;
241 return MachineOperand::MO_SignExtendedImmed;
244 if (!CPV->getType()->isIntegral()) return opType;
246 // Now get the constant value and check if it fits in the IMMED field.
247 // Take advantage of the fact that the max unsigned value will rarely
248 // fit into any IMMED field and ignore that case (i.e., cast smaller
249 // unsigned constants to signed).
252 if (CPV->getType()->isSigned())
254 intValue = ((ConstPoolSInt*)CPV)->getValue();
258 uint64_t V = ((ConstPoolUInt*)CPV)->getValue();
259 if (V >= INT64_MAX) return opType;
260 intValue = (int64_t)V;
263 if (intValue == 0 && target.getRegInfo().getZeroRegNum() >= 0)
265 opType = MachineOperand::MO_MachineRegister;
266 getMachineRegNum = target.getRegInfo().getZeroRegNum();
268 else if (canUseImmed &&
269 target.getInstrInfo().constantFitsInImmedField(opCode, intValue))
271 opType = MachineOperand::MO_SignExtendedImmed;
272 getImmedValue = intValue;
279 //---------------------------------------------------------------------------
280 // Function: FixConstantOperandsForInstr
283 // Special handling for constant operands of a machine instruction
284 // -- if the constant is 0, use the hardwired 0 register, if any;
285 // -- if the constant fits in the IMMEDIATE field, use that field;
286 // -- else create instructions to put the constant into a register, either
287 // directly or by loading explicitly from the constant pool.
289 // In the first 2 cases, the operand of `minstr' is modified in place.
290 // Returns a vector of machine instructions generated for operands that
291 // fall under case 3; these must be inserted before `minstr'.
292 //---------------------------------------------------------------------------
294 vector<MachineInstr*>
295 FixConstantOperandsForInstr(Instruction* vmInstr,
296 MachineInstr* minstr,
297 TargetMachine& target)
299 vector<MachineInstr*> loadConstVec;
301 const MachineInstrDescriptor& instrDesc =
302 target.getInstrInfo().getDescriptor(minstr->getOpCode());
304 Method* method = vmInstr->getParent()->getParent();
306 for (unsigned op=0; op < minstr->getNumOperands(); op++)
308 const MachineOperand& mop = minstr->getOperand(op);
310 // skip the result position (for efficiency below) and any other
311 // positions already marked as not a virtual register
312 if (instrDesc.resultPos == (int) op ||
313 mop.getOperandType() != MachineOperand::MO_VirtualRegister ||
314 mop.getVRegValue() == NULL)
319 Value* opValue = mop.getVRegValue();
320 bool constantThatMustBeLoaded = false;
322 if (isa<ConstPoolVal>(opValue))
324 unsigned int machineRegNum;
326 MachineOperand::MachineOperandType opType =
327 ChooseRegOrImmed(opValue, minstr->getOpCode(), target,
328 /*canUseImmed*/ (op == 1),
329 machineRegNum, immedValue);
331 if (opType == MachineOperand::MO_MachineRegister)
332 minstr->SetMachineOperand(op, machineRegNum);
333 else if (opType == MachineOperand::MO_VirtualRegister)
334 constantThatMustBeLoaded = true; // load is generated below
336 minstr->SetMachineOperand(op, opType, immedValue);
338 if (constantThatMustBeLoaded)
339 { // register the value so it is emitted in the assembly
340 MachineCodeForMethod::get(method).addToConstantPool(
341 cast<ConstPoolVal>(opValue));
345 if (constantThatMustBeLoaded || isa<GlobalValue>(opValue))
346 { // opValue is a constant that must be explicitly loaded into a reg.
347 TmpInstruction* tmpReg = InsertCodeToLoadConstant(opValue, vmInstr,
348 loadConstVec, target);
349 minstr->SetMachineOperand(op, MachineOperand::MO_VirtualRegister,
355 // Also, check for implicit operands used (not those defined) by the
356 // machine instruction. These include:
357 // -- arguments to a Call
358 // -- return value of a Return
359 // Any such operand that is a constant value needs to be fixed also.
360 // The current instructions with implicit refs (viz., Call and Return)
361 // have no immediate fields, so the constant always needs to be loaded
364 for (unsigned i=0, N=minstr->getNumImplicitRefs(); i < N; ++i)
365 if (isa<ConstPoolVal>(minstr->getImplicitRef(i)) ||
366 isa<GlobalValue>(minstr->getImplicitRef(i)))
368 Value* oldVal = minstr->getImplicitRef(i);
369 TmpInstruction* tmpReg =
370 InsertCodeToLoadConstant(oldVal, vmInstr, loadConstVec, target);
371 minstr->setImplicitRef(i, tmpReg);
373 if (isa<ConstPoolVal>(oldVal))
374 { // register the value so it is emitted in the assembly
375 MachineCodeForMethod::get(method).addToConstantPool(
376 cast<ConstPoolVal>(oldVal));