1 //===-- MSchedGraph.cpp - Scheduling Graph ----------------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // A graph class for dependencies. This graph only contains true, anti, and
11 // output data dependencies for a given MachineBasicBlock. Dependencies
12 // across iterations are also computed. Unless data dependence analysis
13 // is provided, a conservative approach of adding dependencies between all
14 // loads and stores is taken.
15 //===----------------------------------------------------------------------===//
16 #define DEBUG_TYPE "ModuloSched"
18 #include "MSchedGraph.h"
19 #include "../SparcV9RegisterInfo.h"
20 #include "../MachineCodeForInstruction.h"
21 #include "llvm/BasicBlock.h"
22 #include "llvm/Constants.h"
23 #include "llvm/Instructions.h"
24 #include "llvm/Type.h"
25 #include "llvm/CodeGen/MachineBasicBlock.h"
26 #include "llvm/Target/TargetInstrInfo.h"
27 #include "llvm/Support/Debug.h"
34 //MSchedGraphNode constructor
35 MSchedGraphNode::MSchedGraphNode(const MachineInstr* inst,
36 MSchedGraph *graph, unsigned idx,
37 unsigned late, bool isBranch)
38 : Inst(inst), Parent(graph), index(idx), latency(late),
39 isBranchInstr(isBranch) {
42 graph->addNode(inst, this);
45 //MSchedGraphNode copy constructor
46 MSchedGraphNode::MSchedGraphNode(const MSchedGraphNode &N)
47 : Predecessors(N.Predecessors), Successors(N.Successors) {
53 isBranchInstr = N.isBranchInstr;
57 //Print the node (instruction and latency)
58 void MSchedGraphNode::print(std::ostream &os) const {
59 os << "MSchedGraphNode: Inst=" << *Inst << ", latency= " << latency << "\n";
63 //Get the edge from a predecessor to this node
64 MSchedGraphEdge MSchedGraphNode::getInEdge(MSchedGraphNode *pred) {
65 //Loop over all the successors of our predecessor
66 //return the edge the corresponds to this in edge
67 for (MSchedGraphNode::succ_iterator I = pred->succ_begin(),
68 E = pred->succ_end(); I != E; ++I) {
72 assert(0 && "Should have found edge between this node and its predecessor!");
76 //Get the iteration difference for the edge from this node to its successor
77 unsigned MSchedGraphNode::getIteDiff(MSchedGraphNode *succ) {
78 for(std::vector<MSchedGraphEdge>::iterator I = Successors.begin(),
81 if(I->getDest() == succ)
82 return I->getIteDiff();
87 //Get the index into the vector of edges for the edge from pred to this node
88 unsigned MSchedGraphNode::getInEdgeNum(MSchedGraphNode *pred) {
89 //Loop over all the successors of our predecessor
90 //return the edge the corresponds to this in edge
92 for(MSchedGraphNode::succ_iterator I = pred->succ_begin(),
99 assert(0 && "Should have found edge between this node and its predecessor!");
103 //Determine if succ is a successor of this node
104 bool MSchedGraphNode::isSuccessor(MSchedGraphNode *succ) {
105 for(succ_iterator I = succ_begin(), E = succ_end(); I != E; ++I)
111 //Dtermine if pred is a predecessor of this node
112 bool MSchedGraphNode::isPredecessor(MSchedGraphNode *pred) {
113 if(std::find( Predecessors.begin(), Predecessors.end(),
114 pred) != Predecessors.end())
120 //Add a node to the graph
121 void MSchedGraph::addNode(const MachineInstr *MI,
122 MSchedGraphNode *node) {
124 //Make sure node does not already exist
125 assert(GraphMap.find(MI) == GraphMap.end()
126 && "New MSchedGraphNode already exists for this instruction");
131 //Delete a node to the graph
132 void MSchedGraph::deleteNode(MSchedGraphNode *node) {
134 //Delete the edge to this node from all predecessors
135 while(node->pred_size() > 0) {
136 //DEBUG(std::cerr << "Delete edge from: " << **P << " to " << *node << "\n");
137 MSchedGraphNode *pred = *(node->pred_begin());
138 pred->deleteSuccessor(node);
141 //Remove this node from the graph
142 GraphMap.erase(node->getInst());
147 //Create a graph for a machine block. The ignoreInstrs map is so that
148 //we ignore instructions associated to the index variable since this
149 //is a special case in Modulo Scheduling. We only want to deal with
150 //the body of the loop.
151 MSchedGraph::MSchedGraph(const MachineBasicBlock *bb,
152 const TargetMachine &targ,
153 std::map<const MachineInstr*, unsigned> &ignoreInstrs,
154 DependenceAnalyzer &DA,
155 std::map<MachineInstr*, Instruction*> &machineTollvm)
158 //Make sure BB is not null,
159 assert(bb != NULL && "Basic Block is null");
163 //Create nodes and edges for this BB
164 buildNodesAndEdges(ignoreInstrs, DA, machineTollvm);
170 //Copies the graph and keeps a map from old to new nodes
171 MSchedGraph::MSchedGraph(const MSchedGraph &G,
172 std::map<MSchedGraphNode*, MSchedGraphNode*> &newNodes)
177 std::map<MSchedGraphNode*, MSchedGraphNode*> oldToNew;
179 for(MSchedGraph::const_iterator N = G.GraphMap.begin(),
180 NE = G.GraphMap.end(); N != NE; ++N) {
182 MSchedGraphNode *newNode = new MSchedGraphNode(*(N->second));
183 oldToNew[&*(N->second)] = newNode;
184 newNodes[newNode] = &*(N->second);
185 GraphMap[&*(N->first)] = newNode;
188 //Loop over nodes and update edges to point to new nodes
189 for(MSchedGraph::iterator N = GraphMap.begin(), NE = GraphMap.end();
192 //Get the node we are dealing with
193 MSchedGraphNode *node = &*(N->second);
195 node->setParent(this);
197 //Loop over nodes successors and predecessors and update to the new nodes
198 for(unsigned i = 0; i < node->pred_size(); ++i) {
199 node->setPredecessor(i, oldToNew[node->getPredecessor(i)]);
202 for(unsigned i = 0; i < node->succ_size(); ++i) {
203 MSchedGraphEdge *edge = node->getSuccessor(i);
204 MSchedGraphNode *oldDest = edge->getDest();
205 edge->setDest(oldToNew[oldDest]);
210 //Deconstructor, deletes all nodes in the graph
211 MSchedGraph::~MSchedGraph () {
212 for(MSchedGraph::iterator I = GraphMap.begin(), E = GraphMap.end();
218 void MSchedGraph::print(std::ostream &os) const {
219 for(MSchedGraph::const_iterator N = GraphMap.begin(), NE = GraphMap.end();
222 //Get the node we are dealing with
223 MSchedGraphNode *node = &*(N->second);
225 os << "Node Start\n";
227 os << "Successors:\n";
229 for(unsigned i = 0; i < node->succ_size(); ++i) {
230 MSchedGraphEdge *edge = node->getSuccessor(i);
231 MSchedGraphNode *oldDest = edge->getDest();
238 //Calculate total delay
239 int MSchedGraph::totalDelay() {
242 for(MSchedGraph::const_iterator N = GraphMap.begin(), NE = GraphMap.end();
245 //Get the node we are dealing with
246 MSchedGraphNode *node = &*(N->second);
247 sum += node->getLatency();
251 //Experimental code to add edges from the branch to all nodes dependent upon it.
252 void hasPath(MSchedGraphNode *node, std::set<MSchedGraphNode*> &visited,
253 std::set<MSchedGraphNode*> &branches, MSchedGraphNode *startNode,
254 std::set<std::pair<MSchedGraphNode*,MSchedGraphNode*> > &newEdges ) {
256 visited.insert(node);
257 DEBUG(std::cerr << "Visiting: " << *node << "\n");
258 //Loop over successors
259 for(unsigned i = 0; i < node->succ_size(); ++i) {
260 MSchedGraphEdge *edge = node->getSuccessor(i);
261 MSchedGraphNode *dest = edge->getDest();
262 if(branches.count(dest))
263 newEdges.insert(std::make_pair(dest, startNode));
265 //only visit if we have not already
266 else if(!visited.count(dest)) {
267 if(edge->getIteDiff() == 0)
268 hasPath(dest, visited, branches, startNode, newEdges);}
274 //Experimental code to add edges from the branch to all nodes dependent upon it.
275 void MSchedGraph::addBranchEdges() {
276 std::set<MSchedGraphNode*> branches;
277 std::set<MSchedGraphNode*> nodes;
279 for(MSchedGraph::iterator I = GraphMap.begin(), E = GraphMap.end();
281 if(I->second->isBranch())
282 if(I->second->hasPredecessors())
283 branches.insert(I->second);
286 //See if there is a path first instruction to the branches, if so, add an
287 //iteration dependence between that node and the branch
288 std::set<std::pair<MSchedGraphNode*, MSchedGraphNode*> > newEdges;
289 for(MSchedGraph::iterator I = GraphMap.begin(), E = GraphMap.end();
291 std::set<MSchedGraphNode*> visited;
292 hasPath((I->second), visited, branches, (I->second), newEdges);
295 //Spit out all edges we are going to add
296 unsigned min = GraphMap.size();
297 if(newEdges.size() == 1) {
298 ((newEdges.begin())->first)->addOutEdge(((newEdges.begin())->second),
299 MSchedGraphEdge::BranchDep,
300 MSchedGraphEdge::NonDataDep, 1);
305 MSchedGraphNode *start;
306 MSchedGraphNode *end;
307 for(std::set<std::pair<MSchedGraphNode*, MSchedGraphNode*> >::iterator I = newEdges.begin(), E = newEdges.end(); I != E; ++I) {
309 DEBUG(std::cerr << "Branch Edge from: " << *(I->first) << " to " << *(I->second) << "\n");
311 // if(I->second->getIndex() <= min) {
314 //min = I->second->getIndex();
316 start->addOutEdge(end,
317 MSchedGraphEdge::BranchDep,
318 MSchedGraphEdge::NonDataDep, 1);
324 //Add edges between the nodes
325 void MSchedGraph::buildNodesAndEdges(std::map<const MachineInstr*, unsigned> &ignoreInstrs,
326 DependenceAnalyzer &DA,
327 std::map<MachineInstr*, Instruction*> &machineTollvm) {
330 //Get Machine target information for calculating latency
331 const TargetInstrInfo *MTI = Target.getInstrInfo();
333 std::vector<MSchedGraphNode*> memInstructions;
334 std::map<int, std::vector<OpIndexNodePair> > regNumtoNodeMap;
335 std::map<const Value*, std::vector<OpIndexNodePair> > valuetoNodeMap;
337 //Save PHI instructions to deal with later
338 std::vector<const MachineInstr*> phiInstrs;
341 for(std::vector<const MachineBasicBlock*>::iterator B = BBs.begin(),
342 BE = BBs.end(); B != BE; ++B) {
344 const MachineBasicBlock *BB = *B;
346 //Loop over instructions in MBB and add nodes and edges
347 for (MachineBasicBlock::const_iterator MI = BB->begin(), e = BB->end();
350 //Ignore indvar instructions
351 if(ignoreInstrs.count(MI)) {
356 //Get each instruction of machine basic block, get the delay
357 //using the op code, create a new node for it, and add to the
360 MachineOpCode opCode = MI->getOpcode();
363 #if 0 // FIXME: LOOK INTO THIS
364 //Check if subsequent instructions can be issued before
365 //the result is ready, if so use min delay.
366 if(MTI->hasResultInterlock(MIopCode))
367 delay = MTI->minLatency(MIopCode);
371 delay = MTI->maxLatency(opCode);
373 //Create new node for this machine instruction and add to the graph.
374 //Create only if not a nop
375 if(MTI->isNop(opCode))
378 //Sparc BE does not use PHI opcode, so assert on this case
379 assert(opCode != TargetInstrInfo::PHI && "Did not expect PHI opcode");
381 bool isBranch = false;
383 //We want to flag the branch node to treat it special
384 if(MTI->isBranch(opCode))
387 //Node is created and added to the graph automatically
388 MSchedGraphNode *node = new MSchedGraphNode(MI, this, index, delay,
391 DEBUG(std::cerr << "Created Node: " << *node << "\n");
393 //Check OpCode to keep track of memory operations to add memory
394 //dependencies later.
395 if(MTI->isLoad(opCode) || MTI->isStore(opCode))
396 memInstructions.push_back(node);
398 //Loop over all operands, and put them into the register number to
399 //graph node map for determining dependencies
400 //If an operands is a use/def, we have an anti dependence to itself
401 for(unsigned i=0; i < MI->getNumOperands(); ++i) {
403 const MachineOperand &mOp = MI->getOperand(i);
405 //Check if it has an allocated register
406 if(mOp.hasAllocatedReg()) {
407 int regNum = mOp.getReg();
409 if(regNum != SparcV9::g0) {
411 regNumtoNodeMap[regNum].push_back(std::make_pair(i, node));
417 //Add virtual registers dependencies
418 //Check if any exist in the value map already and create dependencies
420 if(mOp.getType() == MachineOperand::MO_VirtualRegister
421 || mOp.getType() == MachineOperand::MO_CCRegister) {
423 //Make sure virtual register value is not null
424 assert((mOp.getVRegValue() != NULL) && "Null value is defined");
426 //Check if this is a read operation in a phi node, if so DO NOT PROCESS
427 if(mOp.isUse() && (opCode == TargetInstrInfo::PHI)) {
428 DEBUG(std::cerr << "Read Operation in a PHI node\n");
432 if (const Value* srcI = mOp.getVRegValue()) {
434 //Find value in the map
435 std::map<const Value*, std::vector<OpIndexNodePair> >::iterator V
436 = valuetoNodeMap.find(srcI);
438 //If there is something in the map already, add edges from
440 //to this one we are processing
441 if(V != valuetoNodeMap.end()) {
442 addValueEdges(V->second, node, mOp.isUse(), mOp.isDef(), phiInstrs);
445 V->second.push_back(std::make_pair(i,node));
447 //Otherwise put it in the map
450 valuetoNodeMap[mOp.getVRegValue()].push_back(std::make_pair(i, node));
457 //Loop over LLVM BB, examine phi instructions, and add them to our
458 //phiInstr list to process
459 const BasicBlock *llvm_bb = BB->getBasicBlock();
460 for(BasicBlock::const_iterator I = llvm_bb->begin(), E = llvm_bb->end();
462 if(const PHINode *PN = dyn_cast<PHINode>(I)) {
463 MachineCodeForInstruction & tempMvec = MachineCodeForInstruction::get(PN);
464 for (unsigned j = 0; j < tempMvec.size(); j++) {
465 if(!ignoreInstrs.count(tempMvec[j])) {
466 DEBUG(std::cerr << "Inserting phi instr into map: " << *tempMvec[j] << "\n");
467 phiInstrs.push_back((MachineInstr*) tempMvec[j]);
474 addMemEdges(memInstructions, DA, machineTollvm);
475 addMachRegEdges(regNumtoNodeMap);
477 //Finally deal with PHI Nodes and Value*
478 for(std::vector<const MachineInstr*>::iterator I = phiInstrs.begin(),
479 E = phiInstrs.end(); I != E; ++I) {
481 //Get Node for this instruction
482 std::map<const MachineInstr*, MSchedGraphNode*>::iterator X;
485 if(X == GraphMap.end())
488 MSchedGraphNode *node = X->second;
490 DEBUG(std::cerr << "Adding ite diff edges for node: " << *node << "\n");
492 //Loop over operands for this instruction and add value edges
493 for(unsigned i=0; i < (*I)->getNumOperands(); ++i) {
495 const MachineOperand &mOp = (*I)->getOperand(i);
496 if((mOp.getType() == MachineOperand::MO_VirtualRegister
497 || mOp.getType() == MachineOperand::MO_CCRegister) && mOp.isUse()) {
499 //find the value in the map
500 if (const Value* srcI = mOp.getVRegValue()) {
502 //Find value in the map
503 std::map<const Value*, std::vector<OpIndexNodePair> >::iterator V
504 = valuetoNodeMap.find(srcI);
506 //If there is something in the map already, add edges from
508 //to this one we are processing
509 if(V != valuetoNodeMap.end()) {
510 addValueEdges(V->second, node, mOp.isUse(), mOp.isDef(),
519 //Add dependencies for Value*s
520 void MSchedGraph::addValueEdges(std::vector<OpIndexNodePair> &NodesInMap,
521 MSchedGraphNode *destNode, bool nodeIsUse,
522 bool nodeIsDef, std::vector<const MachineInstr*> &phiInstrs, int diff) {
524 for(std::vector<OpIndexNodePair>::iterator I = NodesInMap.begin(),
525 E = NodesInMap.end(); I != E; ++I) {
527 //Get node in vectors machine operand that is the same value as node
528 MSchedGraphNode *srcNode = I->second;
529 MachineOperand mOp = srcNode->getInst()->getOperand(I->first);
532 if(std::find(phiInstrs.begin(), phiInstrs.end(), srcNode->getInst()) == phiInstrs.end())
535 //Node is a Def, so add output dep.
538 DEBUG(std::cerr << "Edge from " << *srcNode << " to " << *destNode << " (itediff=" << diff << ", type=anti)\n");
539 srcNode->addOutEdge(destNode, MSchedGraphEdge::ValueDep,
540 MSchedGraphEdge::AntiDep, diff);
543 DEBUG(std::cerr << "Edge from " << *srcNode << " to " << *destNode << " (itediff=" << diff << ", type=output)\n");
544 srcNode->addOutEdge(destNode, MSchedGraphEdge::ValueDep,
545 MSchedGraphEdge::OutputDep, diff);
550 DEBUG(std::cerr << "Edge from " << *srcNode << " to " << *destNode << " (itediff=" << diff << ", type=true)\n");
551 srcNode->addOutEdge(destNode, MSchedGraphEdge::ValueDep,
552 MSchedGraphEdge::TrueDep, diff);
558 //Add dependencies for machine registers across iterations
559 void MSchedGraph::addMachRegEdges(std::map<int, std::vector<OpIndexNodePair> >& regNumtoNodeMap) {
560 //Loop over all machine registers in the map, and add dependencies
561 //between the instructions that use it
562 typedef std::map<int, std::vector<OpIndexNodePair> > regNodeMap;
563 for(regNodeMap::iterator I = regNumtoNodeMap.begin();
564 I != regNumtoNodeMap.end(); ++I) {
565 //Get the register number
566 int regNum = (*I).first;
568 //Get Vector of nodes that use this register
569 std::vector<OpIndexNodePair> Nodes = (*I).second;
571 //Loop over nodes and determine the dependence between the other
572 //nodes in the vector
573 for(unsigned i =0; i < Nodes.size(); ++i) {
575 //Get src node operator index that uses this machine register
576 int srcOpIndex = Nodes[i].first;
578 //Get the actual src Node
579 MSchedGraphNode *srcNode = Nodes[i].second;
582 const MachineOperand &srcMOp = srcNode->getInst()->getOperand(srcOpIndex);
584 bool srcIsUseandDef = srcMOp.isDef() && srcMOp.isUse();
585 bool srcIsUse = srcMOp.isUse() && !srcMOp.isDef();
588 //Look at all instructions after this in execution order
589 for(unsigned j=i+1; j < Nodes.size(); ++j) {
591 //Sink node is a write
592 if(Nodes[j].second->getInst()->getOperand(Nodes[j].first).isDef()) {
593 //Src only uses the register (read)
595 srcNode->addOutEdge(Nodes[j].second,
596 MSchedGraphEdge::MachineRegister,
597 MSchedGraphEdge::AntiDep);
599 else if(srcIsUseandDef) {
600 srcNode->addOutEdge(Nodes[j].second,
601 MSchedGraphEdge::MachineRegister,
602 MSchedGraphEdge::AntiDep);
604 srcNode->addOutEdge(Nodes[j].second,
605 MSchedGraphEdge::MachineRegister,
606 MSchedGraphEdge::OutputDep);
609 srcNode->addOutEdge(Nodes[j].second,
610 MSchedGraphEdge::MachineRegister,
611 MSchedGraphEdge::OutputDep);
613 //Dest node is a read
615 if(!srcIsUse || srcIsUseandDef)
616 srcNode->addOutEdge(Nodes[j].second,
617 MSchedGraphEdge::MachineRegister,
618 MSchedGraphEdge::TrueDep);
623 //Look at all the instructions before this one since machine registers
624 //could live across iterations.
625 for(unsigned j = 0; j < i; ++j) {
626 //Sink node is a write
627 if(Nodes[j].second->getInst()->getOperand(Nodes[j].first).isDef()) {
628 //Src only uses the register (read)
630 srcNode->addOutEdge(Nodes[j].second,
631 MSchedGraphEdge::MachineRegister,
632 MSchedGraphEdge::AntiDep, 1);
633 else if(srcIsUseandDef) {
634 srcNode->addOutEdge(Nodes[j].second,
635 MSchedGraphEdge::MachineRegister,
636 MSchedGraphEdge::AntiDep, 1);
638 srcNode->addOutEdge(Nodes[j].second,
639 MSchedGraphEdge::MachineRegister,
640 MSchedGraphEdge::OutputDep, 1);
643 srcNode->addOutEdge(Nodes[j].second,
644 MSchedGraphEdge::MachineRegister,
645 MSchedGraphEdge::OutputDep, 1);
647 //Dest node is a read
649 if(!srcIsUse || srcIsUseandDef)
650 srcNode->addOutEdge(Nodes[j].second,
651 MSchedGraphEdge::MachineRegister,
652 MSchedGraphEdge::TrueDep,1 );
664 //Add edges between all loads and stores
665 //Can be less strict with alias analysis and data dependence analysis.
666 void MSchedGraph::addMemEdges(const std::vector<MSchedGraphNode*>& memInst,
667 DependenceAnalyzer &DA,
668 std::map<MachineInstr*, Instruction*> &machineTollvm) {
670 //Get Target machine instruction info
671 const TargetInstrInfo *TMI = Target.getInstrInfo();
673 //Loop over all memory instructions in the vector
674 //Knowing that they are in execution, add true, anti, and output dependencies
675 for (unsigned srcIndex = 0; srcIndex < memInst.size(); ++srcIndex) {
677 MachineInstr *srcInst = (MachineInstr*) memInst[srcIndex]->getInst();
679 //Get the machine opCode to determine type of memory instruction
680 MachineOpCode srcNodeOpCode = srcInst->getOpcode();
682 //All instructions after this one in execution order have an
683 //iteration delay of 0
684 for(unsigned destIndex = 0; destIndex < memInst.size(); ++destIndex) {
687 if(destIndex == srcIndex)
690 MachineInstr *destInst = (MachineInstr*) memInst[destIndex]->getInst();
692 DEBUG(std::cerr << "MInst1: " << *srcInst << "\n");
693 DEBUG(std::cerr << "MInst2: " << *destInst << "\n");
695 //Assuming instructions without corresponding llvm instructions
696 //are from constant pools.
697 if (!machineTollvm.count(srcInst) || !machineTollvm.count(destInst))
700 bool useDepAnalyzer = true;
702 //Some machine loads and stores are generated by casts, so be
703 //conservative and always add deps
704 Instruction *srcLLVM = machineTollvm[srcInst];
705 Instruction *destLLVM = machineTollvm[destInst];
706 if(!isa<LoadInst>(srcLLVM)
707 && !isa<StoreInst>(srcLLVM)) {
708 if(isa<BinaryOperator>(srcLLVM)) {
709 if(isa<ConstantFP>(srcLLVM->getOperand(0)) || isa<ConstantFP>(srcLLVM->getOperand(1)))
712 useDepAnalyzer = false;
714 if(!isa<LoadInst>(destLLVM)
715 && !isa<StoreInst>(destLLVM)) {
716 if(isa<BinaryOperator>(destLLVM)) {
717 if(isa<ConstantFP>(destLLVM->getOperand(0)) || isa<ConstantFP>(destLLVM->getOperand(1)))
720 useDepAnalyzer = false;
723 //Use dep analysis when we have corresponding llvm loads/stores
725 bool srcBeforeDest = true;
726 if(destIndex < srcIndex)
727 srcBeforeDest = false;
729 DependenceResult dr = DA.getDependenceInfo(machineTollvm[srcInst],
730 machineTollvm[destInst],
733 for(std::vector<Dependence>::iterator d = dr.dependences.begin(),
734 de = dr.dependences.end(); d != de; ++d) {
735 //Add edge from load to store
736 memInst[srcIndex]->addOutEdge(memInst[destIndex],
737 MSchedGraphEdge::MemoryDep,
738 d->getDepType(), d->getIteDiff());
742 //Otherwise, we can not do any further analysis and must make a dependence
745 //Get the machine opCode to determine type of memory instruction
746 MachineOpCode destNodeOpCode = destInst->getOpcode();
748 //Get the Value* that we are reading from the load, always the first op
749 const MachineOperand &mOp = srcInst->getOperand(0);
750 const MachineOperand &mOp2 = destInst->getOperand(0);
752 if(mOp.hasAllocatedReg())
753 if(mOp.getReg() == SparcV9::g0)
755 if(mOp2.hasAllocatedReg())
756 if(mOp2.getReg() == SparcV9::g0)
759 DEBUG(std::cerr << "Adding dependence for machine instructions\n");
761 if(TMI->isLoad(srcNodeOpCode)) {
763 if(TMI->isStore(destNodeOpCode))
764 memInst[srcIndex]->addOutEdge(memInst[destIndex],
765 MSchedGraphEdge::MemoryDep,
766 MSchedGraphEdge::AntiDep, 0);
768 else if(TMI->isStore(srcNodeOpCode)) {
769 if(TMI->isStore(destNodeOpCode))
770 memInst[srcIndex]->addOutEdge(memInst[destIndex],
771 MSchedGraphEdge::MemoryDep,
772 MSchedGraphEdge::OutputDep, 0);
775 memInst[srcIndex]->addOutEdge(memInst[destIndex],
776 MSchedGraphEdge::MemoryDep,
777 MSchedGraphEdge::TrueDep, 0);