1 //===-- PhyRegAlloc.cpp ---------------------------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Traditional graph-coloring global register allocator currently used
11 // by the SPARC back-end.
13 // NOTE: This register allocator has some special support
14 // for the Reoptimizer, such as not saving some registers on calls to
15 // the first-level instrumentation function.
17 // NOTE 2: This register allocator can save its state in a global
18 // variable in the module it's working on. This feature is not
19 // thread-safe; if you have doubts, leave it turned off.
21 //===----------------------------------------------------------------------===//
23 #include "PhyRegAlloc.h"
24 #include "RegAllocCommon.h"
27 #include "llvm/CodeGen/FunctionLiveVarInfo.h"
28 #include "llvm/CodeGen/InstrSelection.h"
29 #include "llvm/CodeGen/MachineInstr.h"
30 #include "llvm/CodeGen/MachineInstrBuilder.h"
31 #include "llvm/CodeGen/MachineInstrAnnot.h"
32 #include "llvm/CodeGen/MachineFunction.h"
33 #include "llvm/CodeGen/MachineFunctionInfo.h"
34 #include "llvm/CodeGen/Passes.h"
35 #include "llvm/Analysis/LoopInfo.h"
36 #include "llvm/Target/TargetInstrInfo.h"
37 #include "llvm/Type.h"
38 #include "llvm/iOther.h"
39 #include "llvm/DerivedTypes.h"
40 #include "llvm/Constants.h"
41 #include "llvm/Module.h"
42 #include "llvm/Support/InstIterator.h"
43 #include "Support/STLExtras.h"
44 #include "Support/SetOperations.h"
45 #include "Support/CommandLine.h"
48 RegAllocDebugLevel_t DEBUG_RA;
50 static cl::opt<RegAllocDebugLevel_t, true>
51 DRA_opt("dregalloc", cl::Hidden, cl::location(DEBUG_RA),
52 cl::desc("enable register allocation debugging information"),
54 clEnumValN(RA_DEBUG_None , "n", "disable debug output"),
55 clEnumValN(RA_DEBUG_Results, "y", "debug output for allocation results"),
56 clEnumValN(RA_DEBUG_Coloring, "c", "debug output for graph coloring step"),
57 clEnumValN(RA_DEBUG_Interference,"ig","debug output for interference graphs"),
58 clEnumValN(RA_DEBUG_LiveRanges , "lr","debug output for live ranges"),
59 clEnumValN(RA_DEBUG_Verbose, "v", "extra debug output"),
63 SaveRegAllocState("save-ra-state", cl::Hidden,
64 cl::desc("write reg. allocator state into module"));
66 FunctionPass *getRegisterAllocator(TargetMachine &T) {
67 return new PhyRegAlloc (T);
70 void PhyRegAlloc::getAnalysisUsage(AnalysisUsage &AU) const {
71 AU.addRequired<LoopInfo> ();
72 AU.addRequired<FunctionLiveVarInfo> ();
77 //----------------------------------------------------------------------------
78 // This method initially creates interference graphs (one in each reg class)
79 // and IGNodeList (one in each IG). The actual nodes will be pushed later.
80 //----------------------------------------------------------------------------
81 void PhyRegAlloc::createIGNodeListsAndIGs() {
82 if (DEBUG_RA >= RA_DEBUG_LiveRanges) std::cerr << "Creating LR lists ...\n";
85 LiveRangeMapType::const_iterator HMI = LRI->getLiveRangeMap()->begin();
88 LiveRangeMapType::const_iterator HMIEnd = LRI->getLiveRangeMap()->end();
90 for (; HMI != HMIEnd ; ++HMI ) {
92 LiveRange *L = HMI->second; // get the LiveRange
95 std::cerr << "\n**** ?!?WARNING: NULL LIVE RANGE FOUND FOR: "
96 << RAV(HMI->first) << "****\n";
100 // if the Value * is not null, and LR is not yet written to the IGNodeList
101 if (!(L->getUserIGNode()) ) {
102 RegClass *const RC = // RegClass of first value in the LR
103 RegClassList[ L->getRegClassID() ];
104 RC->addLRToIG(L); // add this LR to an IG
110 for ( unsigned rc=0; rc < NumOfRegClasses ; rc++)
111 RegClassList[rc]->createInterferenceGraph();
113 if (DEBUG_RA >= RA_DEBUG_LiveRanges) std::cerr << "LRLists Created!\n";
117 //----------------------------------------------------------------------------
118 // This method will add all interferences at for a given instruction.
119 // Interference occurs only if the LR of Def (Inst or Arg) is of the same reg
120 // class as that of live var. The live var passed to this function is the
121 // LVset AFTER the instruction
122 //----------------------------------------------------------------------------
124 void PhyRegAlloc::addInterference(const Value *Def,
125 const ValueSet *LVSet,
127 ValueSet::const_iterator LIt = LVSet->begin();
129 // get the live range of instruction
130 const LiveRange *const LROfDef = LRI->getLiveRangeForValue( Def );
132 IGNode *const IGNodeOfDef = LROfDef->getUserIGNode();
133 assert( IGNodeOfDef );
135 RegClass *const RCOfDef = LROfDef->getRegClass();
137 // for each live var in live variable set
138 for ( ; LIt != LVSet->end(); ++LIt) {
140 if (DEBUG_RA >= RA_DEBUG_Verbose)
141 std::cerr << "< Def=" << RAV(Def) << ", Lvar=" << RAV(*LIt) << "> ";
143 // get the live range corresponding to live var
144 LiveRange *LROfVar = LRI->getLiveRangeForValue(*LIt);
146 // LROfVar can be null if it is a const since a const
147 // doesn't have a dominating def - see Assumptions above
149 if (LROfDef != LROfVar) // do not set interf for same LR
150 if (RCOfDef == LROfVar->getRegClass()) // 2 reg classes are the same
151 RCOfDef->setInterference( LROfDef, LROfVar);
156 //----------------------------------------------------------------------------
157 // For a call instruction, this method sets the CallInterference flag in
158 // the LR of each variable live int the Live Variable Set live after the
159 // call instruction (except the return value of the call instruction - since
160 // the return value does not interfere with that call itself).
161 //----------------------------------------------------------------------------
163 void PhyRegAlloc::setCallInterferences(const MachineInstr *MInst,
164 const ValueSet *LVSetAft) {
165 if (DEBUG_RA >= RA_DEBUG_Interference)
166 std::cerr << "\n For call inst: " << *MInst;
168 // for each live var in live variable set after machine inst
169 for (ValueSet::const_iterator LIt = LVSetAft->begin(), LEnd = LVSetAft->end();
170 LIt != LEnd; ++LIt) {
172 // get the live range corresponding to live var
173 LiveRange *const LR = LRI->getLiveRangeForValue(*LIt );
175 // LR can be null if it is a const since a const
176 // doesn't have a dominating def - see Assumptions above
178 if (DEBUG_RA >= RA_DEBUG_Interference) {
179 std::cerr << "\n\tLR after Call: ";
182 LR->setCallInterference();
183 if (DEBUG_RA >= RA_DEBUG_Interference) {
184 std::cerr << "\n ++After adding call interference for LR: " ;
191 // Now find the LR of the return value of the call
192 // We do this because, we look at the LV set *after* the instruction
193 // to determine, which LRs must be saved across calls. The return value
194 // of the call is live in this set - but it does not interfere with call
195 // (i.e., we can allocate a volatile register to the return value)
196 CallArgsDescriptor* argDesc = CallArgsDescriptor::get(MInst);
198 if (const Value *RetVal = argDesc->getReturnValue()) {
199 LiveRange *RetValLR = LRI->getLiveRangeForValue( RetVal );
200 assert( RetValLR && "No LR for RetValue of call");
201 RetValLR->clearCallInterference();
204 // If the CALL is an indirect call, find the LR of the function pointer.
205 // That has a call interference because it conflicts with outgoing args.
206 if (const Value *AddrVal = argDesc->getIndirectFuncPtr()) {
207 LiveRange *AddrValLR = LRI->getLiveRangeForValue( AddrVal );
208 assert( AddrValLR && "No LR for indirect addr val of call");
209 AddrValLR->setCallInterference();
214 //----------------------------------------------------------------------------
215 // This method will walk thru code and create interferences in the IG of
216 // each RegClass. Also, this method calculates the spill cost of each
217 // Live Range (it is done in this method to save another pass over the code).
218 //----------------------------------------------------------------------------
220 void PhyRegAlloc::buildInterferenceGraphs()
222 if (DEBUG_RA >= RA_DEBUG_Interference)
223 std::cerr << "Creating interference graphs ...\n";
225 unsigned BBLoopDepthCost;
226 for (MachineFunction::iterator BBI = MF->begin(), BBE = MF->end();
228 const MachineBasicBlock &MBB = *BBI;
229 const BasicBlock *BB = MBB.getBasicBlock();
231 // find the 10^(loop_depth) of this BB
232 BBLoopDepthCost = (unsigned)pow(10.0, LoopDepthCalc->getLoopDepth(BB));
234 // get the iterator for machine instructions
235 MachineBasicBlock::const_iterator MII = MBB.begin();
237 // iterate over all the machine instructions in BB
238 for ( ; MII != MBB.end(); ++MII) {
239 const MachineInstr *MInst = *MII;
241 // get the LV set after the instruction
242 const ValueSet &LVSetAI = LVI->getLiveVarSetAfterMInst(MInst, BB);
243 bool isCallInst = TM.getInstrInfo().isCall(MInst->getOpCode());
246 // set the isCallInterference flag of each live range which extends
247 // across this call instruction. This information is used by graph
248 // coloring algorithm to avoid allocating volatile colors to live ranges
249 // that span across calls (since they have to be saved/restored)
250 setCallInterferences(MInst, &LVSetAI);
253 // iterate over all MI operands to find defs
254 for (MachineInstr::const_val_op_iterator OpI = MInst->begin(),
255 OpE = MInst->end(); OpI != OpE; ++OpI) {
256 if (OpI.isDefOnly() || OpI.isDefAndUse()) // create a new LR since def
257 addInterference(*OpI, &LVSetAI, isCallInst);
259 // Calculate the spill cost of each live range
260 LiveRange *LR = LRI->getLiveRangeForValue(*OpI);
261 if (LR) LR->addSpillCost(BBLoopDepthCost);
264 // if there are multiple defs in this instruction e.g. in SETX
265 if (TM.getInstrInfo().isPseudoInstr(MInst->getOpCode()))
266 addInterf4PseudoInstr(MInst);
268 // Also add interference for any implicit definitions in a machine
269 // instr (currently, only calls have this).
270 unsigned NumOfImpRefs = MInst->getNumImplicitRefs();
271 for (unsigned z=0; z < NumOfImpRefs; z++)
272 if (MInst->getImplicitOp(z).opIsDefOnly() ||
273 MInst->getImplicitOp(z).opIsDefAndUse())
274 addInterference( MInst->getImplicitRef(z), &LVSetAI, isCallInst );
276 } // for all machine instructions in BB
277 } // for all BBs in function
279 // add interferences for function arguments. Since there are no explicit
280 // defs in the function for args, we have to add them manually
281 addInterferencesForArgs();
283 if (DEBUG_RA >= RA_DEBUG_Interference)
284 std::cerr << "Interference graphs calculated!\n";
288 //--------------------------------------------------------------------------
289 // Pseudo-instructions may be expanded to multiple instructions by the
290 // assembler. Consequently, all the operands must get distinct registers.
291 // Therefore, we mark all operands of a pseudo-instruction as interfering
293 //--------------------------------------------------------------------------
295 void PhyRegAlloc::addInterf4PseudoInstr(const MachineInstr *MInst) {
296 bool setInterf = false;
298 // iterate over MI operands to find defs
299 for (MachineInstr::const_val_op_iterator It1 = MInst->begin(),
300 ItE = MInst->end(); It1 != ItE; ++It1) {
301 const LiveRange *LROfOp1 = LRI->getLiveRangeForValue(*It1);
302 assert((LROfOp1 || !It1.isUseOnly())&&"No LR for Def in PSEUDO insruction");
304 MachineInstr::const_val_op_iterator It2 = It1;
305 for (++It2; It2 != ItE; ++It2) {
306 const LiveRange *LROfOp2 = LRI->getLiveRangeForValue(*It2);
309 RegClass *RCOfOp1 = LROfOp1->getRegClass();
310 RegClass *RCOfOp2 = LROfOp2->getRegClass();
312 if (RCOfOp1 == RCOfOp2 ){
313 RCOfOp1->setInterference( LROfOp1, LROfOp2 );
317 } // for all other defs in machine instr
318 } // for all operands in an instruction
320 if (!setInterf && MInst->getNumOperands() > 2) {
321 std::cerr << "\nInterf not set for any operand in pseudo instr:\n";
323 assert(0 && "Interf not set for pseudo instr with > 2 operands" );
328 //----------------------------------------------------------------------------
329 // This method adds interferences for incoming arguments to a function.
330 //----------------------------------------------------------------------------
332 void PhyRegAlloc::addInterferencesForArgs() {
333 // get the InSet of root BB
334 const ValueSet &InSet = LVI->getInSetOfBB(&Fn->front());
336 for (Function::const_aiterator AI = Fn->abegin(); AI != Fn->aend(); ++AI) {
337 // add interferences between args and LVars at start
338 addInterference(AI, &InSet, false);
340 if (DEBUG_RA >= RA_DEBUG_Interference)
341 std::cerr << " - %% adding interference for argument " << RAV(AI) << "\n";
346 //----------------------------------------------------------------------------
347 // This method is called after register allocation is complete to set the
348 // allocated registers in the machine code. This code will add register numbers
349 // to MachineOperands that contain a Value. Also it calls target specific
350 // methods to produce caller saving instructions. At the end, it adds all
351 // additional instructions produced by the register allocator to the
352 // instruction stream.
353 //----------------------------------------------------------------------------
355 //-----------------------------
356 // Utility functions used below
357 //-----------------------------
359 InsertBefore(MachineInstr* newMI,
360 MachineBasicBlock& MBB,
361 MachineBasicBlock::iterator& MII)
363 MII = MBB.insert(MII, newMI);
368 InsertAfter(MachineInstr* newMI,
369 MachineBasicBlock& MBB,
370 MachineBasicBlock::iterator& MII)
372 ++MII; // insert before the next instruction
373 MII = MBB.insert(MII, newMI);
377 DeleteInstruction(MachineBasicBlock& MBB,
378 MachineBasicBlock::iterator& MII)
380 MII = MBB.erase(MII);
384 SubstituteInPlace(MachineInstr* newMI,
385 MachineBasicBlock& MBB,
386 MachineBasicBlock::iterator MII)
392 PrependInstructions(std::vector<MachineInstr *> &IBef,
393 MachineBasicBlock& MBB,
394 MachineBasicBlock::iterator& MII,
395 const std::string& msg)
399 MachineInstr* OrigMI = *MII;
400 std::vector<MachineInstr *>::iterator AdIt;
401 for (AdIt = IBef.begin(); AdIt != IBef.end() ; ++AdIt)
404 if (OrigMI) std::cerr << "For MInst:\n " << *OrigMI;
405 std::cerr << msg << "PREPENDed instr:\n " << **AdIt << "\n";
407 InsertBefore(*AdIt, MBB, MII);
413 AppendInstructions(std::vector<MachineInstr *> &IAft,
414 MachineBasicBlock& MBB,
415 MachineBasicBlock::iterator& MII,
416 const std::string& msg)
420 MachineInstr* OrigMI = *MII;
421 std::vector<MachineInstr *>::iterator AdIt;
422 for ( AdIt = IAft.begin(); AdIt != IAft.end() ; ++AdIt )
425 if (OrigMI) std::cerr << "For MInst:\n " << *OrigMI;
426 std::cerr << msg << "APPENDed instr:\n " << **AdIt << "\n";
428 InsertAfter(*AdIt, MBB, MII);
433 bool PhyRegAlloc::markAllocatedRegs(MachineInstr* MInst)
435 bool instrNeedsSpills = false;
437 // First, set the registers for operands in the machine instruction
438 // if a register was successfully allocated. Do this first because we
439 // will need to know which registers are already used by this instr'n.
440 for (unsigned OpNum=0; OpNum < MInst->getNumOperands(); ++OpNum)
442 MachineOperand& Op = MInst->getOperand(OpNum);
443 if (Op.getType() == MachineOperand::MO_VirtualRegister ||
444 Op.getType() == MachineOperand::MO_CCRegister)
446 const Value *const Val = Op.getVRegValue();
447 if (const LiveRange* LR = LRI->getLiveRangeForValue(Val)) {
448 // Remember if any operand needs spilling
449 instrNeedsSpills |= LR->isMarkedForSpill();
451 // An operand may have a color whether or not it needs spilling
453 MInst->SetRegForOperand(OpNum,
454 MRI.getUnifiedRegNum(LR->getRegClassID(),
458 } // for each operand
460 return instrNeedsSpills;
463 void PhyRegAlloc::updateInstruction(MachineBasicBlock::iterator& MII,
464 MachineBasicBlock &MBB)
466 MachineInstr* MInst = *MII;
467 unsigned Opcode = MInst->getOpCode();
469 // Reset tmp stack positions so they can be reused for each machine instr.
470 MF->getInfo()->popAllTempValues();
472 // Mark the operands for which regs have been allocated.
473 bool instrNeedsSpills = markAllocatedRegs(*MII);
476 // Mark that the operands have been updated. Later,
477 // setRelRegsUsedByThisInst() is called to find registers used by each
478 // MachineInst, and it should not be used for an instruction until
479 // this is done. This flag just serves as a sanity check.
480 OperandsColoredMap[MInst] = true;
483 // Now insert caller-saving code before/after the call.
484 // Do this before inserting spill code since some registers must be
485 // used by save/restore and spill code should not use those registers.
486 if (TM.getInstrInfo().isCall(Opcode)) {
487 AddedInstrns &AI = AddedInstrMap[MInst];
488 insertCallerSavingCode(AI.InstrnsBefore, AI.InstrnsAfter, MInst,
489 MBB.getBasicBlock());
492 // Now insert spill code for remaining operands not allocated to
493 // registers. This must be done even for call return instructions
494 // since those are not handled by the special code above.
495 if (instrNeedsSpills)
496 for (unsigned OpNum=0; OpNum < MInst->getNumOperands(); ++OpNum)
498 MachineOperand& Op = MInst->getOperand(OpNum);
499 if (Op.getType() == MachineOperand::MO_VirtualRegister ||
500 Op.getType() == MachineOperand::MO_CCRegister)
502 const Value* Val = Op.getVRegValue();
503 if (const LiveRange *LR = LRI->getLiveRangeForValue(Val))
504 if (LR->isMarkedForSpill())
505 insertCode4SpilledLR(LR, MII, MBB, OpNum);
507 } // for each operand
510 void PhyRegAlloc::updateMachineCode()
512 // Insert any instructions needed at method entry
513 MachineBasicBlock::iterator MII = MF->front().begin();
514 PrependInstructions(AddedInstrAtEntry.InstrnsBefore, MF->front(), MII,
515 "At function entry: \n");
516 assert(AddedInstrAtEntry.InstrnsAfter.empty() &&
517 "InstrsAfter should be unnecessary since we are just inserting at "
518 "the function entry point here.");
520 for (MachineFunction::iterator BBI = MF->begin(), BBE = MF->end();
523 MachineBasicBlock &MBB = *BBI;
525 // Iterate over all machine instructions in BB and mark operands with
526 // their assigned registers or insert spill code, as appropriate.
527 // Also, fix operands of call/return instructions.
528 for (MachineBasicBlock::iterator MII = MBB.begin(); MII != MBB.end(); ++MII)
529 if (! TM.getInstrInfo().isDummyPhiInstr((*MII)->getOpCode()))
530 updateInstruction(MII, MBB);
532 // Now, move code out of delay slots of branches and returns if needed.
533 // (Also, move "after" code from calls to the last delay slot instruction.)
534 // Moving code out of delay slots is needed in 2 situations:
535 // (1) If this is a branch and it needs instructions inserted after it,
536 // move any existing instructions out of the delay slot so that the
537 // instructions can go into the delay slot. This only supports the
538 // case that #instrsAfter <= #delay slots.
540 // (2) If any instruction in the delay slot needs
541 // instructions inserted, move it out of the delay slot and before the
542 // branch because putting code before or after it would be VERY BAD!
544 // If the annul bit of the branch is set, neither of these is legal!
545 // If so, we need to handle spill differently but annulling is not yet used.
546 for (MachineBasicBlock::iterator MII = MBB.begin();
547 MII != MBB.end(); ++MII)
548 if (unsigned delaySlots =
549 TM.getInstrInfo().getNumDelaySlots((*MII)->getOpCode()))
551 MachineInstr *MInst = *MII, *DelaySlotMI = *(MII+1);
553 // Check the 2 conditions above:
554 // (1) Does a branch need instructions added after it?
555 // (2) O/w does delay slot instr. need instrns before or after?
556 bool isBranch = (TM.getInstrInfo().isBranch(MInst->getOpCode()) ||
557 TM.getInstrInfo().isReturn(MInst->getOpCode()));
558 bool cond1 = (isBranch &&
559 AddedInstrMap.count(MInst) &&
560 AddedInstrMap[MInst].InstrnsAfter.size() > 0);
561 bool cond2 = (AddedInstrMap.count(DelaySlotMI) &&
562 (AddedInstrMap[DelaySlotMI].InstrnsBefore.size() > 0 ||
563 AddedInstrMap[DelaySlotMI].InstrnsAfter.size() > 0));
567 assert((MInst->getOpCodeFlags() & AnnulFlag) == 0 &&
568 "FIXME: Moving an annulled delay slot instruction!");
569 assert(delaySlots==1 &&
570 "InsertBefore does not yet handle >1 delay slots!");
571 InsertBefore(DelaySlotMI, MBB, MII); // MII pts back to branch
573 // In case (1), delete it and don't replace with anything!
574 // Otherwise (i.e., case (2) only) replace it with a NOP.
576 DeleteInstruction(MBB, ++MII); // MII now points to next inst.
577 --MII; // reset MII for ++MII of loop
580 SubstituteInPlace(BuildMI(TM.getInstrInfo().getNOPOpCode(),1),
581 MBB, MII+1); // replace with NOP
584 std::cerr << "\nRegAlloc: Moved instr. with added code: "
586 << " out of delay slots of instr: " << *MInst;
590 // For non-branch instr with delay slots (probably a call), move
591 // InstrAfter to the instr. in the last delay slot.
592 move2DelayedInstr(*MII, *(MII+delaySlots));
595 // Finally iterate over all instructions in BB and insert before/after
596 for (MachineBasicBlock::iterator MII=MBB.begin(); MII != MBB.end(); ++MII) {
597 MachineInstr *MInst = *MII;
599 // do not process Phis
600 if (TM.getInstrInfo().isDummyPhiInstr(MInst->getOpCode()))
603 // if there are any added instructions...
604 if (AddedInstrMap.count(MInst)) {
605 AddedInstrns &CallAI = AddedInstrMap[MInst];
608 bool isBranch = (TM.getInstrInfo().isBranch(MInst->getOpCode()) ||
609 TM.getInstrInfo().isReturn(MInst->getOpCode()));
611 AddedInstrMap[MInst].InstrnsAfter.size() <=
612 TM.getInstrInfo().getNumDelaySlots(MInst->getOpCode())) &&
613 "Cannot put more than #delaySlots instrns after "
614 "branch or return! Need to handle temps differently.");
618 // Temporary sanity checking code to detect whether the same machine
619 // instruction is ever inserted twice before/after a call.
620 // I suspect this is happening but am not sure. --Vikram, 7/1/03.
621 std::set<const MachineInstr*> instrsSeen;
622 for (int i = 0, N = CallAI.InstrnsBefore.size(); i < N; ++i) {
623 assert(instrsSeen.count(CallAI.InstrnsBefore[i]) == 0 &&
624 "Duplicate machine instruction in InstrnsBefore!");
625 instrsSeen.insert(CallAI.InstrnsBefore[i]);
627 for (int i = 0, N = CallAI.InstrnsAfter.size(); i < N; ++i) {
628 assert(instrsSeen.count(CallAI.InstrnsAfter[i]) == 0 &&
629 "Duplicate machine instruction in InstrnsBefore/After!");
630 instrsSeen.insert(CallAI.InstrnsAfter[i]);
634 // Now add the instructions before/after this MI.
635 // We do this here to ensure that spill for an instruction is inserted
636 // as close as possible to an instruction (see above insertCode4Spill)
637 if (! CallAI.InstrnsBefore.empty())
638 PrependInstructions(CallAI.InstrnsBefore, MBB, MII,"");
640 if (! CallAI.InstrnsAfter.empty())
641 AppendInstructions(CallAI.InstrnsAfter, MBB, MII,"");
643 } // if there are any added instructions
644 } // for each machine instruction
649 //----------------------------------------------------------------------------
650 // This method inserts spill code for AN operand whose LR was spilled.
651 // This method may be called several times for a single machine instruction
652 // if it contains many spilled operands. Each time it is called, it finds
653 // a register which is not live at that instruction and also which is not
654 // used by other spilled operands of the same instruction. Then it uses
655 // this register temporarily to accommodate the spilled value.
656 //----------------------------------------------------------------------------
658 void PhyRegAlloc::insertCode4SpilledLR(const LiveRange *LR,
659 MachineBasicBlock::iterator& MII,
660 MachineBasicBlock &MBB,
661 const unsigned OpNum) {
662 MachineInstr *MInst = *MII;
663 const BasicBlock *BB = MBB.getBasicBlock();
665 assert((! TM.getInstrInfo().isCall(MInst->getOpCode()) || OpNum == 0) &&
666 "Outgoing arg of a call must be handled elsewhere (func arg ok)");
667 assert(! TM.getInstrInfo().isReturn(MInst->getOpCode()) &&
668 "Return value of a ret must be handled elsewhere");
670 MachineOperand& Op = MInst->getOperand(OpNum);
671 bool isDef = Op.opIsDefOnly();
672 bool isDefAndUse = Op.opIsDefAndUse();
673 unsigned RegType = MRI.getRegTypeForLR(LR);
674 int SpillOff = LR->getSpillOffFromFP();
675 RegClass *RC = LR->getRegClass();
677 // Get the live-variable set to find registers free before this instr.
678 const ValueSet &LVSetBef = LVI->getLiveVarSetBeforeMInst(MInst, BB);
681 // If this instr. is in the delay slot of a branch or return, we need to
682 // include all live variables before that branch or return -- we don't want to
683 // trample those! Verify that the set is included in the LV set before MInst.
684 if (MII != MBB.begin()) {
685 MachineInstr *PredMI = *(MII-1);
686 if (unsigned DS = TM.getInstrInfo().getNumDelaySlots(PredMI->getOpCode()))
687 assert(set_difference(LVI->getLiveVarSetBeforeMInst(PredMI), LVSetBef)
688 .empty() && "Live-var set before branch should be included in "
689 "live-var set of each delay slot instruction!");
693 MF->getInfo()->pushTempValue(MRI.getSpilledRegSize(RegType) );
695 std::vector<MachineInstr*> MIBef, MIAft;
696 std::vector<MachineInstr*> AdIMid;
698 // Choose a register to hold the spilled value, if one was not preallocated.
699 // This may insert code before and after MInst to free up the value. If so,
700 // this code should be first/last in the spill sequence before/after MInst.
701 int TmpRegU=(LR->hasColor()
702 ? MRI.getUnifiedRegNum(LR->getRegClassID(),LR->getColor())
703 : getUsableUniRegAtMI(RegType, &LVSetBef, MInst, MIBef,MIAft));
705 // Set the operand first so that it this register does not get used
706 // as a scratch register for later calls to getUsableUniRegAtMI below
707 MInst->SetRegForOperand(OpNum, TmpRegU);
709 // get the added instructions for this instruction
710 AddedInstrns &AI = AddedInstrMap[MInst];
712 // We may need a scratch register to copy the spilled value to/from memory.
713 // This may itself have to insert code to free up a scratch register.
714 // Any such code should go before (after) the spill code for a load (store).
715 // The scratch reg is not marked as used because it is only used
716 // for the copy and not used across MInst.
717 int scratchRegType = -1;
719 if (MRI.regTypeNeedsScratchReg(RegType, scratchRegType))
721 scratchReg = getUsableUniRegAtMI(scratchRegType, &LVSetBef,
722 MInst, MIBef, MIAft);
723 assert(scratchReg != MRI.getInvalidRegNum());
726 if (!isDef || isDefAndUse) {
727 // for a USE, we have to load the value of LR from stack to a TmpReg
728 // and use the TmpReg as one operand of instruction
730 // actual loading instruction(s)
731 MRI.cpMem2RegMI(AdIMid, MRI.getFramePointer(), SpillOff, TmpRegU,
732 RegType, scratchReg);
734 // the actual load should be after the instructions to free up TmpRegU
735 MIBef.insert(MIBef.end(), AdIMid.begin(), AdIMid.end());
739 if (isDef || isDefAndUse) { // if this is a Def
740 // for a DEF, we have to store the value produced by this instruction
741 // on the stack position allocated for this LR
743 // actual storing instruction(s)
744 MRI.cpReg2MemMI(AdIMid, TmpRegU, MRI.getFramePointer(), SpillOff,
745 RegType, scratchReg);
747 MIAft.insert(MIAft.begin(), AdIMid.begin(), AdIMid.end());
750 // Finally, insert the entire spill code sequences before/after MInst
751 AI.InstrnsBefore.insert(AI.InstrnsBefore.end(), MIBef.begin(), MIBef.end());
752 AI.InstrnsAfter.insert(AI.InstrnsAfter.begin(), MIAft.begin(), MIAft.end());
755 std::cerr << "\nFor Inst:\n " << *MInst;
756 std::cerr << "SPILLED LR# " << LR->getUserIGNode()->getIndex();
757 std::cerr << "; added Instructions:";
758 for_each(MIBef.begin(), MIBef.end(), std::mem_fun(&MachineInstr::dump));
759 for_each(MIAft.begin(), MIAft.end(), std::mem_fun(&MachineInstr::dump));
764 //----------------------------------------------------------------------------
765 // This method inserts caller saving/restoring instructions before/after
766 // a call machine instruction. The caller saving/restoring instructions are
768 // ** caller saving instructions
769 // other instructions inserted for the call by ColorCallArg
771 // other instructions inserted for the call ColorCallArg
772 // ** caller restoring instructions
773 //----------------------------------------------------------------------------
776 PhyRegAlloc::insertCallerSavingCode(std::vector<MachineInstr*> &instrnsBefore,
777 std::vector<MachineInstr*> &instrnsAfter,
778 MachineInstr *CallMI,
779 const BasicBlock *BB)
781 assert(TM.getInstrInfo().isCall(CallMI->getOpCode()));
783 // hash set to record which registers were saved/restored
784 hash_set<unsigned> PushedRegSet;
786 CallArgsDescriptor* argDesc = CallArgsDescriptor::get(CallMI);
788 // if the call is to a instrumentation function, do not insert save and
789 // restore instructions the instrumentation function takes care of save
790 // restore for volatile regs.
792 // FIXME: this should be made general, not specific to the reoptimizer!
793 const Function *Callee = argDesc->getCallInst()->getCalledFunction();
794 bool isLLVMFirstTrigger = Callee && Callee->getName() == "llvm_first_trigger";
796 // Now check if the call has a return value (using argDesc) and if so,
797 // find the LR of the TmpInstruction representing the return value register.
798 // (using the last or second-last *implicit operand* of the call MI).
799 // Insert it to to the PushedRegSet since we must not save that register
800 // and restore it after the call.
801 // We do this because, we look at the LV set *after* the instruction
802 // to determine, which LRs must be saved across calls. The return value
803 // of the call is live in this set - but we must not save/restore it.
804 if (const Value *origRetVal = argDesc->getReturnValue()) {
805 unsigned retValRefNum = (CallMI->getNumImplicitRefs() -
806 (argDesc->getIndirectFuncPtr()? 1 : 2));
807 const TmpInstruction* tmpRetVal =
808 cast<TmpInstruction>(CallMI->getImplicitRef(retValRefNum));
809 assert(tmpRetVal->getOperand(0) == origRetVal &&
810 tmpRetVal->getType() == origRetVal->getType() &&
811 "Wrong implicit ref?");
812 LiveRange *RetValLR = LRI->getLiveRangeForValue(tmpRetVal);
813 assert(RetValLR && "No LR for RetValue of call");
815 if (! RetValLR->isMarkedForSpill())
816 PushedRegSet.insert(MRI.getUnifiedRegNum(RetValLR->getRegClassID(),
817 RetValLR->getColor()));
820 const ValueSet &LVSetAft = LVI->getLiveVarSetAfterMInst(CallMI, BB);
821 ValueSet::const_iterator LIt = LVSetAft.begin();
823 // for each live var in live variable set after machine inst
824 for( ; LIt != LVSetAft.end(); ++LIt) {
825 // get the live range corresponding to live var
826 LiveRange *const LR = LRI->getLiveRangeForValue(*LIt);
828 // LR can be null if it is a const since a const
829 // doesn't have a dominating def - see Assumptions above
831 if(! LR->isMarkedForSpill()) {
832 assert(LR->hasColor() && "LR is neither spilled nor colored?");
833 unsigned RCID = LR->getRegClassID();
834 unsigned Color = LR->getColor();
836 if (MRI.isRegVolatile(RCID, Color) ) {
837 // if this is a call to the first-level reoptimizer
838 // instrumentation entry point, and the register is not
839 // modified by call, don't save and restore it.
840 if (isLLVMFirstTrigger && !MRI.modifiedByCall(RCID, Color))
843 // if the value is in both LV sets (i.e., live before and after
844 // the call machine instruction)
845 unsigned Reg = MRI.getUnifiedRegNum(RCID, Color);
847 // if we haven't already pushed this register...
848 if( PushedRegSet.find(Reg) == PushedRegSet.end() ) {
849 unsigned RegType = MRI.getRegTypeForLR(LR);
851 // Now get two instructions - to push on stack and pop from stack
852 // and add them to InstrnsBefore and InstrnsAfter of the
855 MF->getInfo()->pushTempValue(MRI.getSpilledRegSize(RegType));
857 //---- Insert code for pushing the reg on stack ----------
859 std::vector<MachineInstr*> AdIBef, AdIAft;
861 // We may need a scratch register to copy the saved value
862 // to/from memory. This may itself have to insert code to
863 // free up a scratch register. Any such code should go before
864 // the save code. The scratch register, if any, is by default
865 // temporary and not "used" by the instruction unless the
866 // copy code itself decides to keep the value in the scratch reg.
867 int scratchRegType = -1;
869 if (MRI.regTypeNeedsScratchReg(RegType, scratchRegType))
870 { // Find a register not live in the LVSet before CallMI
871 const ValueSet &LVSetBef =
872 LVI->getLiveVarSetBeforeMInst(CallMI, BB);
873 scratchReg = getUsableUniRegAtMI(scratchRegType, &LVSetBef,
874 CallMI, AdIBef, AdIAft);
875 assert(scratchReg != MRI.getInvalidRegNum());
878 if (AdIBef.size() > 0)
879 instrnsBefore.insert(instrnsBefore.end(),
880 AdIBef.begin(), AdIBef.end());
882 MRI.cpReg2MemMI(instrnsBefore, Reg, MRI.getFramePointer(),
883 StackOff, RegType, scratchReg);
885 if (AdIAft.size() > 0)
886 instrnsBefore.insert(instrnsBefore.end(),
887 AdIAft.begin(), AdIAft.end());
889 //---- Insert code for popping the reg from the stack ----------
893 // We may need a scratch register to copy the saved value
894 // from memory. This may itself have to insert code to
895 // free up a scratch register. Any such code should go
896 // after the save code. As above, scratch is not marked "used".
899 if (MRI.regTypeNeedsScratchReg(RegType, scratchRegType))
900 { // Find a register not live in the LVSet after CallMI
901 scratchReg = getUsableUniRegAtMI(scratchRegType, &LVSetAft,
902 CallMI, AdIBef, AdIAft);
903 assert(scratchReg != MRI.getInvalidRegNum());
906 if (AdIBef.size() > 0)
907 instrnsAfter.insert(instrnsAfter.end(),
908 AdIBef.begin(), AdIBef.end());
910 MRI.cpMem2RegMI(instrnsAfter, MRI.getFramePointer(), StackOff,
911 Reg, RegType, scratchReg);
913 if (AdIAft.size() > 0)
914 instrnsAfter.insert(instrnsAfter.end(),
915 AdIAft.begin(), AdIAft.end());
917 PushedRegSet.insert(Reg);
920 std::cerr << "\nFor call inst:" << *CallMI;
921 std::cerr << " -inserted caller saving instrs: Before:\n\t ";
922 for_each(instrnsBefore.begin(), instrnsBefore.end(),
923 std::mem_fun(&MachineInstr::dump));
924 std::cerr << " -and After:\n\t ";
925 for_each(instrnsAfter.begin(), instrnsAfter.end(),
926 std::mem_fun(&MachineInstr::dump));
928 } // if not already pushed
929 } // if LR has a volatile color
931 } // if there is a LR for Var
932 } // for each value in the LV set after instruction
936 //----------------------------------------------------------------------------
937 // We can use the following method to get a temporary register to be used
938 // BEFORE any given machine instruction. If there is a register available,
939 // this method will simply return that register and set MIBef = MIAft = NULL.
940 // Otherwise, it will return a register and MIAft and MIBef will contain
941 // two instructions used to free up this returned register.
942 // Returned register number is the UNIFIED register number
943 //----------------------------------------------------------------------------
945 int PhyRegAlloc::getUsableUniRegAtMI(const int RegType,
946 const ValueSet *LVSetBef,
948 std::vector<MachineInstr*>& MIBef,
949 std::vector<MachineInstr*>& MIAft) {
950 RegClass* RC = getRegClassByID(MRI.getRegClassIDOfRegType(RegType));
952 int RegU = getUnusedUniRegAtMI(RC, RegType, MInst, LVSetBef);
955 // we couldn't find an unused register. Generate code to free up a reg by
956 // saving it on stack and restoring after the instruction
958 int TmpOff = MF->getInfo()->pushTempValue(MRI.getSpilledRegSize(RegType));
960 RegU = getUniRegNotUsedByThisInst(RC, RegType, MInst);
962 // Check if we need a scratch register to copy this register to memory.
963 int scratchRegType = -1;
964 if (MRI.regTypeNeedsScratchReg(RegType, scratchRegType))
966 int scratchReg = getUsableUniRegAtMI(scratchRegType, LVSetBef,
967 MInst, MIBef, MIAft);
968 assert(scratchReg != MRI.getInvalidRegNum());
970 // We may as well hold the value in the scratch register instead
971 // of copying it to memory and back. But we have to mark the
972 // register as used by this instruction, so it does not get used
973 // as a scratch reg. by another operand or anyone else.
974 ScratchRegsUsed.insert(std::make_pair(MInst, scratchReg));
975 MRI.cpReg2RegMI(MIBef, RegU, scratchReg, RegType);
976 MRI.cpReg2RegMI(MIAft, scratchReg, RegU, RegType);
979 { // the register can be copied directly to/from memory so do it.
980 MRI.cpReg2MemMI(MIBef, RegU, MRI.getFramePointer(), TmpOff, RegType);
981 MRI.cpMem2RegMI(MIAft, MRI.getFramePointer(), TmpOff, RegU, RegType);
989 //----------------------------------------------------------------------------
990 // This method is called to get a new unused register that can be used
991 // to accommodate a temporary value. This method may be called several times
992 // for a single machine instruction. Each time it is called, it finds a
993 // register which is not live at that instruction and also which is not used
994 // by other spilled operands of the same instruction. Return register number
995 // is relative to the register class, NOT the unified number.
996 //----------------------------------------------------------------------------
998 int PhyRegAlloc::getUnusedUniRegAtMI(RegClass *RC,
1000 const MachineInstr *MInst,
1001 const ValueSet* LVSetBef) {
1002 RC->clearColorsUsed(); // Reset array
1004 if (LVSetBef == NULL) {
1005 LVSetBef = &LVI->getLiveVarSetBeforeMInst(MInst);
1006 assert(LVSetBef != NULL && "Unable to get live-var set before MInst?");
1009 ValueSet::const_iterator LIt = LVSetBef->begin();
1011 // for each live var in live variable set after machine inst
1012 for ( ; LIt != LVSetBef->end(); ++LIt) {
1013 // Get the live range corresponding to live var, and its RegClass
1014 LiveRange *const LRofLV = LRI->getLiveRangeForValue(*LIt );
1016 // LR can be null if it is a const since a const
1017 // doesn't have a dominating def - see Assumptions above
1018 if (LRofLV && LRofLV->getRegClass() == RC && LRofLV->hasColor())
1019 RC->markColorsUsed(LRofLV->getColor(),
1020 MRI.getRegTypeForLR(LRofLV), RegType);
1023 // It is possible that one operand of this MInst was already spilled
1024 // and it received some register temporarily. If that's the case,
1025 // it is recorded in machine operand. We must skip such registers.
1026 setRelRegsUsedByThisInst(RC, RegType, MInst);
1028 int unusedReg = RC->getUnusedColor(RegType); // find first unused color
1030 return MRI.getUnifiedRegNum(RC->getID(), unusedReg);
1036 //----------------------------------------------------------------------------
1037 // Get any other register in a register class, other than what is used
1038 // by operands of a machine instruction. Returns the unified reg number.
1039 //----------------------------------------------------------------------------
1041 int PhyRegAlloc::getUniRegNotUsedByThisInst(RegClass *RC,
1043 const MachineInstr *MInst) {
1044 RC->clearColorsUsed();
1046 setRelRegsUsedByThisInst(RC, RegType, MInst);
1048 // find the first unused color
1049 int unusedReg = RC->getUnusedColor(RegType);
1050 assert(unusedReg >= 0 &&
1051 "FATAL: No free register could be found in reg class!!");
1053 return MRI.getUnifiedRegNum(RC->getID(), unusedReg);
1057 //----------------------------------------------------------------------------
1058 // This method modifies the IsColorUsedArr of the register class passed to it.
1059 // It sets the bits corresponding to the registers used by this machine
1060 // instructions. Both explicit and implicit operands are set.
1061 //----------------------------------------------------------------------------
1063 static void markRegisterUsed(int RegNo, RegClass *RC, int RegType,
1064 const TargetRegInfo &TRI) {
1065 unsigned classId = 0;
1066 int classRegNum = TRI.getClassRegNum(RegNo, classId);
1067 if (RC->getID() == classId)
1068 RC->markColorsUsed(classRegNum, RegType, RegType);
1071 void PhyRegAlloc::setRelRegsUsedByThisInst(RegClass *RC, int RegType,
1072 const MachineInstr *MI)
1074 assert(OperandsColoredMap[MI] == true &&
1075 "Illegal to call setRelRegsUsedByThisInst() until colored operands "
1076 "are marked for an instruction.");
1078 // Add the registers already marked as used by the instruction.
1079 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i)
1080 if (MI->getOperand(i).hasAllocatedReg())
1081 markRegisterUsed(MI->getOperand(i).getAllocatedRegNum(), RC, RegType,MRI);
1083 for (unsigned i = 0, e = MI->getNumImplicitRefs(); i != e; ++i)
1084 if (MI->getImplicitOp(i).hasAllocatedReg())
1085 markRegisterUsed(MI->getImplicitOp(i).getAllocatedRegNum(), RC,
1088 // Add all of the scratch registers that are used to save values across the
1089 // instruction (e.g., for saving state register values).
1090 std::pair<ScratchRegsUsedTy::iterator, ScratchRegsUsedTy::iterator>
1091 IR = ScratchRegsUsed.equal_range(MI);
1092 for (ScratchRegsUsedTy::iterator I = IR.first; I != IR.second; ++I)
1093 markRegisterUsed(I->second, RC, RegType, MRI);
1095 // If there are implicit references, mark their allocated regs as well
1096 for (unsigned z=0; z < MI->getNumImplicitRefs(); z++)
1097 if (const LiveRange*
1098 LRofImpRef = LRI->getLiveRangeForValue(MI->getImplicitRef(z)))
1099 if (LRofImpRef->hasColor())
1100 // this implicit reference is in a LR that received a color
1101 RC->markColorsUsed(LRofImpRef->getColor(),
1102 MRI.getRegTypeForLR(LRofImpRef), RegType);
1106 //----------------------------------------------------------------------------
1107 // If there are delay slots for an instruction, the instructions
1108 // added after it must really go after the delayed instruction(s).
1109 // So, we move the InstrAfter of that instruction to the
1110 // corresponding delayed instruction using the following method.
1111 //----------------------------------------------------------------------------
1113 void PhyRegAlloc::move2DelayedInstr(const MachineInstr *OrigMI,
1114 const MachineInstr *DelayedMI)
1116 // "added after" instructions of the original instr
1117 std::vector<MachineInstr *> &OrigAft = AddedInstrMap[OrigMI].InstrnsAfter;
1119 if (DEBUG_RA && OrigAft.size() > 0) {
1120 std::cerr << "\nRegAlloc: Moved InstrnsAfter for: " << *OrigMI;
1121 std::cerr << " to last delay slot instrn: " << *DelayedMI;
1124 // "added after" instructions of the delayed instr
1125 std::vector<MachineInstr *> &DelayedAft=AddedInstrMap[DelayedMI].InstrnsAfter;
1127 // go thru all the "added after instructions" of the original instruction
1128 // and append them to the "added after instructions" of the delayed
1130 DelayedAft.insert(DelayedAft.end(), OrigAft.begin(), OrigAft.end());
1132 // empty the "added after instructions" of the original instruction
1137 void PhyRegAlloc::colorIncomingArgs()
1139 MRI.colorMethodArgs(Fn, *LRI, AddedInstrAtEntry.InstrnsBefore,
1140 AddedInstrAtEntry.InstrnsAfter);
1144 //----------------------------------------------------------------------------
1145 // This method determines whether the suggested color of each live range
1146 // is really usable, and then calls its setSuggestedColorUsable() method to
1147 // record the answer. A suggested color is NOT usable when the suggested color
1148 // is volatile AND when there are call interferences.
1149 //----------------------------------------------------------------------------
1151 void PhyRegAlloc::markUnusableSugColors()
1153 LiveRangeMapType::const_iterator HMI = (LRI->getLiveRangeMap())->begin();
1154 LiveRangeMapType::const_iterator HMIEnd = (LRI->getLiveRangeMap())->end();
1156 for (; HMI != HMIEnd ; ++HMI ) {
1158 LiveRange *L = HMI->second; // get the LiveRange
1159 if (L && L->hasSuggestedColor ())
1160 L->setSuggestedColorUsable
1161 (!(MRI.isRegVolatile (L->getRegClassID (), L->getSuggestedColor ())
1162 && L->isCallInterference ()));
1164 } // for all LR's in hash map
1168 //----------------------------------------------------------------------------
1169 // The following method will set the stack offsets of the live ranges that
1170 // are decided to be spilled. This must be called just after coloring the
1171 // LRs using the graph coloring algo. For each live range that is spilled,
1172 // this method allocate a new spill position on the stack.
1173 //----------------------------------------------------------------------------
1175 void PhyRegAlloc::allocateStackSpace4SpilledLRs() {
1176 if (DEBUG_RA) std::cerr << "\nSetting LR stack offsets for spills...\n";
1178 LiveRangeMapType::const_iterator HMI = LRI->getLiveRangeMap()->begin();
1179 LiveRangeMapType::const_iterator HMIEnd = LRI->getLiveRangeMap()->end();
1181 for ( ; HMI != HMIEnd ; ++HMI) {
1182 if (HMI->first && HMI->second) {
1183 LiveRange *L = HMI->second; // get the LiveRange
1184 if (L->isMarkedForSpill()) { // NOTE: allocating size of long Type **
1185 int stackOffset = MF->getInfo()->allocateSpilledValue(Type::LongTy);
1186 L->setSpillOffFromFP(stackOffset);
1188 std::cerr << " LR# " << L->getUserIGNode()->getIndex()
1189 << ": stack-offset = " << stackOffset << "\n";
1192 } // for all LR's in hash map
1197 /// AllocInfo - Structure representing one instruction's
1198 /// operand's-worth of register allocation state. We create tables
1199 /// made out of these data structures to generate mapping information
1200 /// for this register allocator. (FIXME: This might move to a header
1201 /// file at some point.)
1204 unsigned Instruction;
1206 unsigned AllocState;
1208 AllocInfo (unsigned Instruction_, unsigned Operand_,
1209 unsigned AllocState_, int Placement_) :
1210 Instruction (Instruction_), Operand (Operand_),
1211 AllocState (AllocState_), Placement (Placement_) { }
1212 /// getConstantType - Return a StructType representing an AllocInfo
1215 static StructType *getConstantType () {
1216 std::vector<const Type *> TV;
1217 TV.push_back (Type::UIntTy);
1218 TV.push_back (Type::UIntTy);
1219 TV.push_back (Type::UIntTy);
1220 TV.push_back (Type::IntTy);
1221 return StructType::get (TV);
1223 /// toConstant - Convert this AllocInfo into an LLVM Constant of type
1224 /// getConstantType(), and return the Constant.
1226 Constant *toConstant () const {
1227 StructType *ST = getConstantType ();
1228 std::vector<Constant *> CV;
1229 CV.push_back (ConstantUInt::get (Type::UIntTy, Instruction));
1230 CV.push_back (ConstantUInt::get (Type::UIntTy, Operand));
1231 CV.push_back (ConstantUInt::get (Type::UIntTy, AllocState));
1232 CV.push_back (ConstantSInt::get (Type::IntTy, Placement));
1233 return ConstantStruct::get (ST, CV);
1238 void PhyRegAlloc::saveState ()
1240 std::vector<Constant *> state;
1242 LiveRangeMapType::const_iterator HMIEnd = LRI->getLiveRangeMap ()->end ();
1243 for (const_inst_iterator II=inst_begin (Fn), IE=inst_end (Fn); II != IE; ++II)
1244 for (unsigned i = 0; i < (*II)->getNumOperands (); ++i) {
1245 const Value *V = (*II)->getOperand (i);
1246 // Don't worry about it unless it's something whose reg. we'll need.
1247 if (!isa<Argument> (V) && !isa<Instruction> (V))
1249 LiveRangeMapType::const_iterator HMI = LRI->getLiveRangeMap ()->find (V);
1250 static const unsigned NotAllocated = 0, Allocated = 1, Spilled = 2;
1251 unsigned AllocState = NotAllocated;
1253 if ((HMI != HMIEnd) && HMI->second) {
1254 LiveRange *L = HMI->second;
1255 assert ((L->hasColor () || L->isMarkedForSpill ())
1256 && "Live range exists but not colored or spilled");
1257 if (L->hasColor()) {
1258 AllocState = Allocated;
1259 Placement = MRI.getUnifiedRegNum (L->getRegClassID (),
1261 } else if (L->isMarkedForSpill ()) {
1262 AllocState = Spilled;
1263 assert (L->hasSpillOffset ()
1264 && "Live range marked for spill but has no spill offset");
1265 Placement = L->getSpillOffFromFP ();
1268 state.push_back (AllocInfo (Insn, i, AllocState,
1269 Placement).toConstant ());
1271 // Convert state into an LLVM ConstantArray, and put it in a
1272 // ConstantStruct (named S) along with its size.
1273 unsigned Size = state.size ();
1274 ArrayType *AT = ArrayType::get (AllocInfo::getConstantType (), Size);
1275 std::vector<const Type *> TV;
1276 TV.push_back (Type::UIntTy);
1278 StructType *ST = StructType::get (TV);
1279 std::vector<Constant *> CV;
1280 CV.push_back (ConstantUInt::get (Type::UIntTy, Size));
1281 CV.push_back (ConstantArray::get (AT, state));
1282 Constant *S = ConstantStruct::get (ST, CV);
1283 // Save S in the map containing register allocator state for this module.
1284 FnAllocState[Fn] = S;
1288 bool PhyRegAlloc::doFinalization (Module &M) {
1289 if (!SaveRegAllocState)
1290 return false; // Nothing to do here, unless we're saving state.
1292 // Convert FnAllocState to a single Constant array and add it
1294 ArrayType *AT = ArrayType::get (AllocInfo::getConstantType (), 0);
1295 std::vector<const Type *> TV;
1296 TV.push_back (Type::UIntTy);
1298 PointerType *PT = PointerType::get (StructType::get (TV));
1300 std::vector<Constant *> allstate;
1301 for (Module::iterator I = M.begin (), E = M.end (); I != E; ++I) {
1303 if (FnAllocState.find (F) == FnAllocState.end ()) {
1304 allstate.push_back (ConstantPointerNull::get (PT));
1306 GlobalVariable *GV =
1307 new GlobalVariable (FnAllocState[F]->getType (), true,
1308 GlobalValue::InternalLinkage, FnAllocState[F],
1309 F->getName () + ".regAllocState", &M);
1310 // Have: { uint, [Size x { uint, uint, uint, int }] } *
1311 // Cast it to: { uint, [0 x { uint, uint, uint, int }] } *
1312 Constant *CE = ConstantExpr::getCast (ConstantPointerRef::get (GV), PT);
1313 allstate.push_back (CE);
1317 unsigned Size = allstate.size ();
1318 // Final structure type is:
1319 // { uint, [Size x { uint, [0 x { uint, uint, uint, int }] } *] }
1320 std::vector<const Type *> TV2;
1321 TV2.push_back (Type::UIntTy);
1322 ArrayType *AT2 = ArrayType::get (PT, Size);
1323 TV2.push_back (AT2);
1324 StructType *ST2 = StructType::get (TV2);
1325 std::vector<Constant *> CV2;
1326 CV2.push_back (ConstantUInt::get (Type::UIntTy, Size));
1327 CV2.push_back (ConstantArray::get (AT2, allstate));
1328 new GlobalVariable (ST2, true, GlobalValue::InternalLinkage,
1329 ConstantStruct::get (ST2, CV2), "_llvm_regAllocState",
1331 return false; // No error.
1335 //----------------------------------------------------------------------------
1336 // The entry point to Register Allocation
1337 //----------------------------------------------------------------------------
1339 bool PhyRegAlloc::runOnFunction (Function &F) {
1341 std::cerr << "\n********* Function "<< F.getName () << " ***********\n";
1344 MF = &MachineFunction::get (Fn);
1345 LVI = &getAnalysis<FunctionLiveVarInfo> ();
1346 LRI = new LiveRangeInfo (Fn, TM, RegClassList);
1347 LoopDepthCalc = &getAnalysis<LoopInfo> ();
1349 // Create each RegClass for the target machine and add it to the
1350 // RegClassList. This must be done before calling constructLiveRanges().
1351 for (unsigned rc = 0; rc != NumOfRegClasses; ++rc)
1352 RegClassList.push_back (new RegClass (Fn, &TM.getRegInfo (),
1353 MRI.getMachineRegClass (rc)));
1355 LRI->constructLiveRanges(); // create LR info
1356 if (DEBUG_RA >= RA_DEBUG_LiveRanges)
1357 LRI->printLiveRanges();
1359 createIGNodeListsAndIGs(); // create IGNode list and IGs
1361 buildInterferenceGraphs(); // build IGs in all reg classes
1363 if (DEBUG_RA >= RA_DEBUG_LiveRanges) {
1364 // print all LRs in all reg classes
1365 for ( unsigned rc=0; rc < NumOfRegClasses ; rc++)
1366 RegClassList[rc]->printIGNodeList();
1368 // print IGs in all register classes
1369 for ( unsigned rc=0; rc < NumOfRegClasses ; rc++)
1370 RegClassList[rc]->printIG();
1373 LRI->coalesceLRs(); // coalesce all live ranges
1375 if (DEBUG_RA >= RA_DEBUG_LiveRanges) {
1376 // print all LRs in all reg classes
1377 for (unsigned rc=0; rc < NumOfRegClasses; rc++)
1378 RegClassList[rc]->printIGNodeList();
1380 // print IGs in all register classes
1381 for (unsigned rc=0; rc < NumOfRegClasses; rc++)
1382 RegClassList[rc]->printIG();
1385 // mark un-usable suggested color before graph coloring algorithm.
1386 // When this is done, the graph coloring algo will not reserve
1387 // suggested color unnecessarily - they can be used by another LR
1388 markUnusableSugColors();
1390 // color all register classes using the graph coloring algo
1391 for (unsigned rc=0; rc < NumOfRegClasses ; rc++)
1392 RegClassList[rc]->colorAllRegs();
1394 // After graph coloring, if some LRs did not receive a color (i.e, spilled)
1395 // a position for such spilled LRs
1396 allocateStackSpace4SpilledLRs();
1398 // Reset the temp. area on the stack before use by the first instruction.
1399 // This will also happen after updating each instruction.
1400 MF->getInfo()->popAllTempValues();
1402 // color incoming args - if the correct color was not received
1403 // insert code to copy to the correct register
1404 colorIncomingArgs();
1406 // Save register allocation state for this function in a Constant.
1407 if (SaveRegAllocState)
1410 // Now update the machine code with register names and add any
1411 // additional code inserted by the register allocator to the instruction
1413 updateMachineCode();
1416 std::cerr << "\n**** Machine Code After Register Allocation:\n\n";
1420 // Tear down temporary data structures
1421 for (unsigned rc = 0; rc < NumOfRegClasses; ++rc)
1422 delete RegClassList[rc];
1423 RegClassList.clear ();
1424 AddedInstrMap.clear ();
1425 OperandsColoredMap.clear ();
1426 ScratchRegsUsed.clear ();
1427 AddedInstrAtEntry.clear ();
1430 if (DEBUG_RA) std::cerr << "\nRegister allocation complete!\n";
1431 return false; // Function was not modified