2 //***************************************************************************
7 // Register allocation for LLVM.
10 // 9/10/01 - Ruchira Sasanka - created.
11 //**************************************************************************/
13 #include "llvm/CodeGen/RegisterAllocation.h"
14 #include "llvm/CodeGen/PhyRegAlloc.h"
15 #include "llvm/CodeGen/MachineInstr.h"
16 #include "llvm/CodeGen/MachineCodeForMethod.h"
17 #include "llvm/Analysis/LiveVar/MethodLiveVarInfo.h"
18 #include "llvm/Analysis/LoopInfo.h"
19 #include "llvm/Target/TargetMachine.h"
20 #include "llvm/Target/MachineFrameInfo.h"
21 #include "llvm/Method.h"
22 #include "llvm/Type.h"
28 // ***TODO: There are several places we add instructions. Validate the order
29 // of adding these instructions.
31 cl::Enum<RegAllocDebugLevel_t> DEBUG_RA("dregalloc", cl::NoFlags,
32 "enable register allocation debugging information",
33 clEnumValN(RA_DEBUG_None , "n", "disable debug output"),
34 clEnumValN(RA_DEBUG_Normal , "y", "enable debug output"),
35 clEnumValN(RA_DEBUG_Verbose, "v", "enable extra debug output"), 0);
38 //----------------------------------------------------------------------------
39 // RegisterAllocation pass front end...
40 //----------------------------------------------------------------------------
42 class RegisterAllocator : public MethodPass {
43 TargetMachine &Target;
45 inline RegisterAllocator(TargetMachine &T) : Target(T) {}
47 bool runOnMethod(Method *M) {
49 cerr << "\n******************** Method "<< M->getName()
50 << " ********************\n";
52 PhyRegAlloc PRA(M, Target, &getAnalysis<MethodLiveVarInfo>(),
53 &getAnalysis<cfg::LoopInfo>());
54 PRA.allocateRegisters();
56 if (DEBUG_RA) cerr << "\nRegister allocation complete!\n";
60 virtual void getAnalysisUsageInfo(Pass::AnalysisSet &Requires,
61 Pass::AnalysisSet &Destroyed,
62 Pass::AnalysisSet &Provided) {
63 Requires.push_back(cfg::LoopInfo::ID);
64 Requires.push_back(MethodLiveVarInfo::ID);
69 MethodPass *getRegisterAllocator(TargetMachine &T) {
70 return new RegisterAllocator(T);
73 //----------------------------------------------------------------------------
74 // Constructor: Init local composite objects and create register classes.
75 //----------------------------------------------------------------------------
76 PhyRegAlloc::PhyRegAlloc(Method *M,
77 const TargetMachine& tm,
78 MethodLiveVarInfo *Lvi,
81 mcInfo(MachineCodeForMethod::get(M)),
82 LVI(Lvi), LRI(M, tm, RegClassList),
83 MRI( tm.getRegInfo() ),
84 NumOfRegClasses(MRI.getNumOfRegClasses()),
87 // create each RegisterClass and put in RegClassList
89 for(unsigned int rc=0; rc < NumOfRegClasses; rc++)
90 RegClassList.push_back( new RegClass(M, MRI.getMachineRegClass(rc),
95 //----------------------------------------------------------------------------
96 // Destructor: Deletes register classes
97 //----------------------------------------------------------------------------
98 PhyRegAlloc::~PhyRegAlloc() {
99 for( unsigned int rc=0; rc < NumOfRegClasses; rc++)
100 delete RegClassList[rc];
103 //----------------------------------------------------------------------------
104 // This method initally creates interference graphs (one in each reg class)
105 // and IGNodeList (one in each IG). The actual nodes will be pushed later.
106 //----------------------------------------------------------------------------
107 void PhyRegAlloc::createIGNodeListsAndIGs() {
108 if (DEBUG_RA) cerr << "Creating LR lists ...\n";
111 LiveRangeMapType::const_iterator HMI = LRI.getLiveRangeMap()->begin();
114 LiveRangeMapType::const_iterator HMIEnd = LRI.getLiveRangeMap()->end();
116 for (; HMI != HMIEnd ; ++HMI ) {
118 LiveRange *L = HMI->second; // get the LiveRange
121 cerr << "\n*?!?Warning: Null liver range found for: "
122 << RAV(HMI->first) << "\n";
126 // if the Value * is not null, and LR
127 // is not yet written to the IGNodeList
128 if( !(L->getUserIGNode()) ) {
129 RegClass *const RC = // RegClass of first value in the LR
130 RegClassList[ L->getRegClass()->getID() ];
132 RC->addLRToIG(L); // add this LR to an IG
138 for( unsigned int rc=0; rc < NumOfRegClasses ; rc++)
139 RegClassList[rc]->createInterferenceGraph();
142 cerr << "LRLists Created!\n";
148 //----------------------------------------------------------------------------
149 // This method will add all interferences at for a given instruction.
150 // Interence occurs only if the LR of Def (Inst or Arg) is of the same reg
151 // class as that of live var. The live var passed to this function is the
152 // LVset AFTER the instruction
153 //----------------------------------------------------------------------------
154 void PhyRegAlloc::addInterference(const Value *Def,
155 const ValueSet *LVSet,
158 ValueSet::const_iterator LIt = LVSet->begin();
160 // get the live range of instruction
162 const LiveRange *const LROfDef = LRI.getLiveRangeForValue( Def );
164 IGNode *const IGNodeOfDef = LROfDef->getUserIGNode();
165 assert( IGNodeOfDef );
167 RegClass *const RCOfDef = LROfDef->getRegClass();
169 // for each live var in live variable set
171 for( ; LIt != LVSet->end(); ++LIt) {
174 cerr << "< Def=" << RAV(Def) << ", Lvar=" << RAV(*LIt) << "> ";
176 // get the live range corresponding to live var
178 LiveRange *LROfVar = LRI.getLiveRangeForValue(*LIt);
180 // LROfVar can be null if it is a const since a const
181 // doesn't have a dominating def - see Assumptions above
184 if(LROfDef == LROfVar) // do not set interf for same LR
187 // if 2 reg classes are the same set interference
189 if (RCOfDef == LROfVar->getRegClass()) {
190 RCOfDef->setInterference( LROfDef, LROfVar);
191 } else if (DEBUG_RA > 1) {
192 // we will not have LRs for values not explicitly allocated in the
193 // instruction stream (e.g., constants)
194 cerr << " warning: no live range for " << RAV(*LIt) << "\n";
202 //----------------------------------------------------------------------------
203 // For a call instruction, this method sets the CallInterference flag in
204 // the LR of each variable live int the Live Variable Set live after the
205 // call instruction (except the return value of the call instruction - since
206 // the return value does not interfere with that call itself).
207 //----------------------------------------------------------------------------
209 void PhyRegAlloc::setCallInterferences(const MachineInstr *MInst,
210 const ValueSet *LVSetAft) {
212 // Now find the LR of the return value of the call
213 // We do this because, we look at the LV set *after* the instruction
214 // to determine, which LRs must be saved across calls. The return value
215 // of the call is live in this set - but it does not interfere with call
216 // (i.e., we can allocate a volatile register to the return value)
218 LiveRange *RetValLR = NULL;
219 const Value *RetVal = MRI.getCallInstRetVal( MInst );
222 RetValLR = LRI.getLiveRangeForValue( RetVal );
223 assert( RetValLR && "No LR for RetValue of call");
227 cerr << "\n For call inst: " << *MInst;
229 ValueSet::const_iterator LIt = LVSetAft->begin();
231 // for each live var in live variable set after machine inst
233 for( ; LIt != LVSetAft->end(); ++LIt) {
235 // get the live range corresponding to live var
237 LiveRange *const LR = LRI.getLiveRangeForValue(*LIt );
239 if( LR && DEBUG_RA) {
240 cerr << "\n\tLR Aft Call: ";
245 // LR can be null if it is a const since a const
246 // doesn't have a dominating def - see Assumptions above
248 if( LR && (LR != RetValLR) ) {
249 LR->setCallInterference();
251 cerr << "\n ++Added call interf for LR: " ;
263 //----------------------------------------------------------------------------
264 // This method will walk thru code and create interferences in the IG of
265 // each RegClass. Also, this method calculates the spill cost of each
266 // Live Range (it is done in this method to save another pass over the code).
267 //----------------------------------------------------------------------------
268 void PhyRegAlloc::buildInterferenceGraphs()
271 if(DEBUG_RA) cerr << "Creating interference graphs ...\n";
273 unsigned BBLoopDepthCost;
274 Method::const_iterator BBI = Meth->begin(); // random iterator for BBs
276 for( ; BBI != Meth->end(); ++BBI) { // traverse BBs in random order
278 // find the 10^(loop_depth) of this BB
280 BBLoopDepthCost = (unsigned) pow( 10.0, LoopDepthCalc->getLoopDepth(*BBI));
282 // get the iterator for machine instructions
284 const MachineCodeForBasicBlock& MIVec = (*BBI)->getMachineInstrVec();
285 MachineCodeForBasicBlock::const_iterator
286 MInstIterator = MIVec.begin();
288 // iterate over all the machine instructions in BB
290 for( ; MInstIterator != MIVec.end(); ++MInstIterator) {
292 const MachineInstr *MInst = *MInstIterator;
294 // get the LV set after the instruction
296 const ValueSet &LVSetAI = LVI->getLiveVarSetAfterMInst(MInst, *BBI);
298 const bool isCallInst = TM.getInstrInfo().isCall(MInst->getOpCode());
301 // set the isCallInterference flag of each live range wich extends
302 // accross this call instruction. This information is used by graph
303 // coloring algo to avoid allocating volatile colors to live ranges
304 // that span across calls (since they have to be saved/restored)
306 setCallInterferences(MInst, &LVSetAI);
310 // iterate over all MI operands to find defs
312 for (MachineInstr::const_val_op_iterator OpI = MInst->begin(),
313 OpE = MInst->end(); OpI != OpE; ++OpI) {
314 if (OpI.isDef()) // create a new LR iff this operand is a def
315 addInterference(*OpI, &LVSetAI, isCallInst);
317 // Calculate the spill cost of each live range
319 LiveRange *LR = LRI.getLiveRangeForValue(*OpI);
320 if (LR) LR->addSpillCost(BBLoopDepthCost);
324 // if there are multiple defs in this instruction e.g. in SETX
326 if (TM.getInstrInfo().isPseudoInstr(MInst->getOpCode()))
327 addInterf4PseudoInstr(MInst);
330 // Also add interference for any implicit definitions in a machine
331 // instr (currently, only calls have this).
333 unsigned NumOfImpRefs = MInst->getNumImplicitRefs();
334 if( NumOfImpRefs > 0 ) {
335 for(unsigned z=0; z < NumOfImpRefs; z++)
336 if( MInst->implicitRefIsDefined(z) )
337 addInterference( MInst->getImplicitRef(z), &LVSetAI, isCallInst );
341 } // for all machine instructions in BB
343 } // for all BBs in method
346 // add interferences for method arguments. Since there are no explict
347 // defs in method for args, we have to add them manually
349 addInterferencesForArgs();
352 cerr << "Interference graphs calculted!\n";
358 //--------------------------------------------------------------------------
359 // Pseudo instructions will be exapnded to multiple instructions by the
360 // assembler. Consequently, all the opernds must get distinct registers.
361 // Therefore, we mark all operands of a pseudo instruction as they interfere
363 //--------------------------------------------------------------------------
364 void PhyRegAlloc::addInterf4PseudoInstr(const MachineInstr *MInst) {
366 bool setInterf = false;
368 // iterate over MI operands to find defs
370 for (MachineInstr::const_val_op_iterator It1 = MInst->begin(),
371 ItE = MInst->end(); It1 != ItE; ++It1) {
372 const LiveRange *LROfOp1 = LRI.getLiveRangeForValue(*It1);
373 assert((LROfOp1 || !It1.isDef()) && "No LR for Def in PSEUDO insruction");
375 MachineInstr::const_val_op_iterator It2 = It1;
376 for(++It2; It2 != ItE; ++It2) {
377 const LiveRange *LROfOp2 = LRI.getLiveRangeForValue(*It2);
380 RegClass *RCOfOp1 = LROfOp1->getRegClass();
381 RegClass *RCOfOp2 = LROfOp2->getRegClass();
383 if( RCOfOp1 == RCOfOp2 ){
384 RCOfOp1->setInterference( LROfOp1, LROfOp2 );
388 } // for all other defs in machine instr
389 } // for all operands in an instruction
391 if (!setInterf && MInst->getNumOperands() > 2) {
392 cerr << "\nInterf not set for any operand in pseudo instr:\n";
394 assert(0 && "Interf not set for pseudo instr with > 2 operands" );
400 //----------------------------------------------------------------------------
401 // This method will add interferences for incoming arguments to a method.
402 //----------------------------------------------------------------------------
403 void PhyRegAlloc::addInterferencesForArgs() {
404 // get the InSet of root BB
405 const ValueSet &InSet = LVI->getInSetOfBB(Meth->front());
407 // get the argument list
408 const Method::ArgumentListType& ArgList = Meth->getArgumentList();
410 // get an iterator to arg list
411 Method::ArgumentListType::const_iterator ArgIt = ArgList.begin();
414 for( ; ArgIt != ArgList.end() ; ++ArgIt) { // for each argument
415 addInterference((Value*)*ArgIt, &InSet, false);// add interferences between
416 // args and LVars at start
418 cerr << " - %% adding interference for argument "
419 << RAV((const Value *)*ArgIt) << "\n";
426 //----------------------------------------------------------------------------
427 // This method is called after register allocation is complete to set the
428 // allocated reisters in the machine code. This code will add register numbers
429 // to MachineOperands that contain a Value. Also it calls target specific
430 // methods to produce caller saving instructions. At the end, it adds all
431 // additional instructions produced by the register allocator to the
432 // instruction stream.
433 //----------------------------------------------------------------------------
434 void PhyRegAlloc::updateMachineCode()
437 Method::const_iterator BBI = Meth->begin(); // random iterator for BBs
439 for( ; BBI != Meth->end(); ++BBI) { // traverse BBs in random order
441 // get the iterator for machine instructions
443 MachineCodeForBasicBlock& MIVec = (*BBI)->getMachineInstrVec();
444 MachineCodeForBasicBlock::iterator MInstIterator = MIVec.begin();
446 // iterate over all the machine instructions in BB
448 for( ; MInstIterator != MIVec.end(); ++MInstIterator) {
450 MachineInstr *MInst = *MInstIterator;
452 unsigned Opcode = MInst->getOpCode();
454 // do not process Phis
455 if (TM.getInstrInfo().isPhi(Opcode))
458 // Now insert speical instructions (if necessary) for call/return
461 if (TM.getInstrInfo().isCall(Opcode) ||
462 TM.getInstrInfo().isReturn(Opcode)) {
464 AddedInstrns *AI = AddedInstrMap[ MInst];
466 AI = new AddedInstrns();
467 AddedInstrMap[ MInst ] = AI;
470 // Tmp stack poistions are needed by some calls that have spilled args
471 // So reset it before we call each such method
473 mcInfo.popAllTempValues(TM);
475 if (TM.getInstrInfo().isCall(Opcode))
476 MRI.colorCallArgs(MInst, LRI, AI, *this, *BBI);
477 else if (TM.getInstrInfo().isReturn(Opcode))
478 MRI.colorRetValue(MInst, LRI, AI);
482 /* -- Using above code instead of this
484 // if this machine instr is call, insert caller saving code
486 if( (TM.getInstrInfo()).isCall( MInst->getOpCode()) )
487 MRI.insertCallerSavingCode(MInst, *BBI, *this );
492 // reset the stack offset for temporary variables since we may
493 // need that to spill
494 // mcInfo.popAllTempValues(TM);
495 // TODO ** : do later
497 //for(MachineInstr::val_const_op_iterator OpI(MInst);!OpI.done();++OpI) {
500 // Now replace set the registers for operands in the machine instruction
502 for(unsigned OpNum=0; OpNum < MInst->getNumOperands(); ++OpNum) {
504 MachineOperand& Op = MInst->getOperand(OpNum);
506 if( Op.getOperandType() == MachineOperand::MO_VirtualRegister ||
507 Op.getOperandType() == MachineOperand::MO_CCRegister) {
509 const Value *const Val = Op.getVRegValue();
511 // delete this condition checking later (must assert if Val is null)
514 cerr << "Warning: NULL Value found for operand\n";
517 assert( Val && "Value is NULL");
519 LiveRange *const LR = LRI.getLiveRangeForValue(Val);
523 // nothing to worry if it's a const or a label
526 cerr << "*NO LR for operand : " << Op ;
527 cerr << " [reg:" << Op.getAllocatedRegNum() << "]";
528 cerr << " in inst:\t" << *MInst << "\n";
531 // if register is not allocated, mark register as invalid
532 if( Op.getAllocatedRegNum() == -1)
533 Op.setRegForValue( MRI.getInvalidRegNum());
539 unsigned RCID = (LR->getRegClass())->getID();
541 if( LR->hasColor() ) {
542 Op.setRegForValue( MRI.getUnifiedRegNum(RCID, LR->getColor()) );
546 // LR did NOT receive a color (register). Now, insert spill code
547 // for spilled opeands in this machine instruction
549 //assert(0 && "LR must be spilled");
550 insertCode4SpilledLR(LR, MInst, *BBI, OpNum );
555 } // for each operand
558 // Now add instructions that the register allocator inserts before/after
559 // this machine instructions (done only for calls/rets/incoming args)
560 // We do this here, to ensure that spill for an instruction is inserted
561 // closest as possible to an instruction (see above insertCode4Spill...)
563 // If there are instructions to be added, *before* this machine
564 // instruction, add them now.
566 if( AddedInstrMap[ MInst ] ) {
567 std::deque<MachineInstr *> &IBef = AddedInstrMap[MInst]->InstrnsBefore;
569 if( ! IBef.empty() ) {
570 std::deque<MachineInstr *>::iterator AdIt;
572 for( AdIt = IBef.begin(); AdIt != IBef.end() ; ++AdIt ) {
575 cerr << "For inst " << *MInst;
576 cerr << " PREPENDed instr: " << **AdIt << "\n";
579 MInstIterator = MIVec.insert( MInstIterator, *AdIt );
587 // If there are instructions to be added *after* this machine
588 // instruction, add them now
590 if(AddedInstrMap[MInst] &&
591 !AddedInstrMap[MInst]->InstrnsAfter.empty() ) {
593 // if there are delay slots for this instruction, the instructions
594 // added after it must really go after the delayed instruction(s)
595 // So, we move the InstrAfter of the current instruction to the
596 // corresponding delayed instruction
599 if ((delay=TM.getInstrInfo().getNumDelaySlots(MInst->getOpCode())) >0){
600 move2DelayedInstr(MInst, *(MInstIterator+delay) );
602 if(DEBUG_RA) cerr<< "\nMoved an added instr after the delay slot";
608 // Here we can add the "instructions after" to the current
609 // instruction since there are no delay slots for this instruction
611 std::deque<MachineInstr *> &IAft = AddedInstrMap[MInst]->InstrnsAfter;
613 if( ! IAft.empty() ) {
615 std::deque<MachineInstr *>::iterator AdIt;
617 ++MInstIterator; // advance to the next instruction
619 for( AdIt = IAft.begin(); AdIt != IAft.end() ; ++AdIt ) {
622 cerr << "For inst " << *MInst;
623 cerr << " APPENDed instr: " << **AdIt << "\n";
626 MInstIterator = MIVec.insert( MInstIterator, *AdIt );
630 // MInsterator already points to the next instr. Since the
631 // for loop also increments it, decrement it to point to the
632 // instruction added last
641 } // for each machine instruction
647 //----------------------------------------------------------------------------
648 // This method inserts spill code for AN operand whose LR was spilled.
649 // This method may be called several times for a single machine instruction
650 // if it contains many spilled operands. Each time it is called, it finds
651 // a register which is not live at that instruction and also which is not
652 // used by other spilled operands of the same instruction. Then it uses
653 // this register temporarily to accomodate the spilled value.
654 //----------------------------------------------------------------------------
655 void PhyRegAlloc::insertCode4SpilledLR(const LiveRange *LR,
657 const BasicBlock *BB,
658 const unsigned OpNum) {
660 assert(! TM.getInstrInfo().isCall(MInst->getOpCode()) &&
661 (! TM.getInstrInfo().isReturn(MInst->getOpCode())) &&
662 "Arg of a call/ret must be handled elsewhere");
664 MachineOperand& Op = MInst->getOperand(OpNum);
665 bool isDef = MInst->operandIsDefined(OpNum);
666 unsigned RegType = MRI.getRegType( LR );
667 int SpillOff = LR->getSpillOffFromFP();
668 RegClass *RC = LR->getRegClass();
669 const ValueSet &LVSetBef = LVI->getLiveVarSetBeforeMInst(MInst, BB);
671 mcInfo.pushTempValue(TM, MRI.getSpilledRegSize(RegType) );
673 MachineInstr *MIBef=NULL, *AdIMid=NULL, *MIAft=NULL;
675 int TmpRegU = getUsableUniRegAtMI(RC, RegType, MInst,&LVSetBef, MIBef, MIAft);
677 // get the added instructions for this instruciton
678 AddedInstrns *AI = AddedInstrMap[ MInst ];
680 AI = new AddedInstrns();
681 AddedInstrMap[ MInst ] = AI;
687 // for a USE, we have to load the value of LR from stack to a TmpReg
688 // and use the TmpReg as one operand of instruction
690 // actual loading instruction
691 AdIMid = MRI.cpMem2RegMI(MRI.getFramePointer(), SpillOff, TmpRegU,RegType);
694 AI->InstrnsBefore.push_back(MIBef);
696 AI->InstrnsBefore.push_back(AdIMid);
699 AI->InstrnsAfter.push_front(MIAft);
701 } else { // if this is a Def
702 // for a DEF, we have to store the value produced by this instruction
703 // on the stack position allocated for this LR
705 // actual storing instruction
706 AdIMid = MRI.cpReg2MemMI(TmpRegU, MRI.getFramePointer(), SpillOff,RegType);
709 AI->InstrnsBefore.push_back(MIBef);
711 AI->InstrnsAfter.push_front(AdIMid);
714 AI->InstrnsAfter.push_front(MIAft);
718 cerr << "\nFor Inst " << *MInst;
719 cerr << " - SPILLED LR: "; printSet(*LR);
720 cerr << "\n - Added Instructions:";
721 if (MIBef) cerr << *MIBef;
723 if (MIAft) cerr << *MIAft;
725 Op.setRegForValue(TmpRegU); // set the opearnd
730 //----------------------------------------------------------------------------
731 // We can use the following method to get a temporary register to be used
732 // BEFORE any given machine instruction. If there is a register available,
733 // this method will simply return that register and set MIBef = MIAft = NULL.
734 // Otherwise, it will return a register and MIAft and MIBef will contain
735 // two instructions used to free up this returned register.
736 // Returned register number is the UNIFIED register number
737 //----------------------------------------------------------------------------
739 int PhyRegAlloc::getUsableUniRegAtMI(RegClass *RC,
741 const MachineInstr *MInst,
742 const ValueSet *LVSetBef,
744 MachineInstr *MIAft) {
746 int RegU = getUnusedUniRegAtMI(RC, MInst, LVSetBef);
750 // we found an unused register, so we can simply use it
751 MIBef = MIAft = NULL;
754 // we couldn't find an unused register. Generate code to free up a reg by
755 // saving it on stack and restoring after the instruction
757 int TmpOff = mcInfo.pushTempValue(TM, MRI.getSpilledRegSize(RegType) );
759 RegU = getUniRegNotUsedByThisInst(RC, MInst);
760 MIBef = MRI.cpReg2MemMI(RegU, MRI.getFramePointer(), TmpOff, RegType );
761 MIAft = MRI.cpMem2RegMI(MRI.getFramePointer(), TmpOff, RegU, RegType );
767 //----------------------------------------------------------------------------
768 // This method is called to get a new unused register that can be used to
769 // accomodate a spilled value.
770 // This method may be called several times for a single machine instruction
771 // if it contains many spilled operands. Each time it is called, it finds
772 // a register which is not live at that instruction and also which is not
773 // used by other spilled operands of the same instruction.
774 // Return register number is relative to the register class. NOT
776 //----------------------------------------------------------------------------
777 int PhyRegAlloc::getUnusedUniRegAtMI(RegClass *RC,
778 const MachineInstr *MInst,
779 const ValueSet *LVSetBef) {
781 unsigned NumAvailRegs = RC->getNumOfAvailRegs();
783 bool *IsColorUsedArr = RC->getIsColorUsedArr();
785 for(unsigned i=0; i < NumAvailRegs; i++) // Reset array
786 IsColorUsedArr[i] = false;
788 ValueSet::const_iterator LIt = LVSetBef->begin();
790 // for each live var in live variable set after machine inst
791 for( ; LIt != LVSetBef->end(); ++LIt) {
793 // get the live range corresponding to live var
794 LiveRange *const LRofLV = LRI.getLiveRangeForValue(*LIt );
796 // LR can be null if it is a const since a const
797 // doesn't have a dominating def - see Assumptions above
799 if( LRofLV->hasColor() )
800 IsColorUsedArr[ LRofLV->getColor() ] = true;
803 // It is possible that one operand of this MInst was already spilled
804 // and it received some register temporarily. If that's the case,
805 // it is recorded in machine operand. We must skip such registers.
807 setRelRegsUsedByThisInst(RC, MInst);
809 unsigned c; // find first unused color
810 for( c=0; c < NumAvailRegs; c++)
811 if( ! IsColorUsedArr[ c ] ) break;
814 return MRI.getUnifiedRegNum(RC->getID(), c);
822 //----------------------------------------------------------------------------
823 // Get any other register in a register class, other than what is used
824 // by operands of a machine instruction. Returns the unified reg number.
825 //----------------------------------------------------------------------------
826 int PhyRegAlloc::getUniRegNotUsedByThisInst(RegClass *RC,
827 const MachineInstr *MInst) {
829 bool *IsColorUsedArr = RC->getIsColorUsedArr();
830 unsigned NumAvailRegs = RC->getNumOfAvailRegs();
833 for(unsigned i=0; i < NumAvailRegs ; i++) // Reset array
834 IsColorUsedArr[i] = false;
836 setRelRegsUsedByThisInst(RC, MInst);
838 unsigned c; // find first unused color
839 for( c=0; c < RC->getNumOfAvailRegs(); c++)
840 if( ! IsColorUsedArr[ c ] ) break;
843 return MRI.getUnifiedRegNum(RC->getID(), c);
845 assert( 0 && "FATAL: No free register could be found in reg class!!");
850 //----------------------------------------------------------------------------
851 // This method modifies the IsColorUsedArr of the register class passed to it.
852 // It sets the bits corresponding to the registers used by this machine
853 // instructions. Both explicit and implicit operands are set.
854 //----------------------------------------------------------------------------
855 void PhyRegAlloc::setRelRegsUsedByThisInst(RegClass *RC,
856 const MachineInstr *MInst ) {
858 bool *IsColorUsedArr = RC->getIsColorUsedArr();
860 for(unsigned OpNum=0; OpNum < MInst->getNumOperands(); ++OpNum) {
862 const MachineOperand& Op = MInst->getOperand(OpNum);
864 if( Op.getOperandType() == MachineOperand::MO_VirtualRegister ||
865 Op.getOperandType() == MachineOperand::MO_CCRegister ) {
867 const Value *const Val = Op.getVRegValue();
870 if( MRI.getRegClassIDOfValue(Val) == RC->getID() ) {
872 if( (Reg=Op.getAllocatedRegNum()) != -1) {
873 IsColorUsedArr[ Reg ] = true;
876 // it is possilbe that this operand still is not marked with
877 // a register but it has a LR and that received a color
879 LiveRange *LROfVal = LRI.getLiveRangeForValue(Val);
881 if( LROfVal->hasColor() )
882 IsColorUsedArr[ LROfVal->getColor() ] = true;
885 } // if reg classes are the same
887 else if (Op.getOperandType() == MachineOperand::MO_MachineRegister) {
888 IsColorUsedArr[ Op.getMachineRegNum() ] = true;
892 // If there are implicit references, mark them as well
894 for(unsigned z=0; z < MInst->getNumImplicitRefs(); z++) {
896 LiveRange *const LRofImpRef =
897 LRI.getLiveRangeForValue( MInst->getImplicitRef(z) );
899 if(LRofImpRef && LRofImpRef->hasColor())
900 IsColorUsedArr[LRofImpRef->getColor()] = true;
911 //----------------------------------------------------------------------------
912 // If there are delay slots for an instruction, the instructions
913 // added after it must really go after the delayed instruction(s).
914 // So, we move the InstrAfter of that instruction to the
915 // corresponding delayed instruction using the following method.
917 //----------------------------------------------------------------------------
918 void PhyRegAlloc:: move2DelayedInstr(const MachineInstr *OrigMI,
919 const MachineInstr *DelayedMI) {
921 // "added after" instructions of the original instr
922 std::deque<MachineInstr *> &OrigAft = AddedInstrMap[OrigMI]->InstrnsAfter;
924 // "added instructions" of the delayed instr
925 AddedInstrns *DelayAdI = AddedInstrMap[DelayedMI];
927 if(! DelayAdI ) { // create a new "added after" if necessary
928 DelayAdI = new AddedInstrns();
929 AddedInstrMap[DelayedMI] = DelayAdI;
932 // "added after" instructions of the delayed instr
933 std::deque<MachineInstr *> &DelayedAft = DelayAdI->InstrnsAfter;
935 // go thru all the "added after instructions" of the original instruction
936 // and append them to the "addded after instructions" of the delayed
938 DelayedAft.insert(DelayedAft.end(), OrigAft.begin(), OrigAft.end());
940 // empty the "added after instructions" of the original instruction
944 //----------------------------------------------------------------------------
945 // This method prints the code with registers after register allocation is
947 //----------------------------------------------------------------------------
948 void PhyRegAlloc::printMachineCode()
951 cerr << "\n;************** Method " << Meth->getName()
952 << " *****************\n";
954 Method::const_iterator BBI = Meth->begin(); // random iterator for BBs
956 for( ; BBI != Meth->end(); ++BBI) { // traverse BBs in random order
958 cerr << "\n"; printLabel( *BBI); cerr << ": ";
960 // get the iterator for machine instructions
961 MachineCodeForBasicBlock& MIVec = (*BBI)->getMachineInstrVec();
962 MachineCodeForBasicBlock::iterator MInstIterator = MIVec.begin();
964 // iterate over all the machine instructions in BB
965 for( ; MInstIterator != MIVec.end(); ++MInstIterator) {
967 MachineInstr *const MInst = *MInstIterator;
971 cerr << TargetInstrDescriptors[MInst->getOpCode()].opCodeString;
974 //for(MachineInstr::val_const_op_iterator OpI(MInst);!OpI.done();++OpI) {
976 for(unsigned OpNum=0; OpNum < MInst->getNumOperands(); ++OpNum) {
978 MachineOperand& Op = MInst->getOperand(OpNum);
980 if( Op.getOperandType() == MachineOperand::MO_VirtualRegister ||
981 Op.getOperandType() == MachineOperand::MO_CCRegister /*||
982 Op.getOperandType() == MachineOperand::MO_PCRelativeDisp*/ ) {
984 const Value *const Val = Op.getVRegValue () ;
985 // ****this code is temporary till NULL Values are fixed
987 cerr << "\t<*NULL*>";
991 // if a label or a constant
992 if(isa<BasicBlock>(Val)) {
993 cerr << "\t"; printLabel( Op.getVRegValue () );
995 // else it must be a register value
996 const int RegNum = Op.getAllocatedRegNum();
998 cerr << "\t" << "%" << MRI.getUnifiedRegName( RegNum );
1000 cerr << "(" << Val->getName() << ")";
1002 cerr << "(" << Val << ")";
1007 const LiveRange *LROfVal = LRI.getLiveRangeForValue(Val);
1009 if( LROfVal->hasSpillOffset() )
1014 else if(Op.getOperandType() == MachineOperand::MO_MachineRegister) {
1015 cerr << "\t" << "%" << MRI.getUnifiedRegName(Op.getMachineRegNum());
1019 cerr << "\t" << Op; // use dump field
1024 unsigned NumOfImpRefs = MInst->getNumImplicitRefs();
1025 if( NumOfImpRefs > 0) {
1026 cerr << "\tImplicit:";
1028 for(unsigned z=0; z < NumOfImpRefs; z++)
1029 cerr << RAV(MInst->getImplicitRef(z)) << "\t";
1032 } // for all machine instructions
1044 //----------------------------------------------------------------------------
1046 //----------------------------------------------------------------------------
1048 void PhyRegAlloc::colorCallRetArgs()
1051 CallRetInstrListType &CallRetInstList = LRI.getCallRetInstrList();
1052 CallRetInstrListType::const_iterator It = CallRetInstList.begin();
1054 for( ; It != CallRetInstList.end(); ++It ) {
1056 const MachineInstr *const CRMI = *It;
1057 unsigned OpCode = CRMI->getOpCode();
1059 // get the added instructions for this Call/Ret instruciton
1060 AddedInstrns *AI = AddedInstrMap[ CRMI ];
1062 AI = new AddedInstrns();
1063 AddedInstrMap[ CRMI ] = AI;
1066 // Tmp stack poistions are needed by some calls that have spilled args
1067 // So reset it before we call each such method
1068 //mcInfo.popAllTempValues(TM);
1072 if (TM.getInstrInfo().isCall(OpCode))
1073 MRI.colorCallArgs(CRMI, LRI, AI, *this);
1074 else if (TM.getInstrInfo().isReturn(OpCode))
1075 MRI.colorRetValue( CRMI, LRI, AI );
1077 assert(0 && "Non Call/Ret instrn in CallRetInstrList\n");
1083 //----------------------------------------------------------------------------
1085 //----------------------------------------------------------------------------
1086 void PhyRegAlloc::colorIncomingArgs()
1088 const BasicBlock *const FirstBB = Meth->front();
1089 const MachineInstr *FirstMI = FirstBB->getMachineInstrVec().front();
1090 assert(FirstMI && "No machine instruction in entry BB");
1092 AddedInstrns *AI = AddedInstrMap[FirstMI];
1094 AddedInstrMap[FirstMI] = AI = new AddedInstrns();
1096 MRI.colorMethodArgs(Meth, LRI, AI);
1100 //----------------------------------------------------------------------------
1101 // Used to generate a label for a basic block
1102 //----------------------------------------------------------------------------
1103 void PhyRegAlloc::printLabel(const Value *const Val) {
1105 cerr << Val->getName();
1107 cerr << "Label" << Val;
1111 //----------------------------------------------------------------------------
1112 // This method calls setSugColorUsable method of each live range. This
1113 // will determine whether the suggested color of LR is really usable.
1114 // A suggested color is not usable when the suggested color is volatile
1115 // AND when there are call interferences
1116 //----------------------------------------------------------------------------
1118 void PhyRegAlloc::markUnusableSugColors()
1120 if(DEBUG_RA ) cerr << "\nmarking unusable suggested colors ...\n";
1122 // hash map iterator
1123 LiveRangeMapType::const_iterator HMI = (LRI.getLiveRangeMap())->begin();
1124 LiveRangeMapType::const_iterator HMIEnd = (LRI.getLiveRangeMap())->end();
1126 for(; HMI != HMIEnd ; ++HMI ) {
1128 LiveRange *L = HMI->second; // get the LiveRange
1130 if(L->hasSuggestedColor()) {
1131 int RCID = L->getRegClass()->getID();
1132 if( MRI.isRegVolatile( RCID, L->getSuggestedColor()) &&
1133 L->isCallInterference() )
1134 L->setSuggestedColorUsable( false );
1136 L->setSuggestedColorUsable( true );
1138 } // if L->hasSuggestedColor()
1140 } // for all LR's in hash map
1145 //----------------------------------------------------------------------------
1146 // The following method will set the stack offsets of the live ranges that
1147 // are decided to be spillled. This must be called just after coloring the
1148 // LRs using the graph coloring algo. For each live range that is spilled,
1149 // this method allocate a new spill position on the stack.
1150 //----------------------------------------------------------------------------
1152 void PhyRegAlloc::allocateStackSpace4SpilledLRs() {
1153 if (DEBUG_RA) cerr << "\nsetting LR stack offsets ...\n";
1155 LiveRangeMapType::const_iterator HMI = LRI.getLiveRangeMap()->begin();
1156 LiveRangeMapType::const_iterator HMIEnd = LRI.getLiveRangeMap()->end();
1158 for( ; HMI != HMIEnd ; ++HMI) {
1159 if (HMI->first && HMI->second) {
1160 LiveRange *L = HMI->second; // get the LiveRange
1161 if (!L->hasColor()) // NOTE: ** allocating the size of long Type **
1162 L->setSpillOffFromFP(mcInfo.allocateSpilledValue(TM, Type::LongTy));
1164 } // for all LR's in hash map
1169 //----------------------------------------------------------------------------
1170 // The entry pont to Register Allocation
1171 //----------------------------------------------------------------------------
1173 void PhyRegAlloc::allocateRegisters()
1176 // make sure that we put all register classes into the RegClassList
1177 // before we call constructLiveRanges (now done in the constructor of
1178 // PhyRegAlloc class).
1180 LRI.constructLiveRanges(); // create LR info
1183 LRI.printLiveRanges();
1185 createIGNodeListsAndIGs(); // create IGNode list and IGs
1187 buildInterferenceGraphs(); // build IGs in all reg classes
1191 // print all LRs in all reg classes
1192 for( unsigned int rc=0; rc < NumOfRegClasses ; rc++)
1193 RegClassList[ rc ]->printIGNodeList();
1195 // print IGs in all register classes
1196 for( unsigned int rc=0; rc < NumOfRegClasses ; rc++)
1197 RegClassList[ rc ]->printIG();
1201 LRI.coalesceLRs(); // coalesce all live ranges
1205 // print all LRs in all reg classes
1206 for( unsigned int rc=0; rc < NumOfRegClasses ; rc++)
1207 RegClassList[ rc ]->printIGNodeList();
1209 // print IGs in all register classes
1210 for( unsigned int rc=0; rc < NumOfRegClasses ; rc++)
1211 RegClassList[ rc ]->printIG();
1215 // mark un-usable suggested color before graph coloring algorithm.
1216 // When this is done, the graph coloring algo will not reserve
1217 // suggested color unnecessarily - they can be used by another LR
1219 markUnusableSugColors();
1221 // color all register classes using the graph coloring algo
1222 for( unsigned int rc=0; rc < NumOfRegClasses ; rc++)
1223 RegClassList[ rc ]->colorAllRegs();
1225 // Atter grpah coloring, if some LRs did not receive a color (i.e, spilled)
1226 // a poistion for such spilled LRs
1228 allocateStackSpace4SpilledLRs();
1230 mcInfo.popAllTempValues(TM); // TODO **Check
1232 // color incoming args - if the correct color was not received
1233 // insert code to copy to the correct register
1235 colorIncomingArgs();
1237 // Now update the machine code with register names and add any
1238 // additional code inserted by the register allocator to the instruction
1241 updateMachineCode();
1244 MachineCodeForMethod::get(Meth).dump();
1245 printMachineCode(); // only for DEBUGGING