1 #include "llvm/CodeGen/PhyRegAlloc.h"
3 //***TODO: There are several places we add instructions. Validate the order
4 // of adding these instructions.
8 cl::Enum<RegAllocDebugLevel_t> DEBUG_RA("dregalloc", cl::NoFlags,
9 "enable register allocation debugging information",
10 clEnumValN(RA_DEBUG_None , "n", "disable debug output"),
11 clEnumValN(RA_DEBUG_Normal , "y", "enable debug output"),
12 clEnumValN(RA_DEBUG_Verbose, "v", "enable extra debug output"), 0);
15 //----------------------------------------------------------------------------
16 // Constructor: Init local composite objects and create register classes.
17 //----------------------------------------------------------------------------
18 PhyRegAlloc::PhyRegAlloc(const Method *const M,
19 const TargetMachine& tm,
20 MethodLiveVarInfo *const Lvi)
22 Meth(M), TM(tm), LVI(Lvi), LRI(M, tm, RegClassList),
23 MRI( tm.getRegInfo() ),
24 NumOfRegClasses(MRI.getNumOfRegClasses()),
25 AddedInstrMap(), StackOffsets() /*, PhiInstList()*/
28 // **TODO: use an actual reserved color list
29 ReservedColorListType *RCL = new ReservedColorListType();
31 // create each RegisterClass and put in RegClassList
32 for( unsigned int rc=0; rc < NumOfRegClasses; rc++)
33 RegClassList.push_back( new RegClass(M, MRI.getMachineRegClass(rc), RCL) );
35 // **TODO: Init to the correct value. Also reset this to the correct
36 // value at the start of each instruction. Need a way to track max used
37 int curOffset4TmpSpills =0 ;
40 //----------------------------------------------------------------------------
41 // This method initally creates interference graphs (one in each reg class)
42 // and IGNodeList (one in each IG). The actual nodes will be pushed later.
43 //----------------------------------------------------------------------------
45 void PhyRegAlloc::createIGNodeListsAndIGs()
47 if(DEBUG_RA ) cout << "Creating LR lists ..." << endl;
50 LiveRangeMapType::const_iterator HMI = (LRI.getLiveRangeMap())->begin();
53 LiveRangeMapType::const_iterator HMIEnd = (LRI.getLiveRangeMap())->end();
55 for( ; HMI != HMIEnd ; ++HMI ) {
59 LiveRange *L = (*HMI).second; // get the LiveRange
63 cout << "\n*?!?Warning: Null liver range found for: ";
64 printValue( (*HMI).first) ; cout << endl;
68 // if the Value * is not null, and LR
69 // is not yet written to the IGNodeList
70 if( !(L->getUserIGNode()) ) {
72 RegClass *const RC = // RegClass of first value in the LR
73 //RegClassList [MRI.getRegClassIDOfValue(*(L->begin()))];
74 RegClassList[ L->getRegClass()->getID() ];
76 RC-> addLRToIG( L ); // add this LR to an IG
82 for( unsigned int rc=0; rc < NumOfRegClasses ; rc++)
83 RegClassList[ rc ]->createInterferenceGraph();
86 cout << "LRLists Created!" << endl;
91 //----------------------------------------------------------------------------
92 // This method will add all interferences at for a given instruction.
93 // Interence occurs only if the LR of Def (Inst or Arg) is of the same reg
94 // class as that of live var. The live var passed to this function is the
95 // LVset AFTER the instruction
96 //----------------------------------------------------------------------------
98 void PhyRegAlloc::addInterference(const Value *const Def,
99 const LiveVarSet *const LVSet,
100 const bool isCallInst) {
102 LiveVarSet::const_iterator LIt = LVSet->begin();
104 // get the live range of instruction
105 const LiveRange *const LROfDef = LRI.getLiveRangeForValue( Def );
107 IGNode *const IGNodeOfDef = LROfDef->getUserIGNode();
108 assert( IGNodeOfDef );
110 RegClass *const RCOfDef = LROfDef->getRegClass();
112 // for each live var in live variable set
113 for( ; LIt != LVSet->end(); ++LIt) {
116 cout << "< Def="; printValue(Def);
117 cout << ", Lvar="; printValue( *LIt); cout << "> ";
120 // get the live range corresponding to live var
121 LiveRange *const LROfVar = LRI.getLiveRangeForValue(*LIt );
123 // LROfVar can be null if it is a const since a const
124 // doesn't have a dominating def - see Assumptions above
127 if(LROfDef == LROfVar) // do not set interf for same LR
130 // if 2 reg classes are the same set interference
131 if( RCOfDef == LROfVar->getRegClass() ){
132 RCOfDef->setInterference( LROfDef, LROfVar);
136 else if(DEBUG_RA > 1) {
137 // we will not have LRs for values not explicitly allocated in the
138 // instruction stream (e.g., constants)
139 cout << " warning: no live range for " ;
140 printValue( *LIt); cout << endl; }
149 //----------------------------------------------------------------------------
150 // For a call instruction, this method sets the CallInterference flag in
151 // the LR of each variable live int the Live Variable Set live after the
152 // call instruction (except the return value of the call instruction - since
153 // the return value does not interfere with that call itself).
154 //----------------------------------------------------------------------------
156 void PhyRegAlloc::setCallInterferences(const MachineInstr *MInst,
157 const LiveVarSet *const LVSetAft )
159 // Now find the LR of the return value of the call
162 // We do this because, we look at the LV set *after* the instruction
163 // to determine, which LRs must be saved across calls. The return value
164 // of the call is live in this set - but it does not interfere with call
165 // (i.e., we can allocate a volatile register to the return value)
167 LiveRange *RetValLR = NULL;
169 const Value *RetVal = MRI.getCallInstRetVal( MInst );
172 RetValLR = LRI.getLiveRangeForValue( RetVal );
173 assert( RetValLR && "No LR for RetValue of call");
177 cout << "\n For call inst: " << *MInst;
179 LiveVarSet::const_iterator LIt = LVSetAft->begin();
181 // for each live var in live variable set after machine inst
182 for( ; LIt != LVSetAft->end(); ++LIt) {
184 // get the live range corresponding to live var
185 LiveRange *const LR = LRI.getLiveRangeForValue(*LIt );
187 if( LR && DEBUG_RA) {
188 cout << "\n\tLR Aft Call: ";
193 // LR can be null if it is a const since a const
194 // doesn't have a dominating def - see Assumptions above
195 if( LR && (LR != RetValLR) ) {
196 LR->setCallInterference();
198 cout << "\n ++Added call interf for LR: " ;
208 //----------------------------------------------------------------------------
209 // This method will walk thru code and create interferences in the IG of
211 //----------------------------------------------------------------------------
213 void PhyRegAlloc::buildInterferenceGraphs()
216 if(DEBUG_RA) cout << "Creating interference graphs ..." << endl;
218 Method::const_iterator BBI = Meth->begin(); // random iterator for BBs
220 for( ; BBI != Meth->end(); ++BBI) { // traverse BBs in random order
222 // get the iterator for machine instructions
223 const MachineCodeForBasicBlock& MIVec = (*BBI)->getMachineInstrVec();
224 MachineCodeForBasicBlock::const_iterator
225 MInstIterator = MIVec.begin();
227 // iterate over all the machine instructions in BB
228 for( ; MInstIterator != MIVec.end(); ++MInstIterator) {
230 const MachineInstr * MInst = *MInstIterator;
232 // get the LV set after the instruction
233 const LiveVarSet *const LVSetAI =
234 LVI->getLiveVarSetAfterMInst(MInst, *BBI);
236 const bool isCallInst = TM.getInstrInfo().isCall(MInst->getOpCode());
239 //cout << "\nFor call inst: " << *MInst;
241 // set the isCallInterference flag of each live range wich extends
242 // accross this call instruction. This information is used by graph
243 // coloring algo to avoid allocating volatile colors to live ranges
244 // that span across calls (since they have to be saved/restored)
245 setCallInterferences( MInst, LVSetAI);
249 // iterate over MI operands to find defs
250 for( MachineInstr::val_op_const_iterator OpI(MInst);!OpI.done(); ++OpI) {
253 // create a new LR iff this operand is a def
254 addInterference(*OpI, LVSetAI, isCallInst );
258 } // for all operands
261 // Also add interference for any implicit definitions in a machine
262 // instr (currently, only calls have this).
264 unsigned NumOfImpRefs = MInst->getNumImplicitRefs();
265 if( NumOfImpRefs > 0 ) {
266 for(unsigned z=0; z < NumOfImpRefs; z++)
267 if( MInst->implicitRefIsDefined(z) )
268 addInterference( MInst->getImplicitRef(z), LVSetAI, isCallInst );
272 // record phi instrns in PhiInstList
273 if( TM.getInstrInfo().isDummyPhiInstr(MInst->getOpCode()) )
274 PhiInstList.push_back( MInst );
277 } // for all machine instructions in BB
279 } // for all BBs in method
282 // add interferences for method arguments. Since there are no explict
283 // defs in method for args, we have to add them manually
285 addInterferencesForArgs(); // add interference for method args
288 cout << "Interference graphs calculted!" << endl;
295 //----------------------------------------------------------------------------
296 // This method will add interferences for incoming arguments to a method.
297 //----------------------------------------------------------------------------
298 void PhyRegAlloc::addInterferencesForArgs()
300 // get the InSet of root BB
301 const LiveVarSet *const InSet = LVI->getInSetOfBB( Meth->front() );
303 // get the argument list
304 const Method::ArgumentListType& ArgList = Meth->getArgumentList();
306 // get an iterator to arg list
307 Method::ArgumentListType::const_iterator ArgIt = ArgList.begin();
310 for( ; ArgIt != ArgList.end() ; ++ArgIt) { // for each argument
311 addInterference( *ArgIt, InSet, false ); // add interferences between
312 // args and LVars at start
314 cout << " - %% adding interference for argument ";
315 printValue( (const Value *) *ArgIt); cout << endl;
324 //----------------------------------------------------------------------------
325 // This method inserts caller saving/restoring instructons before/after
326 // a call machine instruction.
327 //----------------------------------------------------------------------------
330 void PhyRegAlloc::insertCallerSavingCode(const MachineInstr *MInst,
331 const BasicBlock *BB )
333 // assert( (TM.getInstrInfo()).isCall( MInst->getOpCode() ) );
335 StackOffsets.resetTmpPos();
337 hash_set<unsigned> PushedRegSet;
339 // Now find the LR of the return value of the call
340 // The last *implicit operand* is the return value of a call
341 // Insert it to to he PushedRegSet since we must not save that register
342 // and restore it after the call.
343 // We do this because, we look at the LV set *after* the instruction
344 // to determine, which LRs must be saved across calls. The return value
345 // of the call is live in this set - but we must not save/restore it.
348 const Value *RetVal = MRI.getCallInstRetVal( MInst );
352 LiveRange *RetValLR = LRI.getLiveRangeForValue( RetVal );
353 assert( RetValLR && "No LR for RetValue of call");
356 MRI.getUnifiedRegNum((RetValLR->getRegClass())->getID(),
357 RetValLR->getColor() ) );
361 const LiveVarSet *LVSetAft = LVI->getLiveVarSetAfterMInst(MInst, BB);
363 LiveVarSet::const_iterator LIt = LVSetAft->begin();
365 // for each live var in live variable set after machine inst
366 for( ; LIt != LVSetAft->end(); ++LIt) {
368 // get the live range corresponding to live var
369 LiveRange *const LR = LRI.getLiveRangeForValue(*LIt );
371 // LR can be null if it is a const since a const
372 // doesn't have a dominating def - see Assumptions above
375 if( LR->hasColor() ) {
377 unsigned RCID = (LR->getRegClass())->getID();
378 unsigned Color = LR->getColor();
380 if ( MRI.isRegVolatile(RCID, Color) ) {
382 // if the value is in both LV sets (i.e., live before and after
383 // the call machine instruction)
385 unsigned Reg = MRI.getUnifiedRegNum(RCID, Color);
387 if( PushedRegSet.find(Reg) == PushedRegSet.end() ) {
389 // if we haven't already pushed that register
391 unsigned RegType = MRI.getRegType( LR );
393 // Now get two instructions - to push on stack and pop from stack
394 // and add them to InstrnsBefore and InstrnsAfter of the
397 int StackOff = StackOffsets.getNewTmpPosOffFromSP();
401 if( RegType == SaveViaIntReg) {
403 int FreeIntReg = getFreedIntReg(......)
409 MachineInstr *AdIBef =
410 MRI.cpReg2MemMI(Reg, MRI.getStackPointer(), StackOff, RegType );
412 MachineInstr *AdIAft =
413 MRI.cpMem2RegMI(MRI.getStackPointer(), StackOff, Reg, RegType );
415 ((AddedInstrMap[MInst])->InstrnsBefore).push_front(AdIBef);
416 ((AddedInstrMap[MInst])->InstrnsAfter).push_back(AdIAft);
418 PushedRegSet.insert( Reg );
421 cerr << "\nFor callee save call inst:" << *MInst;
422 cerr << "\n -inserted caller saving instrs:\n\t ";
423 cerr << *AdIBef << "\n\t" << *AdIAft ;
425 } // if not already pushed
427 } // if LR has a volatile color
431 } // if there is a LR for Var
433 } // for each value in the LV set after instruction
440 //----------------------------------------------------------------------------
441 // This method is called after register allocation is complete to set the
442 // allocated reisters in the machine code. This code will add register numbers
443 // to MachineOperands that contain a Value.
444 //----------------------------------------------------------------------------
446 void PhyRegAlloc::updateMachineCode()
449 Method::const_iterator BBI = Meth->begin(); // random iterator for BBs
451 for( ; BBI != Meth->end(); ++BBI) { // traverse BBs in random order
453 // get the iterator for machine instructions
454 MachineCodeForBasicBlock& MIVec = (*BBI)->getMachineInstrVec();
455 MachineCodeForBasicBlock::iterator MInstIterator = MIVec.begin();
457 // iterate over all the machine instructions in BB
458 for( ; MInstIterator != MIVec.end(); ++MInstIterator) {
460 MachineInstr *MInst = *MInstIterator;
462 // if this machine instr is call, insert caller saving code
464 if( (TM.getInstrInfo()).isCall( MInst->getOpCode()) )
465 MRI.insertCallerSavingCode(MInst, *BBI, *this );
467 // If there are instructions to be added, *before* this machine
468 // instruction, add them now.
470 if( AddedInstrMap[ MInst ] ) {
472 deque<MachineInstr *> &IBef = (AddedInstrMap[MInst])->InstrnsBefore;
474 if( ! IBef.empty() ) {
476 deque<MachineInstr *>::iterator AdIt;
478 for( AdIt = IBef.begin(); AdIt != IBef.end() ; ++AdIt ) {
481 cerr << " *$* PREPENDed instr " << *AdIt << endl;
483 MInstIterator = MIVec.insert( MInstIterator, *AdIt );
491 // reset the stack offset for temporary variables since we may
492 // need that to spill
493 StackOffsets.resetTmpPos();
495 //for(MachineInstr::val_op_const_iterator OpI(MInst);!OpI.done();++OpI) {
497 for(unsigned OpNum=0; OpNum < MInst->getNumOperands(); ++OpNum) {
499 MachineOperand& Op = MInst->getOperand(OpNum);
501 if( Op.getOperandType() == MachineOperand::MO_VirtualRegister ||
502 Op.getOperandType() == MachineOperand::MO_CCRegister) {
504 const Value *const Val = Op.getVRegValue();
506 // delete this condition checking later (must assert if Val is null)
509 cout << "Warning: NULL Value found for operand" << endl;
512 assert( Val && "Value is NULL");
514 LiveRange *const LR = LRI.getLiveRangeForValue(Val);
518 // nothing to worry if it's a const or a label
521 cout << "*NO LR for operand : " << Op ;
522 cout << " [reg:" << Op.getAllocatedRegNum() << "]";
523 cout << " in inst:\t" << *MInst << endl;
526 // if register is not allocated, mark register as invalid
527 if( Op.getAllocatedRegNum() == -1)
528 Op.setRegForValue( MRI.getInvalidRegNum());
534 unsigned RCID = (LR->getRegClass())->getID();
536 if( LR->hasColor() ) {
537 Op.setRegForValue( MRI.getUnifiedRegNum(RCID, LR->getColor()) );
541 // LR did NOT receive a color (register). Now, insert spill code
542 // for spilled opeands in this machine instruction
544 assert(0 && "LR must be spilled");
545 // insertCode4SpilledLR(LR, MInst, *BBI, OpNum );
550 } // for each operand
553 // If there are instructions to be added *after* this machine
554 // instruction, add them now
556 if( AddedInstrMap[ MInst ] &&
557 ! (AddedInstrMap[ MInst ]->InstrnsAfter).empty() ) {
559 // if there are delay slots for this instruction, the instructions
560 // added after it must really go after the delayed instruction(s)
561 // So, we move the InstrAfter of the current instruction to the
562 // corresponding delayed instruction
565 if((delay=TM.getInstrInfo().getNumDelaySlots(MInst->getOpCode())) >0){
566 move2DelayedInstr(MInst, *(MInstIterator+delay) );
568 if(DEBUG_RA) cout<< "\nMoved an added instr after the delay slot";
574 // Here we can add the "instructions after" to the current
575 // instruction since there are no delay slots for this instruction
577 deque<MachineInstr *> &IAft = (AddedInstrMap[MInst])->InstrnsAfter;
579 if( ! IAft.empty() ) {
581 deque<MachineInstr *>::iterator AdIt;
583 ++MInstIterator; // advance to the next instruction
585 for( AdIt = IAft.begin(); AdIt != IAft.end() ; ++AdIt ) {
588 cerr << " *#* APPENDed instr opcode: " << *AdIt << endl;
590 MInstIterator = MIVec.insert( MInstIterator, *AdIt );
594 // MInsterator already points to the next instr. Since the
595 // for loop also increments it, decrement it to point to the
596 // instruction added last
605 } // for each machine instruction
614 //----------------------------------------------------------------------------
615 // This method inserts spill code for AN operand whose LR was spilled.
616 // This method may be called several times for a single machine instruction
617 // if it contains many spilled operands. Each time it is called, it finds
618 // a register which is not live at that instruction and also which is not
619 // used by other spilled operands of the same instruction. Then it uses
620 // this register temporarily to accomodate the spilled value.
621 //----------------------------------------------------------------------------
622 void PhyRegAlloc::insertCode4SpilledLR(const LiveRange *LR,
623 const MachineInstr *MInst,
624 const BasisBlock *BB,
625 const unsigned OpNum) {
627 MachineOperand& Op = MInst->getOperand(OpNum);
628 bool isDef = MInst->operandIsDefined(OpNum);
629 unsigned RegType = MRI.getRegType( LR );
630 int SpillOff = LR->getSpillOffFromFP();
631 RegClass *RC = LR->getRegClass();
632 const LiveVarSet *LVSetBef = LVI->getLiveVarSetBeforeMInst(MInst, BB);
633 int TmpOff = StackOffsets.getNewTmpPosOffFromSP();
634 MachineInstr *MIBef, *AdIMid, *MIAft;
637 TmpReg = getUsableRegAtMI(RC, RegType, MInst,LVSetBef, MIBef, MIAft);
638 TmpReg = getUnifiedRegNum( RC->getID(), TmpReg );
643 // for a USE, we have to load the value of LR from stack to a TmpReg
644 // and use the TmpReg as one operand of instruction
646 // actual loading instruction
647 AdIMid = MRI.cpMem2RegMI(MRI.getFramePointer(), SpillOff, TmpReg, RegType);
650 ((AddedInstrMap[MInst])->InstrnsBefore).push_back(MIBef);
652 ((AddedInstrMap[MInst])->InstrnsBefore).push_back(AdiMid);
655 ((AddedInstrMap[MInst])->InstrnsAfter).push_front(MIAft);
659 else { // if this is a Def
661 // for a DEF, we have to store the value produced by this instruction
662 // on the stack position allocated for this LR
664 // actual storing instruction
665 AdIMid = MRI.cpReg2MemMI(TmpReg, MRI.getFramePointer(), SpillOff, RegType);
668 ((AddedInstrMap[MInst])->InstrnsBefore).push_back(MIBef);
670 ((AddedInstrMap[MInst])->InstrnsBefore).push_back(AdiMid);
673 ((AddedInstrMap[MInst])->InstrnsAfter).push_front(MIAft);
678 Op.setRegForValue( TmpReg ); // set the opearnd
686 //----------------------------------------------------------------------------
687 // We can use the following method to get a temporary register to be used
688 // BEFORE any given machine instruction. If there is a register available,
689 // this method will simply return that register and set MIBef = MIAft = NULL.
690 // Otherwise, it will return a register and MIAft and MIBef will contain
691 // two instructions used to free up this returned register.
692 // Returned register number is the UNIFIED register number
693 //----------------------------------------------------------------------------
695 int PhyRegAlloc::getUsableRegAtMI(RegClass *RC,
697 const MachineInstr *MInst,
698 const LiveVarSet *LVSetBef,
700 MachineInstr *MIAft) {
702 int Reg = getUnusedRegAtMI(RC, MInst, LVSetBef);
703 Reg = MRI.getUnifiedRegNum(RC->getID(), Reg);
706 // we found an unused register, so we can simply used
707 MIBef = MIAft = NULL;
710 // we couldn't find an unused register. Generate code to free up a reg by
711 // saving it on stack and restoring after the instruction
713 int TmpOff = StackOffsets.getNewTmpPosOffFromFP();
715 Reg = getRegNotUsedByThisInst(RC, MInst);
716 MIBef = MRI.cpReg2MemMI(Reg, MRI.getFramePointer(), TmpOff, RegType );
717 MIAft = MRI.cpMem2RegMI(MRI.getFramePointer(), TmpOff, Reg, RegType );
723 //----------------------------------------------------------------------------
724 // This method is called to get a new unused register that can be used to
725 // accomodate a spilled value.
726 // This method may be called several times for a single machine instruction
727 // if it contains many spilled operands. Each time it is called, it finds
728 // a register which is not live at that instruction and also which is not
729 // used by other spilled operands of the same instruction.
730 // Return register number is relative to the register class. NOT
732 //----------------------------------------------------------------------------
733 int PhyRegAlloc::getUnusedRegAtMI(RegClass *RC,
734 const MachineInstr *MInst,
735 const LiveVarSet *LVSetBef) {
737 unsigned NumAvailRegs = RC->getNumOfAvailRegs();
739 bool *IsColorUsedArr = RC->getIsColorUsedArr();
741 for(unsigned i=0; i < NumAvailRegs; i++)
742 IsColorUsedArr[i] = false;
744 LiveVarSet::const_iterator LIt = LVSetBef->begin();
746 // for each live var in live variable set after machine inst
747 for( ; LIt != LVSetBef->end(); ++LIt) {
749 // get the live range corresponding to live var
750 LiveRange *const LRofLV = LRI.getLiveRangeForValue(*LIt );
752 // LR can be null if it is a const since a const
753 // doesn't have a dominating def - see Assumptions above
755 if( LRofLV->hasColor() )
756 IsColorUsedArr[ LRofLV->getColor() ] = true;
759 // It is possible that one operand of this MInst was already spilled
760 // and it received some register temporarily. If that's the case,
761 // it is recorded in machine operand. We must skip such registers.
763 setRegsUsedByThisInst(RC, MInst);
765 unsigned c; // find first unused color
766 for( c=0; c < NumAvailRegs; c++)
767 if( ! IsColorUsedArr[ c ] ) break;
779 //----------------------------------------------------------------------------
780 // This method modifies the IsColorUsedArr of the register class passed to it.
781 // It sets the bits corresponding to the registers used by this machine
782 // instructions. Explicit operands are set.
783 //----------------------------------------------------------------------------
784 void PhyRegAlloc::setRegsUsedByThisInst(RegClass *RC,
785 const MachineInstr *MInst ) {
787 bool *IsColorUsedArr = RC->getIsColorUsedArr();
789 for(unsigned OpNum=0; OpNum < MInst->getNumOperands(); ++OpNum) {
791 const MachineOperand& Op = MInst->getOperand(OpNum);
793 if( Op.getOperandType() == MachineOperand::MO_VirtualRegister ||
794 Op.getOperandType() == MachineOperand::MO_CCRegister) {
796 const Value *const Val = Op.getVRegValue();
799 if( MRI.getRegClassIDOfValue( Val )== RC->getID() ) {
801 if( (Reg=Op.getAllocatedRegNum()) != -1)
802 IsColorUsedArr[ Reg ] = true;
808 // If there are implicit references, mark them as well
810 for(unsigned z=0; z < MInst->getNumImplicitRefs(); z++) {
812 LiveRange *const LRofImpRef =
813 LRI.getLiveRangeForValue( MInst->getImplicitRef(z) );
816 if( LRofImpRef->hasColor() )
817 IsColorUsedArr[ LRofImpRef->getColor() ] = true;
826 //----------------------------------------------------------------------------
827 // Get any other register in a register class, other than what is used
828 // by operands of a machine instruction.
829 //----------------------------------------------------------------------------
830 int PhyRegAlloc::getRegNotUsedByThisInst(RegClass *RC,
831 const MachineInstr *MInst) {
833 bool *IsColorUsedArr = RC->getIsColorUsedArr();
834 unsigned NumAvailRegs = RC->getNumOfAvailRegs();
837 for(unsigned i=0; i < NumAvailRegs ; i++)
838 IsColorUsedArr[i] = false;
840 setRegsUsedByThisInst(RC, MInst);
842 unsigned c; // find first unused color
843 for( c=0; c < RC->getNumOfAvailRegs(); c++)
844 if( ! IsColorUsedArr[ c ] ) break;
849 assert( 0 && "FATAL: No free register could be found in reg class!!");
857 //----------------------------------------------------------------------------
858 // If there are delay slots for an instruction, the instructions
859 // added after it must really go after the delayed instruction(s).
860 // So, we move the InstrAfter of that instruction to the
861 // corresponding delayed instruction using the following method.
863 //----------------------------------------------------------------------------
864 void PhyRegAlloc:: move2DelayedInstr(const MachineInstr *OrigMI,
865 const MachineInstr *DelayedMI) {
868 // "added after" instructions of the original instr
869 deque<MachineInstr *> &OrigAft = (AddedInstrMap[OrigMI])->InstrnsAfter;
871 // "added instructions" of the delayed instr
872 AddedInstrns *DelayAdI = AddedInstrMap[DelayedMI];
874 if(! DelayAdI ) { // create a new "added after" if necessary
875 DelayAdI = new AddedInstrns();
876 AddedInstrMap[DelayedMI] = DelayAdI;
879 // "added after" instructions of the delayed instr
880 deque<MachineInstr *> &DelayedAft = DelayAdI->InstrnsAfter;
882 // go thru all the "added after instructions" of the original instruction
883 // and append them to the "addded after instructions" of the delayed
886 deque<MachineInstr *>::iterator OrigAdIt;
888 for( OrigAdIt = OrigAft.begin(); OrigAdIt != OrigAft.end() ; ++OrigAdIt ) {
889 DelayedAft.push_back( *OrigAdIt );
892 // empty the "added after instructions" of the original instruction
897 //----------------------------------------------------------------------------
898 // This method prints the code with registers after register allocation is
900 //----------------------------------------------------------------------------
901 void PhyRegAlloc::printMachineCode()
904 cout << endl << ";************** Method ";
905 cout << Meth->getName() << " *****************" << endl;
907 Method::const_iterator BBI = Meth->begin(); // random iterator for BBs
909 for( ; BBI != Meth->end(); ++BBI) { // traverse BBs in random order
911 cout << endl ; printLabel( *BBI); cout << ": ";
913 // get the iterator for machine instructions
914 MachineCodeForBasicBlock& MIVec = (*BBI)->getMachineInstrVec();
915 MachineCodeForBasicBlock::iterator MInstIterator = MIVec.begin();
917 // iterate over all the machine instructions in BB
918 for( ; MInstIterator != MIVec.end(); ++MInstIterator) {
920 MachineInstr *const MInst = *MInstIterator;
923 cout << endl << "\t";
924 cout << TargetInstrDescriptors[MInst->getOpCode()].opCodeString;
927 //for(MachineInstr::val_op_const_iterator OpI(MInst);!OpI.done();++OpI) {
929 for(unsigned OpNum=0; OpNum < MInst->getNumOperands(); ++OpNum) {
931 MachineOperand& Op = MInst->getOperand(OpNum);
933 if( Op.getOperandType() == MachineOperand::MO_VirtualRegister ||
934 Op.getOperandType() == MachineOperand::MO_CCRegister /*||
935 Op.getOperandType() == MachineOperand::MO_PCRelativeDisp*/ ) {
937 const Value *const Val = Op.getVRegValue () ;
938 // ****this code is temporary till NULL Values are fixed
940 cout << "\t<*NULL*>";
944 // if a label or a constant
945 if( (Val->getValueType() == Value::BasicBlockVal) ) {
947 cout << "\t"; printLabel( Op.getVRegValue () );
950 // else it must be a register value
951 const int RegNum = Op.getAllocatedRegNum();
953 cout << "\t" << "%" << MRI.getUnifiedRegName( RegNum );
957 else if(Op.getOperandType() == MachineOperand::MO_MachineRegister) {
958 cout << "\t" << "%" << MRI.getUnifiedRegName(Op.getMachineRegNum());
962 cout << "\t" << Op; // use dump field
967 unsigned NumOfImpRefs = MInst->getNumImplicitRefs();
968 if( NumOfImpRefs > 0 ) {
970 cout << "\tImplicit:";
972 for(unsigned z=0; z < NumOfImpRefs; z++) {
973 printValue( MInst->getImplicitRef(z) );
979 } // for all machine instructions
990 //----------------------------------------------------------------------------
992 //----------------------------------------------------------------------------
994 void PhyRegAlloc::colorCallRetArgs()
997 CallRetInstrListType &CallRetInstList = LRI.getCallRetInstrList();
998 CallRetInstrListType::const_iterator It = CallRetInstList.begin();
1000 for( ; It != CallRetInstList.end(); ++It ) {
1002 const MachineInstr *const CRMI = *It;
1003 unsigned OpCode = CRMI->getOpCode();
1005 // get the added instructions for this Call/Ret instruciton
1006 AddedInstrns *AI = AddedInstrMap[ CRMI ];
1008 AI = new AddedInstrns();
1009 AddedInstrMap[ CRMI ] = AI;
1012 // Tmp stack poistions are needed by some calls that have spilled args
1013 // So reset it before we call each such method
1014 StackOffsets.resetTmpPos();
1016 if( (TM.getInstrInfo()).isCall( OpCode ) )
1017 MRI.colorCallArgs( CRMI, LRI, AI, *this );
1019 else if ( (TM.getInstrInfo()).isReturn(OpCode) )
1020 MRI.colorRetValue( CRMI, LRI, AI );
1022 else assert( 0 && "Non Call/Ret instrn in CallRetInstrList\n" );
1030 //----------------------------------------------------------------------------
1032 //----------------------------------------------------------------------------
1033 void PhyRegAlloc::colorIncomingArgs()
1035 const BasicBlock *const FirstBB = Meth->front();
1036 const MachineInstr *FirstMI = *((FirstBB->getMachineInstrVec()).begin());
1037 assert( FirstMI && "No machine instruction in entry BB");
1039 AddedInstrns *AI = AddedInstrMap[ FirstMI ];
1041 AI = new AddedInstrns();
1042 AddedInstrMap[ FirstMI ] = AI;
1045 MRI.colorMethodArgs(Meth, LRI, AI );
1049 //----------------------------------------------------------------------------
1050 // Used to generate a label for a basic block
1051 //----------------------------------------------------------------------------
1052 void PhyRegAlloc::printLabel(const Value *const Val)
1054 if( Val->hasName() )
1055 cout << Val->getName();
1057 cout << "Label" << Val;
1061 //----------------------------------------------------------------------------
1062 // This method calls setSugColorUsable method of each live range. This
1063 // will determine whether the suggested color of LR is really usable.
1064 // A suggested color is not usable when the suggested color is volatile
1065 // AND when there are call interferences
1066 //----------------------------------------------------------------------------
1068 void PhyRegAlloc::markUnusableSugColors()
1070 if(DEBUG_RA ) cout << "\nmarking unusable suggested colors ..." << endl;
1072 // hash map iterator
1073 LiveRangeMapType::const_iterator HMI = (LRI.getLiveRangeMap())->begin();
1074 LiveRangeMapType::const_iterator HMIEnd = (LRI.getLiveRangeMap())->end();
1076 for( ; HMI != HMIEnd ; ++HMI ) {
1078 if( (*HMI).first ) {
1080 LiveRange *L = (*HMI).second; // get the LiveRange
1083 if( L->hasSuggestedColor() ) {
1085 int RCID = (L->getRegClass())->getID();
1086 if( MRI.isRegVolatile( RCID, L->getSuggestedColor()) &&
1087 L->isCallInterference() )
1088 L->setSuggestedColorUsable( false );
1090 L->setSuggestedColorUsable( true );
1092 } // if L->hasSuggestedColor()
1094 } // for all LR's in hash map
1099 //----------------------------------------------------------------------------
1100 // The following method will set the stack offsets of the live ranges that
1101 // are decided to be spillled. This must be called just after coloring the
1102 // LRs using the graph coloring algo. For each live range that is spilled,
1103 // this method allocate a new spill position on the stack.
1104 //----------------------------------------------------------------------------
1106 void PhyRegAlloc::allocateStackSpace4SpilledLRs()
1108 if(DEBUG_RA ) cout << "\nsetting LR stack offsets ..." << endl;
1110 // hash map iterator
1111 LiveRangeMapType::const_iterator HMI = (LRI.getLiveRangeMap())->begin();
1112 LiveRangeMapType::const_iterator HMIEnd = (LRI.getLiveRangeMap())->end();
1114 for( ; HMI != HMIEnd ; ++HMI ) {
1116 if( (*HMI).first ) {
1117 LiveRange *L = (*HMI).second; // get the LiveRange
1119 if( ! L->hasColor() )
1120 L->setSpillOffFromFP( StackOffsets.getNewSpillOffFromFP() );
1122 } // for all LR's in hash map
1124 StackOffsets.setEndOfSpillRegion();
1130 //----------------------------------------------------------------------------
1131 // The entry pont to Register Allocation
1132 //----------------------------------------------------------------------------
1134 void PhyRegAlloc::allocateRegisters()
1137 // make sure that we put all register classes into the RegClassList
1138 // before we call constructLiveRanges (now done in the constructor of
1139 // PhyRegAlloc class).
1141 constructLiveRanges(); // create LR info
1144 LRI.printLiveRanges();
1146 createIGNodeListsAndIGs(); // create IGNode list and IGs
1148 buildInterferenceGraphs(); // build IGs in all reg classes
1152 // print all LRs in all reg classes
1153 for( unsigned int rc=0; rc < NumOfRegClasses ; rc++)
1154 RegClassList[ rc ]->printIGNodeList();
1156 // print IGs in all register classes
1157 for( unsigned int rc=0; rc < NumOfRegClasses ; rc++)
1158 RegClassList[ rc ]->printIG();
1161 LRI.coalesceLRs(); // coalesce all live ranges
1163 // coalscing could not get rid of all phi's, add phi elimination
1165 // insertPhiEleminateInstrns();
1168 // print all LRs in all reg classes
1169 for( unsigned int rc=0; rc < NumOfRegClasses ; rc++)
1170 RegClassList[ rc ]->printIGNodeList();
1172 // print IGs in all register classes
1173 for( unsigned int rc=0; rc < NumOfRegClasses ; rc++)
1174 RegClassList[ rc ]->printIG();
1178 // mark un-usable suggested color before graph coloring algorithm.
1179 // When this is done, the graph coloring algo will not reserve
1180 // suggested color unnecessarily - they can be used by another LR
1181 markUnusableSugColors();
1183 // color all register classes using the graph coloring algo
1184 for( unsigned int rc=0; rc < NumOfRegClasses ; rc++)
1185 RegClassList[ rc ]->colorAllRegs();
1187 // Atter grpah coloring, if some LRs did not receive a color (i.e, spilled)
1188 // a poistion for such spilled LRs
1189 allocateStackSpace4SpilledLRs();
1191 // color incoming args and call args
1192 colorIncomingArgs();
1196 updateMachineCode();
1198 Meth->getMachineCode().dump();
1199 printMachineCode(); // only for DEBUGGING