2 //***************************************************************************
7 // Register allocation for LLVM.
10 // 9/10/01 - Ruchira Sasanka - created.
11 //**************************************************************************/
13 #include "llvm/CodeGen/RegisterAllocation.h"
14 #include "llvm/CodeGen/PhyRegAlloc.h"
15 #include "llvm/CodeGen/MachineInstr.h"
16 #include "llvm/CodeGen/MachineCodeForMethod.h"
17 #include "llvm/Analysis/LiveVar/MethodLiveVarInfo.h"
18 #include "llvm/Analysis/LiveVar/LiveVarSet.h"
19 #include "llvm/Analysis/LoopInfo.h"
20 #include "llvm/Target/TargetMachine.h"
21 #include "llvm/Target/MachineFrameInfo.h"
22 #include "llvm/Method.h"
28 // ***TODO: There are several places we add instructions. Validate the order
29 // of adding these instructions.
31 cl::Enum<RegAllocDebugLevel_t> DEBUG_RA("dregalloc", cl::NoFlags,
32 "enable register allocation debugging information",
33 clEnumValN(RA_DEBUG_None , "n", "disable debug output"),
34 clEnumValN(RA_DEBUG_Normal , "y", "enable debug output"),
35 clEnumValN(RA_DEBUG_Verbose, "v", "enable extra debug output"), 0);
38 //----------------------------------------------------------------------------
39 // RegisterAllocation pass front end...
40 //----------------------------------------------------------------------------
42 class RegisterAllocator : public MethodPass {
43 TargetMachine &Target;
45 inline RegisterAllocator(TargetMachine &T) : Target(T) {}
47 bool runOnMethod(Method *M) {
49 cerr << "\n******************** Method "<< M->getName()
50 << " ********************\n";
52 PhyRegAlloc PRA(M, Target, &getAnalysis<MethodLiveVarInfo>(),
53 &getAnalysis<cfg::LoopInfo>());
54 PRA.allocateRegisters();
56 if (DEBUG_RA) cerr << "\nRegister allocation complete!\n";
60 virtual void getAnalysisUsageInfo(Pass::AnalysisSet &Requires,
61 Pass::AnalysisSet &Destroyed,
62 Pass::AnalysisSet &Provided) {
63 Requires.push_back(cfg::LoopInfo::ID);
64 Requires.push_back(MethodLiveVarInfo::ID);
69 MethodPass *getRegisterAllocator(TargetMachine &T) {
70 return new RegisterAllocator(T);
73 //----------------------------------------------------------------------------
74 // Constructor: Init local composite objects and create register classes.
75 //----------------------------------------------------------------------------
76 PhyRegAlloc::PhyRegAlloc(Method *M,
77 const TargetMachine& tm,
78 MethodLiveVarInfo *Lvi,
81 mcInfo(MachineCodeForMethod::get(M)),
82 LVI(Lvi), LRI(M, tm, RegClassList),
83 MRI( tm.getRegInfo() ),
84 NumOfRegClasses(MRI.getNumOfRegClasses()),
87 // create each RegisterClass and put in RegClassList
89 for(unsigned int rc=0; rc < NumOfRegClasses; rc++)
90 RegClassList.push_back( new RegClass(M, MRI.getMachineRegClass(rc),
95 //----------------------------------------------------------------------------
96 // Destructor: Deletes register classes
97 //----------------------------------------------------------------------------
98 PhyRegAlloc::~PhyRegAlloc() {
99 for( unsigned int rc=0; rc < NumOfRegClasses; rc++)
100 delete RegClassList[rc];
103 //----------------------------------------------------------------------------
104 // This method initally creates interference graphs (one in each reg class)
105 // and IGNodeList (one in each IG). The actual nodes will be pushed later.
106 //----------------------------------------------------------------------------
107 void PhyRegAlloc::createIGNodeListsAndIGs() {
108 if (DEBUG_RA) cerr << "Creating LR lists ...\n";
111 LiveRangeMapType::const_iterator HMI = LRI.getLiveRangeMap()->begin();
114 LiveRangeMapType::const_iterator HMIEnd = LRI.getLiveRangeMap()->end();
116 for (; HMI != HMIEnd ; ++HMI ) {
118 LiveRange *L = HMI->second; // get the LiveRange
121 cerr << "\n*?!?Warning: Null liver range found for: ";
122 printValue(HMI->first); cerr << "\n";
126 // if the Value * is not null, and LR
127 // is not yet written to the IGNodeList
128 if( !(L->getUserIGNode()) ) {
129 RegClass *const RC = // RegClass of first value in the LR
130 RegClassList[ L->getRegClass()->getID() ];
132 RC->addLRToIG(L); // add this LR to an IG
138 for( unsigned int rc=0; rc < NumOfRegClasses ; rc++)
139 RegClassList[rc]->createInterferenceGraph();
142 cerr << "LRLists Created!\n";
148 //----------------------------------------------------------------------------
149 // This method will add all interferences at for a given instruction.
150 // Interence occurs only if the LR of Def (Inst or Arg) is of the same reg
151 // class as that of live var. The live var passed to this function is the
152 // LVset AFTER the instruction
153 //----------------------------------------------------------------------------
154 void PhyRegAlloc::addInterference(const Value *const Def,
155 const LiveVarSet *const LVSet,
156 const bool isCallInst) {
158 LiveVarSet::const_iterator LIt = LVSet->begin();
160 // get the live range of instruction
162 const LiveRange *const LROfDef = LRI.getLiveRangeForValue( Def );
164 IGNode *const IGNodeOfDef = LROfDef->getUserIGNode();
165 assert( IGNodeOfDef );
167 RegClass *const RCOfDef = LROfDef->getRegClass();
169 // for each live var in live variable set
171 for( ; LIt != LVSet->end(); ++LIt) {
174 cerr << "< Def="; printValue(Def);
175 cerr << ", Lvar="; printValue( *LIt); cerr << "> ";
178 // get the live range corresponding to live var
180 LiveRange *const LROfVar = LRI.getLiveRangeForValue(*LIt );
182 // LROfVar can be null if it is a const since a const
183 // doesn't have a dominating def - see Assumptions above
186 if(LROfDef == LROfVar) // do not set interf for same LR
189 // if 2 reg classes are the same set interference
191 if(RCOfDef == LROfVar->getRegClass()) {
192 RCOfDef->setInterference( LROfDef, LROfVar);
193 } else if(DEBUG_RA > 1) {
194 // we will not have LRs for values not explicitly allocated in the
195 // instruction stream (e.g., constants)
196 cerr << " warning: no live range for " ;
197 printValue(*LIt); cerr << "\n";
205 //----------------------------------------------------------------------------
206 // For a call instruction, this method sets the CallInterference flag in
207 // the LR of each variable live int the Live Variable Set live after the
208 // call instruction (except the return value of the call instruction - since
209 // the return value does not interfere with that call itself).
210 //----------------------------------------------------------------------------
212 void PhyRegAlloc::setCallInterferences(const MachineInstr *MInst,
213 const LiveVarSet *const LVSetAft ) {
215 // Now find the LR of the return value of the call
216 // We do this because, we look at the LV set *after* the instruction
217 // to determine, which LRs must be saved across calls. The return value
218 // of the call is live in this set - but it does not interfere with call
219 // (i.e., we can allocate a volatile register to the return value)
221 LiveRange *RetValLR = NULL;
222 const Value *RetVal = MRI.getCallInstRetVal( MInst );
225 RetValLR = LRI.getLiveRangeForValue( RetVal );
226 assert( RetValLR && "No LR for RetValue of call");
230 cerr << "\n For call inst: " << *MInst;
232 LiveVarSet::const_iterator LIt = LVSetAft->begin();
234 // for each live var in live variable set after machine inst
236 for( ; LIt != LVSetAft->end(); ++LIt) {
238 // get the live range corresponding to live var
240 LiveRange *const LR = LRI.getLiveRangeForValue(*LIt );
242 if( LR && DEBUG_RA) {
243 cerr << "\n\tLR Aft Call: ";
248 // LR can be null if it is a const since a const
249 // doesn't have a dominating def - see Assumptions above
251 if( LR && (LR != RetValLR) ) {
252 LR->setCallInterference();
254 cerr << "\n ++Added call interf for LR: " ;
266 //----------------------------------------------------------------------------
267 // This method will walk thru code and create interferences in the IG of
268 // each RegClass. Also, this method calculates the spill cost of each
269 // Live Range (it is done in this method to save another pass over the code).
270 //----------------------------------------------------------------------------
271 void PhyRegAlloc::buildInterferenceGraphs()
274 if(DEBUG_RA) cerr << "Creating interference graphs ...\n";
276 unsigned BBLoopDepthCost;
277 Method::const_iterator BBI = Meth->begin(); // random iterator for BBs
279 for( ; BBI != Meth->end(); ++BBI) { // traverse BBs in random order
281 // find the 10^(loop_depth) of this BB
283 BBLoopDepthCost = (unsigned) pow( 10.0, LoopDepthCalc->getLoopDepth(*BBI));
285 // get the iterator for machine instructions
287 const MachineCodeForBasicBlock& MIVec = (*BBI)->getMachineInstrVec();
288 MachineCodeForBasicBlock::const_iterator
289 MInstIterator = MIVec.begin();
291 // iterate over all the machine instructions in BB
293 for( ; MInstIterator != MIVec.end(); ++MInstIterator) {
295 const MachineInstr * MInst = *MInstIterator;
297 // get the LV set after the instruction
299 const LiveVarSet *const LVSetAI =
300 LVI->getLiveVarSetAfterMInst(MInst, *BBI);
302 const bool isCallInst = TM.getInstrInfo().isCall(MInst->getOpCode());
305 // set the isCallInterference flag of each live range wich extends
306 // accross this call instruction. This information is used by graph
307 // coloring algo to avoid allocating volatile colors to live ranges
308 // that span across calls (since they have to be saved/restored)
310 setCallInterferences( MInst, LVSetAI);
314 // iterate over all MI operands to find defs
316 for( MachineInstr::val_const_op_iterator OpI(MInst);!OpI.done(); ++OpI) {
319 // create a new LR iff this operand is a def
321 addInterference(*OpI, LVSetAI, isCallInst );
324 // Calculate the spill cost of each live range
326 LiveRange *LR = LRI.getLiveRangeForValue( *OpI );
328 LR->addSpillCost(BBLoopDepthCost);
332 // if there are multiple defs in this instruction e.g. in SETX
334 if (TM.getInstrInfo().isPseudoInstr(MInst->getOpCode()))
335 addInterf4PseudoInstr(MInst);
338 // Also add interference for any implicit definitions in a machine
339 // instr (currently, only calls have this).
341 unsigned NumOfImpRefs = MInst->getNumImplicitRefs();
342 if( NumOfImpRefs > 0 ) {
343 for(unsigned z=0; z < NumOfImpRefs; z++)
344 if( MInst->implicitRefIsDefined(z) )
345 addInterference( MInst->getImplicitRef(z), LVSetAI, isCallInst );
349 } // for all machine instructions in BB
351 } // for all BBs in method
354 // add interferences for method arguments. Since there are no explict
355 // defs in method for args, we have to add them manually
357 addInterferencesForArgs();
360 cerr << "Interference graphs calculted!\n";
366 //--------------------------------------------------------------------------
367 // Pseudo instructions will be exapnded to multiple instructions by the
368 // assembler. Consequently, all the opernds must get distinct registers.
369 // Therefore, we mark all operands of a pseudo instruction as they interfere
371 //--------------------------------------------------------------------------
372 void PhyRegAlloc::addInterf4PseudoInstr(const MachineInstr *MInst) {
374 bool setInterf = false;
376 // iterate over MI operands to find defs
378 for( MachineInstr::val_const_op_iterator It1(MInst);!It1.done(); ++It1) {
380 const LiveRange *const LROfOp1 = LRI.getLiveRangeForValue( *It1 );
382 if( !LROfOp1 && It1.isDef() )
383 assert( 0 && "No LR for Def in PSEUDO insruction");
385 MachineInstr::val_const_op_iterator It2 = It1;
388 for( ; !It2.done(); ++It2) {
390 const LiveRange *const LROfOp2 = LRI.getLiveRangeForValue( *It2 );
394 RegClass *const RCOfOp1 = LROfOp1->getRegClass();
395 RegClass *const RCOfOp2 = LROfOp2->getRegClass();
397 if( RCOfOp1 == RCOfOp2 ){
398 RCOfOp1->setInterference( LROfOp1, LROfOp2 );
404 } // for all other defs in machine instr
406 } // for all operands in an instruction
408 if( !setInterf && (MInst->getNumOperands() > 2) ) {
409 cerr << "\nInterf not set for any operand in pseudo instr:\n";
411 assert(0 && "Interf not set for pseudo instr with > 2 operands" );
419 //----------------------------------------------------------------------------
420 // This method will add interferences for incoming arguments to a method.
421 //----------------------------------------------------------------------------
422 void PhyRegAlloc::addInterferencesForArgs()
424 // get the InSet of root BB
425 const LiveVarSet *const InSet = LVI->getInSetOfBB( Meth->front() );
427 // get the argument list
428 const Method::ArgumentListType& ArgList = Meth->getArgumentList();
430 // get an iterator to arg list
431 Method::ArgumentListType::const_iterator ArgIt = ArgList.begin();
434 for( ; ArgIt != ArgList.end() ; ++ArgIt) { // for each argument
435 addInterference((Value*)*ArgIt, InSet, false); // add interferences between
436 // args and LVars at start
438 cerr << " - %% adding interference for argument ";
439 printValue((const Value *)*ArgIt); cerr << "\n";
447 //----------------------------------------------------------------------------
448 // This method is called after register allocation is complete to set the
449 // allocated reisters in the machine code. This code will add register numbers
450 // to MachineOperands that contain a Value. Also it calls target specific
451 // methods to produce caller saving instructions. At the end, it adds all
452 // additional instructions produced by the register allocator to the
453 // instruction stream.
454 //----------------------------------------------------------------------------
455 void PhyRegAlloc::updateMachineCode()
458 Method::const_iterator BBI = Meth->begin(); // random iterator for BBs
460 for( ; BBI != Meth->end(); ++BBI) { // traverse BBs in random order
462 // get the iterator for machine instructions
464 MachineCodeForBasicBlock& MIVec = (*BBI)->getMachineInstrVec();
465 MachineCodeForBasicBlock::iterator MInstIterator = MIVec.begin();
467 // iterate over all the machine instructions in BB
469 for( ; MInstIterator != MIVec.end(); ++MInstIterator) {
471 MachineInstr *MInst = *MInstIterator;
473 unsigned Opcode = MInst->getOpCode();
475 // do not process Phis
476 if (TM.getInstrInfo().isPhi(Opcode))
479 // Now insert speical instructions (if necessary) for call/return
482 if (TM.getInstrInfo().isCall(Opcode) ||
483 TM.getInstrInfo().isReturn(Opcode)) {
485 AddedInstrns *AI = AddedInstrMap[ MInst];
487 AI = new AddedInstrns();
488 AddedInstrMap[ MInst ] = AI;
491 // Tmp stack poistions are needed by some calls that have spilled args
492 // So reset it before we call each such method
494 mcInfo.popAllTempValues(TM);
496 if (TM.getInstrInfo().isCall(Opcode))
497 MRI.colorCallArgs(MInst, LRI, AI, *this, *BBI);
498 else if (TM.getInstrInfo().isReturn(Opcode))
499 MRI.colorRetValue(MInst, LRI, AI);
503 /* -- Using above code instead of this
505 // if this machine instr is call, insert caller saving code
507 if( (TM.getInstrInfo()).isCall( MInst->getOpCode()) )
508 MRI.insertCallerSavingCode(MInst, *BBI, *this );
513 // reset the stack offset for temporary variables since we may
514 // need that to spill
515 // mcInfo.popAllTempValues(TM);
516 // TODO ** : do later
518 //for(MachineInstr::val_const_op_iterator OpI(MInst);!OpI.done();++OpI) {
521 // Now replace set the registers for operands in the machine instruction
523 for(unsigned OpNum=0; OpNum < MInst->getNumOperands(); ++OpNum) {
525 MachineOperand& Op = MInst->getOperand(OpNum);
527 if( Op.getOperandType() == MachineOperand::MO_VirtualRegister ||
528 Op.getOperandType() == MachineOperand::MO_CCRegister) {
530 const Value *const Val = Op.getVRegValue();
532 // delete this condition checking later (must assert if Val is null)
535 cerr << "Warning: NULL Value found for operand\n";
538 assert( Val && "Value is NULL");
540 LiveRange *const LR = LRI.getLiveRangeForValue(Val);
544 // nothing to worry if it's a const or a label
547 cerr << "*NO LR for operand : " << Op ;
548 cerr << " [reg:" << Op.getAllocatedRegNum() << "]";
549 cerr << " in inst:\t" << *MInst << "\n";
552 // if register is not allocated, mark register as invalid
553 if( Op.getAllocatedRegNum() == -1)
554 Op.setRegForValue( MRI.getInvalidRegNum());
560 unsigned RCID = (LR->getRegClass())->getID();
562 if( LR->hasColor() ) {
563 Op.setRegForValue( MRI.getUnifiedRegNum(RCID, LR->getColor()) );
567 // LR did NOT receive a color (register). Now, insert spill code
568 // for spilled opeands in this machine instruction
570 //assert(0 && "LR must be spilled");
571 insertCode4SpilledLR(LR, MInst, *BBI, OpNum );
576 } // for each operand
579 // Now add instructions that the register allocator inserts before/after
580 // this machine instructions (done only for calls/rets/incoming args)
581 // We do this here, to ensure that spill for an instruction is inserted
582 // closest as possible to an instruction (see above insertCode4Spill...)
584 // If there are instructions to be added, *before* this machine
585 // instruction, add them now.
587 if( AddedInstrMap[ MInst ] ) {
588 std::deque<MachineInstr *> &IBef = AddedInstrMap[MInst]->InstrnsBefore;
590 if( ! IBef.empty() ) {
591 std::deque<MachineInstr *>::iterator AdIt;
593 for( AdIt = IBef.begin(); AdIt != IBef.end() ; ++AdIt ) {
596 cerr << "For inst " << *MInst;
597 cerr << " PREPENDed instr: " << **AdIt << "\n";
600 MInstIterator = MIVec.insert( MInstIterator, *AdIt );
608 // If there are instructions to be added *after* this machine
609 // instruction, add them now
611 if(AddedInstrMap[MInst] &&
612 !AddedInstrMap[MInst]->InstrnsAfter.empty() ) {
614 // if there are delay slots for this instruction, the instructions
615 // added after it must really go after the delayed instruction(s)
616 // So, we move the InstrAfter of the current instruction to the
617 // corresponding delayed instruction
620 if ((delay=TM.getInstrInfo().getNumDelaySlots(MInst->getOpCode())) >0){
621 move2DelayedInstr(MInst, *(MInstIterator+delay) );
623 if(DEBUG_RA) cerr<< "\nMoved an added instr after the delay slot";
629 // Here we can add the "instructions after" to the current
630 // instruction since there are no delay slots for this instruction
632 std::deque<MachineInstr *> &IAft = AddedInstrMap[MInst]->InstrnsAfter;
634 if( ! IAft.empty() ) {
636 std::deque<MachineInstr *>::iterator AdIt;
638 ++MInstIterator; // advance to the next instruction
640 for( AdIt = IAft.begin(); AdIt != IAft.end() ; ++AdIt ) {
643 cerr << "For inst " << *MInst;
644 cerr << " APPENDed instr: " << **AdIt << "\n";
647 MInstIterator = MIVec.insert( MInstIterator, *AdIt );
651 // MInsterator already points to the next instr. Since the
652 // for loop also increments it, decrement it to point to the
653 // instruction added last
662 } // for each machine instruction
668 //----------------------------------------------------------------------------
669 // This method inserts spill code for AN operand whose LR was spilled.
670 // This method may be called several times for a single machine instruction
671 // if it contains many spilled operands. Each time it is called, it finds
672 // a register which is not live at that instruction and also which is not
673 // used by other spilled operands of the same instruction. Then it uses
674 // this register temporarily to accomodate the spilled value.
675 //----------------------------------------------------------------------------
676 void PhyRegAlloc::insertCode4SpilledLR(const LiveRange *LR,
678 const BasicBlock *BB,
679 const unsigned OpNum) {
681 assert(! TM.getInstrInfo().isCall(MInst->getOpCode()) &&
682 (! TM.getInstrInfo().isReturn(MInst->getOpCode())) &&
683 "Arg of a call/ret must be handled elsewhere");
685 MachineOperand& Op = MInst->getOperand(OpNum);
686 bool isDef = MInst->operandIsDefined(OpNum);
687 unsigned RegType = MRI.getRegType( LR );
688 int SpillOff = LR->getSpillOffFromFP();
689 RegClass *RC = LR->getRegClass();
690 const LiveVarSet *LVSetBef = LVI->getLiveVarSetBeforeMInst(MInst, BB);
692 mcInfo.pushTempValue(TM, MRI.getSpilledRegSize(RegType) );
694 MachineInstr *MIBef=NULL, *AdIMid=NULL, *MIAft=NULL;
696 int TmpRegU = getUsableUniRegAtMI(RC, RegType, MInst,LVSetBef, MIBef, MIAft);
698 // get the added instructions for this instruciton
699 AddedInstrns *AI = AddedInstrMap[ MInst ];
701 AI = new AddedInstrns();
702 AddedInstrMap[ MInst ] = AI;
708 // for a USE, we have to load the value of LR from stack to a TmpReg
709 // and use the TmpReg as one operand of instruction
711 // actual loading instruction
712 AdIMid = MRI.cpMem2RegMI(MRI.getFramePointer(), SpillOff, TmpRegU,RegType);
715 AI->InstrnsBefore.push_back(MIBef);
717 AI->InstrnsBefore.push_back(AdIMid);
720 AI->InstrnsAfter.push_front(MIAft);
724 else { // if this is a Def
726 // for a DEF, we have to store the value produced by this instruction
727 // on the stack position allocated for this LR
729 // actual storing instruction
730 AdIMid = MRI.cpReg2MemMI(TmpRegU, MRI.getFramePointer(), SpillOff,RegType);
733 AI->InstrnsBefore.push_back(MIBef);
735 AI->InstrnsAfter.push_front(AdIMid);
738 AI->InstrnsAfter.push_front(MIAft);
742 cerr << "\nFor Inst " << *MInst;
743 cerr << " - SPILLED LR: "; LR->printSet();
744 cerr << "\n - Added Instructions:";
745 if( MIBef ) cerr << *MIBef;
747 if( MIAft ) cerr << *MIAft;
749 Op.setRegForValue( TmpRegU ); // set the opearnd
759 //----------------------------------------------------------------------------
760 // We can use the following method to get a temporary register to be used
761 // BEFORE any given machine instruction. If there is a register available,
762 // this method will simply return that register and set MIBef = MIAft = NULL.
763 // Otherwise, it will return a register and MIAft and MIBef will contain
764 // two instructions used to free up this returned register.
765 // Returned register number is the UNIFIED register number
766 //----------------------------------------------------------------------------
768 int PhyRegAlloc::getUsableUniRegAtMI(RegClass *RC,
770 const MachineInstr *MInst,
771 const LiveVarSet *LVSetBef,
773 MachineInstr *MIAft) {
775 int RegU = getUnusedUniRegAtMI(RC, MInst, LVSetBef);
779 // we found an unused register, so we can simply use it
780 MIBef = MIAft = NULL;
783 // we couldn't find an unused register. Generate code to free up a reg by
784 // saving it on stack and restoring after the instruction
786 int TmpOff = mcInfo.pushTempValue(TM, MRI.getSpilledRegSize(RegType) );
788 RegU = getUniRegNotUsedByThisInst(RC, MInst);
789 MIBef = MRI.cpReg2MemMI(RegU, MRI.getFramePointer(), TmpOff, RegType );
790 MIAft = MRI.cpMem2RegMI(MRI.getFramePointer(), TmpOff, RegU, RegType );
796 //----------------------------------------------------------------------------
797 // This method is called to get a new unused register that can be used to
798 // accomodate a spilled value.
799 // This method may be called several times for a single machine instruction
800 // if it contains many spilled operands. Each time it is called, it finds
801 // a register which is not live at that instruction and also which is not
802 // used by other spilled operands of the same instruction.
803 // Return register number is relative to the register class. NOT
805 //----------------------------------------------------------------------------
806 int PhyRegAlloc::getUnusedUniRegAtMI(RegClass *RC,
807 const MachineInstr *MInst,
808 const LiveVarSet *LVSetBef) {
810 unsigned NumAvailRegs = RC->getNumOfAvailRegs();
812 bool *IsColorUsedArr = RC->getIsColorUsedArr();
814 for(unsigned i=0; i < NumAvailRegs; i++) // Reset array
815 IsColorUsedArr[i] = false;
817 LiveVarSet::const_iterator LIt = LVSetBef->begin();
819 // for each live var in live variable set after machine inst
820 for( ; LIt != LVSetBef->end(); ++LIt) {
822 // get the live range corresponding to live var
823 LiveRange *const LRofLV = LRI.getLiveRangeForValue(*LIt );
825 // LR can be null if it is a const since a const
826 // doesn't have a dominating def - see Assumptions above
828 if( LRofLV->hasColor() )
829 IsColorUsedArr[ LRofLV->getColor() ] = true;
832 // It is possible that one operand of this MInst was already spilled
833 // and it received some register temporarily. If that's the case,
834 // it is recorded in machine operand. We must skip such registers.
836 setRelRegsUsedByThisInst(RC, MInst);
838 unsigned c; // find first unused color
839 for( c=0; c < NumAvailRegs; c++)
840 if( ! IsColorUsedArr[ c ] ) break;
843 return MRI.getUnifiedRegNum(RC->getID(), c);
851 //----------------------------------------------------------------------------
852 // Get any other register in a register class, other than what is used
853 // by operands of a machine instruction. Returns the unified reg number.
854 //----------------------------------------------------------------------------
855 int PhyRegAlloc::getUniRegNotUsedByThisInst(RegClass *RC,
856 const MachineInstr *MInst) {
858 bool *IsColorUsedArr = RC->getIsColorUsedArr();
859 unsigned NumAvailRegs = RC->getNumOfAvailRegs();
862 for(unsigned i=0; i < NumAvailRegs ; i++) // Reset array
863 IsColorUsedArr[i] = false;
865 setRelRegsUsedByThisInst(RC, MInst);
867 unsigned c; // find first unused color
868 for( c=0; c < RC->getNumOfAvailRegs(); c++)
869 if( ! IsColorUsedArr[ c ] ) break;
872 return MRI.getUnifiedRegNum(RC->getID(), c);
874 assert( 0 && "FATAL: No free register could be found in reg class!!");
879 //----------------------------------------------------------------------------
880 // This method modifies the IsColorUsedArr of the register class passed to it.
881 // It sets the bits corresponding to the registers used by this machine
882 // instructions. Both explicit and implicit operands are set.
883 //----------------------------------------------------------------------------
884 void PhyRegAlloc::setRelRegsUsedByThisInst(RegClass *RC,
885 const MachineInstr *MInst ) {
887 bool *IsColorUsedArr = RC->getIsColorUsedArr();
889 for(unsigned OpNum=0; OpNum < MInst->getNumOperands(); ++OpNum) {
891 const MachineOperand& Op = MInst->getOperand(OpNum);
893 if( Op.getOperandType() == MachineOperand::MO_VirtualRegister ||
894 Op.getOperandType() == MachineOperand::MO_CCRegister ) {
896 const Value *const Val = Op.getVRegValue();
899 if( MRI.getRegClassIDOfValue(Val) == RC->getID() ) {
901 if( (Reg=Op.getAllocatedRegNum()) != -1) {
902 IsColorUsedArr[ Reg ] = true;
905 // it is possilbe that this operand still is not marked with
906 // a register but it has a LR and that received a color
908 LiveRange *LROfVal = LRI.getLiveRangeForValue(Val);
910 if( LROfVal->hasColor() )
911 IsColorUsedArr[ LROfVal->getColor() ] = true;
914 } // if reg classes are the same
916 else if (Op.getOperandType() == MachineOperand::MO_MachineRegister) {
917 IsColorUsedArr[ Op.getMachineRegNum() ] = true;
921 // If there are implicit references, mark them as well
923 for(unsigned z=0; z < MInst->getNumImplicitRefs(); z++) {
925 LiveRange *const LRofImpRef =
926 LRI.getLiveRangeForValue( MInst->getImplicitRef(z) );
928 if(LRofImpRef && LRofImpRef->hasColor())
929 IsColorUsedArr[LRofImpRef->getColor()] = true;
940 //----------------------------------------------------------------------------
941 // If there are delay slots for an instruction, the instructions
942 // added after it must really go after the delayed instruction(s).
943 // So, we move the InstrAfter of that instruction to the
944 // corresponding delayed instruction using the following method.
946 //----------------------------------------------------------------------------
947 void PhyRegAlloc:: move2DelayedInstr(const MachineInstr *OrigMI,
948 const MachineInstr *DelayedMI) {
950 // "added after" instructions of the original instr
951 std::deque<MachineInstr *> &OrigAft = AddedInstrMap[OrigMI]->InstrnsAfter;
953 // "added instructions" of the delayed instr
954 AddedInstrns *DelayAdI = AddedInstrMap[DelayedMI];
956 if(! DelayAdI ) { // create a new "added after" if necessary
957 DelayAdI = new AddedInstrns();
958 AddedInstrMap[DelayedMI] = DelayAdI;
961 // "added after" instructions of the delayed instr
962 std::deque<MachineInstr *> &DelayedAft = DelayAdI->InstrnsAfter;
964 // go thru all the "added after instructions" of the original instruction
965 // and append them to the "addded after instructions" of the delayed
967 DelayedAft.insert(DelayedAft.end(), OrigAft.begin(), OrigAft.end());
969 // empty the "added after instructions" of the original instruction
973 //----------------------------------------------------------------------------
974 // This method prints the code with registers after register allocation is
976 //----------------------------------------------------------------------------
977 void PhyRegAlloc::printMachineCode()
980 cerr << "\n;************** Method " << Meth->getName()
981 << " *****************\n";
983 Method::const_iterator BBI = Meth->begin(); // random iterator for BBs
985 for( ; BBI != Meth->end(); ++BBI) { // traverse BBs in random order
987 cerr << "\n"; printLabel( *BBI); cerr << ": ";
989 // get the iterator for machine instructions
990 MachineCodeForBasicBlock& MIVec = (*BBI)->getMachineInstrVec();
991 MachineCodeForBasicBlock::iterator MInstIterator = MIVec.begin();
993 // iterate over all the machine instructions in BB
994 for( ; MInstIterator != MIVec.end(); ++MInstIterator) {
996 MachineInstr *const MInst = *MInstIterator;
1000 cerr << TargetInstrDescriptors[MInst->getOpCode()].opCodeString;
1003 //for(MachineInstr::val_const_op_iterator OpI(MInst);!OpI.done();++OpI) {
1005 for(unsigned OpNum=0; OpNum < MInst->getNumOperands(); ++OpNum) {
1007 MachineOperand& Op = MInst->getOperand(OpNum);
1009 if( Op.getOperandType() == MachineOperand::MO_VirtualRegister ||
1010 Op.getOperandType() == MachineOperand::MO_CCRegister /*||
1011 Op.getOperandType() == MachineOperand::MO_PCRelativeDisp*/ ) {
1013 const Value *const Val = Op.getVRegValue () ;
1014 // ****this code is temporary till NULL Values are fixed
1016 cerr << "\t<*NULL*>";
1020 // if a label or a constant
1021 if(isa<BasicBlock>(Val)) {
1022 cerr << "\t"; printLabel( Op.getVRegValue () );
1024 // else it must be a register value
1025 const int RegNum = Op.getAllocatedRegNum();
1027 cerr << "\t" << "%" << MRI.getUnifiedRegName( RegNum );
1028 if (Val->hasName() )
1029 cerr << "(" << Val->getName() << ")";
1031 cerr << "(" << Val << ")";
1036 const LiveRange *LROfVal = LRI.getLiveRangeForValue(Val);
1038 if( LROfVal->hasSpillOffset() )
1043 else if(Op.getOperandType() == MachineOperand::MO_MachineRegister) {
1044 cerr << "\t" << "%" << MRI.getUnifiedRegName(Op.getMachineRegNum());
1048 cerr << "\t" << Op; // use dump field
1053 unsigned NumOfImpRefs = MInst->getNumImplicitRefs();
1054 if( NumOfImpRefs > 0 ) {
1056 cerr << "\tImplicit:";
1058 for(unsigned z=0; z < NumOfImpRefs; z++) {
1059 printValue( MInst->getImplicitRef(z) );
1065 } // for all machine instructions
1077 //----------------------------------------------------------------------------
1079 //----------------------------------------------------------------------------
1081 void PhyRegAlloc::colorCallRetArgs()
1084 CallRetInstrListType &CallRetInstList = LRI.getCallRetInstrList();
1085 CallRetInstrListType::const_iterator It = CallRetInstList.begin();
1087 for( ; It != CallRetInstList.end(); ++It ) {
1089 const MachineInstr *const CRMI = *It;
1090 unsigned OpCode = CRMI->getOpCode();
1092 // get the added instructions for this Call/Ret instruciton
1093 AddedInstrns *AI = AddedInstrMap[ CRMI ];
1095 AI = new AddedInstrns();
1096 AddedInstrMap[ CRMI ] = AI;
1099 // Tmp stack poistions are needed by some calls that have spilled args
1100 // So reset it before we call each such method
1101 //mcInfo.popAllTempValues(TM);
1105 if (TM.getInstrInfo().isCall(OpCode))
1106 MRI.colorCallArgs(CRMI, LRI, AI, *this);
1107 else if (TM.getInstrInfo().isReturn(OpCode))
1108 MRI.colorRetValue( CRMI, LRI, AI );
1110 assert(0 && "Non Call/Ret instrn in CallRetInstrList\n");
1116 //----------------------------------------------------------------------------
1118 //----------------------------------------------------------------------------
1119 void PhyRegAlloc::colorIncomingArgs()
1121 const BasicBlock *const FirstBB = Meth->front();
1122 const MachineInstr *FirstMI = FirstBB->getMachineInstrVec().front();
1123 assert(FirstMI && "No machine instruction in entry BB");
1125 AddedInstrns *AI = AddedInstrMap[FirstMI];
1127 AddedInstrMap[FirstMI] = AI = new AddedInstrns();
1129 MRI.colorMethodArgs(Meth, LRI, AI);
1133 //----------------------------------------------------------------------------
1134 // Used to generate a label for a basic block
1135 //----------------------------------------------------------------------------
1136 void PhyRegAlloc::printLabel(const Value *const Val) {
1138 cerr << Val->getName();
1140 cerr << "Label" << Val;
1144 //----------------------------------------------------------------------------
1145 // This method calls setSugColorUsable method of each live range. This
1146 // will determine whether the suggested color of LR is really usable.
1147 // A suggested color is not usable when the suggested color is volatile
1148 // AND when there are call interferences
1149 //----------------------------------------------------------------------------
1151 void PhyRegAlloc::markUnusableSugColors()
1153 if(DEBUG_RA ) cerr << "\nmarking unusable suggested colors ...\n";
1155 // hash map iterator
1156 LiveRangeMapType::const_iterator HMI = (LRI.getLiveRangeMap())->begin();
1157 LiveRangeMapType::const_iterator HMIEnd = (LRI.getLiveRangeMap())->end();
1159 for(; HMI != HMIEnd ; ++HMI ) {
1161 LiveRange *L = HMI->second; // get the LiveRange
1163 if(L->hasSuggestedColor()) {
1164 int RCID = L->getRegClass()->getID();
1165 if( MRI.isRegVolatile( RCID, L->getSuggestedColor()) &&
1166 L->isCallInterference() )
1167 L->setSuggestedColorUsable( false );
1169 L->setSuggestedColorUsable( true );
1171 } // if L->hasSuggestedColor()
1173 } // for all LR's in hash map
1178 //----------------------------------------------------------------------------
1179 // The following method will set the stack offsets of the live ranges that
1180 // are decided to be spillled. This must be called just after coloring the
1181 // LRs using the graph coloring algo. For each live range that is spilled,
1182 // this method allocate a new spill position on the stack.
1183 //----------------------------------------------------------------------------
1185 void PhyRegAlloc::allocateStackSpace4SpilledLRs()
1187 if(DEBUG_RA ) cerr << "\nsetting LR stack offsets ...\n";
1189 // hash map iterator
1190 LiveRangeMapType::const_iterator HMI = (LRI.getLiveRangeMap())->begin();
1191 LiveRangeMapType::const_iterator HMIEnd = (LRI.getLiveRangeMap())->end();
1193 for( ; HMI != HMIEnd ; ++HMI ) {
1194 if(HMI->first && HMI->second) {
1195 LiveRange *L = HMI->second; // get the LiveRange
1196 if( ! L->hasColor() )
1197 // NOTE: ** allocating the size of long Type **
1198 L->setSpillOffFromFP(mcInfo.allocateSpilledValue(TM, Type::LongTy));
1200 } // for all LR's in hash map
1205 //----------------------------------------------------------------------------
1206 // The entry pont to Register Allocation
1207 //----------------------------------------------------------------------------
1209 void PhyRegAlloc::allocateRegisters()
1212 // make sure that we put all register classes into the RegClassList
1213 // before we call constructLiveRanges (now done in the constructor of
1214 // PhyRegAlloc class).
1216 LRI.constructLiveRanges(); // create LR info
1219 LRI.printLiveRanges();
1221 createIGNodeListsAndIGs(); // create IGNode list and IGs
1223 buildInterferenceGraphs(); // build IGs in all reg classes
1227 // print all LRs in all reg classes
1228 for( unsigned int rc=0; rc < NumOfRegClasses ; rc++)
1229 RegClassList[ rc ]->printIGNodeList();
1231 // print IGs in all register classes
1232 for( unsigned int rc=0; rc < NumOfRegClasses ; rc++)
1233 RegClassList[ rc ]->printIG();
1237 LRI.coalesceLRs(); // coalesce all live ranges
1241 // print all LRs in all reg classes
1242 for( unsigned int rc=0; rc < NumOfRegClasses ; rc++)
1243 RegClassList[ rc ]->printIGNodeList();
1245 // print IGs in all register classes
1246 for( unsigned int rc=0; rc < NumOfRegClasses ; rc++)
1247 RegClassList[ rc ]->printIG();
1251 // mark un-usable suggested color before graph coloring algorithm.
1252 // When this is done, the graph coloring algo will not reserve
1253 // suggested color unnecessarily - they can be used by another LR
1255 markUnusableSugColors();
1257 // color all register classes using the graph coloring algo
1258 for( unsigned int rc=0; rc < NumOfRegClasses ; rc++)
1259 RegClassList[ rc ]->colorAllRegs();
1261 // Atter grpah coloring, if some LRs did not receive a color (i.e, spilled)
1262 // a poistion for such spilled LRs
1264 allocateStackSpace4SpilledLRs();
1266 mcInfo.popAllTempValues(TM); // TODO **Check
1268 // color incoming args - if the correct color was not received
1269 // insert code to copy to the correct register
1271 colorIncomingArgs();
1273 // Now update the machine code with register names and add any
1274 // additional code inserted by the register allocator to the instruction
1277 updateMachineCode();
1280 MachineCodeForMethod::get(Meth).dump();
1281 printMachineCode(); // only for DEBUGGING