1 #include "llvm/CodeGen/PhyRegAlloc.h"
3 cl::Enum<RegAllocDebugLevel_t> DEBUG_RA("dregalloc", cl::NoFlags,
4 "enable register allocation debugging information",
5 clEnumValN(RA_DEBUG_None , "n", "disable debug output"),
6 clEnumValN(RA_DEBUG_Normal , "y", "enable debug output"),
7 clEnumValN(RA_DEBUG_Verbose, "v", "enable extra debug output"), 0);
10 //----------------------------------------------------------------------------
11 // Constructor: Init local composite objects and create register classes.
12 //----------------------------------------------------------------------------
13 PhyRegAlloc::PhyRegAlloc(const Method *const M,
14 const TargetMachine& tm,
15 MethodLiveVarInfo *const Lvi)
17 Meth(M), TM(tm), LVI(Lvi), LRI(M, tm, RegClassList),
18 MRI( tm.getRegInfo() ),
19 NumOfRegClasses(MRI.getNumOfRegClasses()),
23 // **TODO: use an actual reserved color list
24 ReservedColorListType *RCL = new ReservedColorListType();
26 // create each RegisterClass and put in RegClassList
27 for( unsigned int rc=0; rc < NumOfRegClasses; rc++)
28 RegClassList.push_back( new RegClass(M, MRI.getMachineRegClass(rc), RCL) );
32 //----------------------------------------------------------------------------
33 // This method initally creates interference graphs (one in each reg class)
34 // and IGNodeList (one in each IG). The actual nodes will be pushed later.
35 //----------------------------------------------------------------------------
37 void PhyRegAlloc::createIGNodeListsAndIGs()
39 if(DEBUG_RA ) cout << "Creating LR lists ..." << endl;
42 LiveRangeMapType::const_iterator HMI = (LRI.getLiveRangeMap())->begin();
45 LiveRangeMapType::const_iterator HMIEnd = (LRI.getLiveRangeMap())->end();
47 for( ; HMI != HMIEnd ; ++HMI ) {
51 LiveRange *L = (*HMI).second; // get the LiveRange
55 cout << "\n*?!?Warning: Null liver range found for: ";
56 printValue( (*HMI).first) ; cout << endl;
60 // if the Value * is not null, and LR
61 // is not yet written to the IGNodeList
62 if( !(L->getUserIGNode()) ) {
64 RegClass *const RC = // RegClass of first value in the LR
65 //RegClassList [MRI.getRegClassIDOfValue(*(L->begin()))];
66 RegClassList[ L->getRegClass()->getID() ];
68 RC-> addLRToIG( L ); // add this LR to an IG
74 for( unsigned int rc=0; rc < NumOfRegClasses ; rc++)
75 RegClassList[ rc ]->createInterferenceGraph();
78 cout << "LRLists Created!" << endl;
83 //----------------------------------------------------------------------------
84 // This method will add all interferences at for a given instruction.
85 // Interence occurs only if the LR of Def (Inst or Arg) is of the same reg
86 // class as that of live var. The live var passed to this function is the
87 // LVset AFTER the instruction
88 //----------------------------------------------------------------------------
90 void PhyRegAlloc::addInterference(const Value *const Def,
91 const LiveVarSet *const LVSet,
92 const bool isCallInst) {
94 LiveVarSet::const_iterator LIt = LVSet->begin();
96 // get the live range of instruction
97 const LiveRange *const LROfDef = LRI.getLiveRangeForValue( Def );
99 IGNode *const IGNodeOfDef = LROfDef->getUserIGNode();
100 assert( IGNodeOfDef );
102 RegClass *const RCOfDef = LROfDef->getRegClass();
104 // for each live var in live variable set
105 for( ; LIt != LVSet->end(); ++LIt) {
108 cout << "< Def="; printValue(Def);
109 cout << ", Lvar="; printValue( *LIt); cout << "> ";
112 // get the live range corresponding to live var
113 LiveRange *const LROfVar = LRI.getLiveRangeForValue(*LIt );
115 // LROfVar can be null if it is a const since a const
116 // doesn't have a dominating def - see Assumptions above
119 if(LROfDef == LROfVar) // do not set interf for same LR
122 // if 2 reg classes are the same set interference
123 if( RCOfDef == LROfVar->getRegClass() ){
124 RCOfDef->setInterference( LROfDef, LROfVar);
128 else if(DEBUG_RA > 1) {
129 // we will not have LRs for values not explicitly allocated in the
130 // instruction stream (e.g., constants)
131 cout << " warning: no live range for " ;
132 printValue( *LIt); cout << endl; }
141 //----------------------------------------------------------------------------
142 // For a call instruction, this method sets the CallInterference flag in
143 // the LR of each variable live int the Live Variable Set live after the
144 // call instruction (except the return value of the call instruction - since
145 // the return value does not interfere with that call itself).
146 //----------------------------------------------------------------------------
148 void PhyRegAlloc::setCallInterferences(const MachineInstr *MInst,
149 const LiveVarSet *const LVSetAft )
151 // Now find the LR of the return value of the call
152 // The last *implicit operand* is the return value of a call
154 // We do this because, we look at the LV set *after* the instruction
155 // to determine, which LRs must be saved across calls. The return value
156 // of the call is live in this set - but it does not interfere with call
157 // (i.e., we can allocate a volatile register to the return value)
159 LiveRange *RetValLR = NULL;
161 unsigned NumOfImpRefs = MInst->getNumImplicitRefs();
162 if( NumOfImpRefs > 0 ) {
164 if( MInst->implicitRefIsDefined(NumOfImpRefs-1) ) {
166 const Value *RetVal = MInst->getImplicitRef(NumOfImpRefs-1);
167 RetValLR = LRI.getLiveRangeForValue( RetVal );
168 assert( RetValLR && "No LR for RetValue of call");
175 cout << "\n For call inst: " << *MInst;
177 LiveVarSet::const_iterator LIt = LVSetAft->begin();
179 // for each live var in live variable set after machine inst
180 for( ; LIt != LVSetAft->end(); ++LIt) {
182 // get the live range corresponding to live var
183 LiveRange *const LR = LRI.getLiveRangeForValue(*LIt );
185 if( LR && DEBUG_RA) {
186 cout << "\n\tLR Aft Call: ";
191 // LR can be null if it is a const since a const
192 // doesn't have a dominating def - see Assumptions above
193 if( LR && (LR != RetValLR) ) {
194 LR->setCallInterference();
196 cout << "\n ++Added call interf for LR: " ;
206 //----------------------------------------------------------------------------
207 // This method will walk thru code and create interferences in the IG of
209 //----------------------------------------------------------------------------
211 void PhyRegAlloc::buildInterferenceGraphs()
214 if(DEBUG_RA) cout << "Creating interference graphs ..." << endl;
216 Method::const_iterator BBI = Meth->begin(); // random iterator for BBs
218 for( ; BBI != Meth->end(); ++BBI) { // traverse BBs in random order
220 // get the iterator for machine instructions
221 const MachineCodeForBasicBlock& MIVec = (*BBI)->getMachineInstrVec();
222 MachineCodeForBasicBlock::const_iterator
223 MInstIterator = MIVec.begin();
225 // iterate over all the machine instructions in BB
226 for( ; MInstIterator != MIVec.end(); ++MInstIterator) {
228 const MachineInstr *const MInst = *MInstIterator;
230 // get the LV set after the instruction
231 const LiveVarSet *const LVSetAI =
232 LVI->getLiveVarSetAfterMInst(MInst, *BBI);
234 const bool isCallInst = TM.getInstrInfo().isCall(MInst->getOpCode());
237 //cout << "\nFor call inst: " << *MInst;
239 // set the isCallInterference flag of each live range wich extends
240 // accross this call instruction. This information is used by graph
241 // coloring algo to avoid allocating volatile colors to live ranges
242 // that span across calls (since they have to be saved/restored)
243 setCallInterferences( MInst, LVSetAI);
247 // iterate over MI operands to find defs
248 for( MachineInstr::val_op_const_iterator OpI(MInst);!OpI.done(); ++OpI) {
251 // create a new LR iff this operand is a def
252 addInterference(*OpI, LVSetAI, isCallInst );
256 } // for all operands
259 // Also add interference for any implicit definitions in a machine
260 // instr (currently, only calls have this).
262 unsigned NumOfImpRefs = MInst->getNumImplicitRefs();
263 if( NumOfImpRefs > 0 ) {
264 for(unsigned z=0; z < NumOfImpRefs; z++)
265 if( MInst->implicitRefIsDefined(z) )
266 addInterference( MInst->getImplicitRef(z), LVSetAI, isCallInst );
269 } // for all machine instructions in BB
274 // go thru LLVM instructions in the basic block and record all CALL
275 // instructions and Return instructions in the CallInstrList
276 // This is done because since there are no reverse pointers in machine
277 // instructions to find the llvm instruction, when we encounter a call
278 // or a return whose args must be specailly colored (e.g., %o's for args)
279 BasicBlock::const_iterator InstIt = (*BBI)->begin();
281 for( ; InstIt != (*BBI)->end() ; ++ InstIt) {
282 unsigned OpCode = (*InstIt)->getOpcode();
284 if( OpCode == Instruction::Call )
285 CallInstrList.push_back( *InstIt );
287 else if( OpCode == Instruction::Ret )
288 RetInstrList.push_back( *InstIt );
294 } // for all BBs in method
297 // add interferences for method arguments. Since there are no explict
298 // defs in method for args, we have to add them manually
300 addInterferencesForArgs(); // add interference for method args
303 cout << "Interference graphs calculted!" << endl;
310 //----------------------------------------------------------------------------
311 // This method will add interferences for incoming arguments to a method.
312 //----------------------------------------------------------------------------
313 void PhyRegAlloc::addInterferencesForArgs()
315 // get the InSet of root BB
316 const LiveVarSet *const InSet = LVI->getInSetOfBB( Meth->front() );
318 // get the argument list
319 const Method::ArgumentListType& ArgList = Meth->getArgumentList();
321 // get an iterator to arg list
322 Method::ArgumentListType::const_iterator ArgIt = ArgList.begin();
325 for( ; ArgIt != ArgList.end() ; ++ArgIt) { // for each argument
326 addInterference( *ArgIt, InSet, false ); // add interferences between
327 // args and LVars at start
329 cout << " - %% adding interference for argument ";
330 printValue( (const Value *) *ArgIt); cout << endl;
337 //----------------------------------------------------------------------------
338 // This method inserts caller saving/restoring instructons before/after
339 // a call machine instruction.
340 //----------------------------------------------------------------------------
343 void PhyRegAlloc::insertCallerSavingCode(const MachineInstr *MInst,
344 const BasicBlock *BB )
346 // assert( (TM.getInstrInfo()).isCall( MInst->getOpCode() ) );
348 int StackOff = -8; // ****TODO : Change
349 hash_set<unsigned> PushedRegSet;
351 // Now find the LR of the return value of the call
352 // The last *implicit operand* is the return value of a call
353 // Insert it to to he PushedRegSet since we must not save that register
354 // and restore it after the call.
355 // We do this because, we look at the LV set *after* the instruction
356 // to determine, which LRs must be saved across calls. The return value
357 // of the call is live in this set - but we must not save/restore it.
359 unsigned NumOfImpRefs = MInst->getNumImplicitRefs();
360 if( NumOfImpRefs > 0 ) {
362 if( MInst->implicitRefIsDefined(NumOfImpRefs-1) ) {
364 const Value *RetVal = MInst->getImplicitRef(NumOfImpRefs-1);
365 LiveRange *RetValLR = LRI.getLiveRangeForValue( RetVal );
366 assert( RetValLR && "No LR for RetValue of call");
369 MRI.getUnifiedRegNum((RetValLR->getRegClass())->getID(),
370 RetValLR->getColor() ) );
376 const LiveVarSet *LVSetAft = LVI->getLiveVarSetAfterMInst(MInst, BB);
378 LiveVarSet::const_iterator LIt = LVSetAft->begin();
380 // for each live var in live variable set after machine inst
381 for( ; LIt != LVSetAft->end(); ++LIt) {
383 // get the live range corresponding to live var
384 LiveRange *const LR = LRI.getLiveRangeForValue(*LIt );
386 // LR can be null if it is a const since a const
387 // doesn't have a dominating def - see Assumptions above
390 if( LR->hasColor() ) {
392 unsigned RCID = (LR->getRegClass())->getID();
393 unsigned Color = LR->getColor();
395 if ( MRI.isRegVolatile(RCID, Color) ) {
397 // if the value is in both LV sets (i.e., live before and after
398 // the call machine instruction)
400 unsigned Reg = MRI.getUnifiedRegNum(RCID, Color);
402 if( PushedRegSet.find(Reg) == PushedRegSet.end() ) {
404 // if we haven't already pushed that register
406 unsigned RegType = MRI.getRegType( LR );
408 // Now get two instructions - to push on stack and pop from stack
409 // and add them to InstrnsBefore and InstrnsAfter of the
412 MachineInstr *AdIBef =
413 MRI.cpReg2MemMI(Reg, MRI.getFramePointer(), StackOff, RegType );
415 MachineInstr *AdIAft =
416 MRI.cpMem2RegMI(MRI.getFramePointer(), StackOff, Reg, RegType );
418 ((AddedInstrMap[MInst])->InstrnsBefore).push_front(AdIBef);
419 ((AddedInstrMap[MInst])->InstrnsAfter).push_back(AdIAft);
421 PushedRegSet.insert( Reg );
422 StackOff -= 8; // ****TODO: Correct ??????
425 cerr << "\nFor callee save call inst:" << *MInst;
426 cerr << "\n -inserted caller saving instrs:\n\t ";
427 cerr << *AdIBef << "\n\t" << *AdIAft ;
429 } // if not already pushed
431 } // if LR has a volatile color
435 } // if there is a LR for Var
437 } // for each value in the LV set after instruction
442 //----------------------------------------------------------------------------
443 // This method is called after register allocation is complete to set the
444 // allocated reisters in the machine code. This code will add register numbers
445 // to MachineOperands that contain a Value.
446 //----------------------------------------------------------------------------
448 void PhyRegAlloc::updateMachineCode()
451 Method::const_iterator BBI = Meth->begin(); // random iterator for BBs
453 for( ; BBI != Meth->end(); ++BBI) { // traverse BBs in random order
455 // get the iterator for machine instructions
456 MachineCodeForBasicBlock& MIVec = (*BBI)->getMachineInstrVec();
457 MachineCodeForBasicBlock::iterator MInstIterator = MIVec.begin();
459 // iterate over all the machine instructions in BB
460 for( ; MInstIterator != MIVec.end(); ++MInstIterator) {
462 MachineInstr *MInst = *MInstIterator;
464 // if this machine instr is call, insert caller saving code
466 if( (TM.getInstrInfo()).isCall( MInst->getOpCode()) )
467 insertCallerSavingCode(MInst, *BBI );
469 // If there are instructions to be added, *before* this machine
470 // instruction, add them now.
472 if( AddedInstrMap[ MInst ] ) {
474 deque<MachineInstr *> &IBef = (AddedInstrMap[MInst])->InstrnsBefore;
476 if( ! IBef.empty() ) {
478 deque<MachineInstr *>::iterator AdIt;
480 for( AdIt = IBef.begin(); AdIt != IBef.end() ; ++AdIt ) {
483 cerr << " *$* PREPENDed instr " << *AdIt << endl;
485 MInstIterator = MIVec.insert( MInstIterator, *AdIt );
495 //for(MachineInstr::val_op_const_iterator OpI(MInst);!OpI.done();++OpI) {
497 for(unsigned OpNum=0; OpNum < MInst->getNumOperands(); ++OpNum) {
499 MachineOperand& Op = MInst->getOperand(OpNum);
501 if( Op.getOperandType() == MachineOperand::MO_VirtualRegister ||
502 Op.getOperandType() == MachineOperand::MO_CCRegister) {
504 const Value *const Val = Op.getVRegValue();
506 // delete this condition checking later (must assert if Val is null)
509 cout << "Warning: NULL Value found for operand" << endl;
512 assert( Val && "Value is NULL");
514 const LiveRange *const LR = LRI.getLiveRangeForValue(Val);
518 // nothing to worry if it's a const or a label
521 cout << "*NO LR for operand : " << Op ;
522 cout << " [reg:" << Op.getAllocatedRegNum() << "]";
523 cout << " in inst:\t" << *MInst << endl;
526 // if register is not allocated, mark register as invalid
527 if( Op.getAllocatedRegNum() == -1)
528 Op.setRegForValue( MRI.getInvalidRegNum());
531 if( ((Val->getType())->isLabelType()) ||
532 (Val->getValueType() == Value::ConstantVal) )
535 // The return address is not explicitly defined within a
536 // method. So, it is not colored by usual algorithm. In that case
539 //else if (TM.getInstrInfo().isCall(MInst->getOpCode()))
540 //Op.setRegForValue( MRI.getCallAddressReg() );
542 //TM.getInstrInfo().isReturn(MInst->getOpCode())
543 else if(TM.getInstrInfo().isReturn(MInst->getOpCode()) ) {
544 if (DEBUG_RA) cout << endl << "RETURN found" << endl;
545 Op.setRegForValue( MRI.getReturnAddressReg() );
549 if (Val->getValueType() == Value::InstructionVal)
552 cout << "!Warning: No LiveRange for: ";
553 printValue( Val); cout << " Type: " << Val->getValueType();
554 cout << " RegVal=" << Op.getAllocatedRegNum() << endl;
563 unsigned RCID = (LR->getRegClass())->getID();
565 Op.setRegForValue( MRI.getUnifiedRegNum(RCID, LR->getColor()) );
567 int RegNum = MRI.getUnifiedRegNum(RCID, LR->getColor());
571 } // for each operand
574 // If there are instructions to be added *after* this machine
575 // instruction, add them now
577 if( AddedInstrMap[ MInst ] ) {
579 deque<MachineInstr *> &IAft = (AddedInstrMap[MInst])->InstrnsAfter;
581 if( ! IAft.empty() ) {
583 deque<MachineInstr *>::iterator AdIt;
585 ++MInstIterator; // advance to the next instruction
587 for( AdIt = IAft.begin(); AdIt != IAft.end() ; ++AdIt ) {
590 cerr << " *#* APPENDed instr opcode: " << *AdIt << endl;
592 MInstIterator = MIVec.insert( MInstIterator, *AdIt );
596 // MInsterator already points to the next instr. Since the
597 // for loop also increments it, decrement it to point to the
598 // instruction added last
605 } // for each machine instruction
612 //----------------------------------------------------------------------------
613 // This method prints the code with registers after register allocation is
615 //----------------------------------------------------------------------------
616 void PhyRegAlloc::printMachineCode()
619 cout << endl << ";************** Method ";
620 cout << Meth->getName() << " *****************" << endl;
622 Method::const_iterator BBI = Meth->begin(); // random iterator for BBs
624 for( ; BBI != Meth->end(); ++BBI) { // traverse BBs in random order
626 cout << endl ; printLabel( *BBI); cout << ": ";
628 // get the iterator for machine instructions
629 MachineCodeForBasicBlock& MIVec = (*BBI)->getMachineInstrVec();
630 MachineCodeForBasicBlock::iterator MInstIterator = MIVec.begin();
632 // iterate over all the machine instructions in BB
633 for( ; MInstIterator != MIVec.end(); ++MInstIterator) {
635 MachineInstr *const MInst = *MInstIterator;
638 cout << endl << "\t";
639 cout << TargetInstrDescriptors[MInst->getOpCode()].opCodeString;
642 //for(MachineInstr::val_op_const_iterator OpI(MInst);!OpI.done();++OpI) {
644 for(unsigned OpNum=0; OpNum < MInst->getNumOperands(); ++OpNum) {
646 MachineOperand& Op = MInst->getOperand(OpNum);
648 if( Op.getOperandType() == MachineOperand::MO_VirtualRegister ||
649 Op.getOperandType() == MachineOperand::MO_CCRegister /*||
650 Op.getOperandType() == MachineOperand::MO_PCRelativeDisp*/ ) {
652 const Value *const Val = Op.getVRegValue () ;
653 // ****this code is temporary till NULL Values are fixed
655 cout << "\t<*NULL*>";
659 // if a label or a constant
660 if( (Val->getValueType() == Value::BasicBlockVal) ) {
662 cout << "\t"; printLabel( Op.getVRegValue () );
665 // else it must be a register value
666 const int RegNum = Op.getAllocatedRegNum();
668 cout << "\t" << "%" << MRI.getUnifiedRegName( RegNum );
672 else if(Op.getOperandType() == MachineOperand::MO_MachineRegister) {
673 cout << "\t" << "%" << MRI.getUnifiedRegName(Op.getMachineRegNum());
677 cout << "\t" << Op; // use dump field
682 unsigned NumOfImpRefs = MInst->getNumImplicitRefs();
683 if( NumOfImpRefs > 0 ) {
685 cout << "\tImplicit:";
687 for(unsigned z=0; z < NumOfImpRefs; z++) {
688 printValue( MInst->getImplicitRef(z) );
694 } // for all machine instructions
705 //----------------------------------------------------------------------------
707 //----------------------------------------------------------------------------
709 void PhyRegAlloc::colorCallRetArgs()
712 CallRetInstrListType &CallRetInstList = LRI.getCallRetInstrList();
713 CallRetInstrListType::const_iterator It = CallRetInstList.begin();
715 for( ; It != CallRetInstList.end(); ++It ) {
717 const MachineInstr *const CRMI = *It;
718 unsigned OpCode = CRMI->getOpCode();
720 // get the added instructions for this Call/Ret instruciton
721 AddedInstrns *AI = AddedInstrMap[ CRMI ];
723 AI = new AddedInstrns();
724 AddedInstrMap[ CRMI ] = AI;
727 if( (TM.getInstrInfo()).isCall( OpCode ) )
728 MRI.colorCallArgs( CRMI, LRI, AI );
730 else if ( (TM.getInstrInfo()).isReturn(OpCode) )
731 MRI.colorRetValue( CRMI, LRI, AI );
733 else assert( 0 && "Non Call/Ret instrn in CallRetInstrList\n" );
741 //----------------------------------------------------------------------------
743 //----------------------------------------------------------------------------
744 void PhyRegAlloc::colorIncomingArgs()
746 const BasicBlock *const FirstBB = Meth->front();
747 const MachineInstr *FirstMI = *((FirstBB->getMachineInstrVec()).begin());
748 assert( FirstMI && "No machine instruction in entry BB");
750 AddedInstrns *AI = AddedInstrMap[ FirstMI ];
752 AI = new AddedInstrns();
753 AddedInstrMap[ FirstMI ] = AI;
756 MRI.colorMethodArgs(Meth, LRI, AI );
760 //----------------------------------------------------------------------------
761 // Used to generate a label for a basic block
762 //----------------------------------------------------------------------------
763 void PhyRegAlloc::printLabel(const Value *const Val)
766 cout << Val->getName();
768 cout << "Label" << Val;
772 //----------------------------------------------------------------------------
773 // This method calls setSugColorUsable method of each live range. This
774 // will determine whether the suggested color of LR is really usable.
775 // A suggested color is not usable when the suggested color is volatile
776 // AND when there are call interferences
777 //----------------------------------------------------------------------------
779 void PhyRegAlloc::markUnusableSugColors()
781 if(DEBUG_RA ) cout << "Creating LR lists ..." << endl;
784 LiveRangeMapType::const_iterator HMI = (LRI.getLiveRangeMap())->begin();
785 LiveRangeMapType::const_iterator HMIEnd = (LRI.getLiveRangeMap())->end();
787 for( ; HMI != HMIEnd ; ++HMI ) {
791 LiveRange *L = (*HMI).second; // get the LiveRange
794 if( L->hasSuggestedColor() ) {
796 int RCID = (L->getRegClass())->getID();
797 if( MRI.isRegVolatile( RCID, L->getSuggestedColor()) &&
798 L->isCallInterference() )
799 L->setSuggestedColorUsable( false );
801 L->setSuggestedColorUsable( true );
803 } // if L->hasSuggestedColor()
805 } // for all LR's in hash map
818 //----------------------------------------------------------------------------
819 // The entry pont to Register Allocation
820 //----------------------------------------------------------------------------
822 void PhyRegAlloc::allocateRegisters()
825 // make sure that we put all register classes into the RegClassList
826 // before we call constructLiveRanges (now done in the constructor of
827 // PhyRegAlloc class).
829 constructLiveRanges(); // create LR info
832 LRI.printLiveRanges();
834 createIGNodeListsAndIGs(); // create IGNode list and IGs
836 buildInterferenceGraphs(); // build IGs in all reg classes
840 // print all LRs in all reg classes
841 for( unsigned int rc=0; rc < NumOfRegClasses ; rc++)
842 RegClassList[ rc ]->printIGNodeList();
844 // print IGs in all register classes
845 for( unsigned int rc=0; rc < NumOfRegClasses ; rc++)
846 RegClassList[ rc ]->printIG();
849 LRI.coalesceLRs(); // coalesce all live ranges
852 // print all LRs in all reg classes
853 for( unsigned int rc=0; rc < NumOfRegClasses ; rc++)
854 RegClassList[ rc ]->printIGNodeList();
856 // print IGs in all register classes
857 for( unsigned int rc=0; rc < NumOfRegClasses ; rc++)
858 RegClassList[ rc ]->printIG();
862 // mark un-usable suggested color before graph coloring algorithm.
863 // When this is done, the graph coloring algo will not reserve
864 // suggested color unnecessarily - they can be used by another LR
865 markUnusableSugColors();
867 // color all register classes using the graph coloring algo
868 for( unsigned int rc=0; rc < NumOfRegClasses ; rc++)
869 RegClassList[ rc ]->colorAllRegs();
872 // color incoming args and call args
879 PrintMachineInstructions(Meth);
880 printMachineCode(); // only for DEBUGGING