2 //***************************************************************************
7 // Register allocation for LLVM.
10 // 9/10/01 - Ruchira Sasanka - created.
11 //**************************************************************************/
13 #include "llvm/CodeGen/PhyRegAlloc.h"
14 #include "llvm/CodeGen/MachineInstr.h"
15 #include "llvm/Target/TargetMachine.h"
16 #include "llvm/Target/MachineFrameInfo.h"
19 // ***TODO: There are several places we add instructions. Validate the order
20 // of adding these instructions.
24 cl::Enum<RegAllocDebugLevel_t> DEBUG_RA("dregalloc", cl::NoFlags,
25 "enable register allocation debugging information",
26 clEnumValN(RA_DEBUG_None , "n", "disable debug output"),
27 clEnumValN(RA_DEBUG_Normal , "y", "enable debug output"),
28 clEnumValN(RA_DEBUG_Verbose, "v", "enable extra debug output"), 0);
31 //----------------------------------------------------------------------------
32 // Constructor: Init local composite objects and create register classes.
33 //----------------------------------------------------------------------------
34 PhyRegAlloc::PhyRegAlloc(Method *M,
35 const TargetMachine& tm,
36 MethodLiveVarInfo *const Lvi)
40 mcInfo(MachineCodeForMethod::get(M)),
41 LVI(Lvi), LRI(M, tm, RegClassList),
42 MRI( tm.getRegInfo() ),
43 NumOfRegClasses(MRI.getNumOfRegClasses()),
47 // **TODO: use an actual reserved color list
48 ReservedColorListType *RCL = new ReservedColorListType();
50 // create each RegisterClass and put in RegClassList
51 for( unsigned int rc=0; rc < NumOfRegClasses; rc++)
52 RegClassList.push_back( new RegClass(M, MRI.getMachineRegClass(rc), RCL) );
55 //----------------------------------------------------------------------------
56 // This method initally creates interference graphs (one in each reg class)
57 // and IGNodeList (one in each IG). The actual nodes will be pushed later.
58 //----------------------------------------------------------------------------
60 void PhyRegAlloc::createIGNodeListsAndIGs()
62 if(DEBUG_RA ) cout << "Creating LR lists ..." << endl;
65 LiveRangeMapType::const_iterator HMI = (LRI.getLiveRangeMap())->begin();
68 LiveRangeMapType::const_iterator HMIEnd = (LRI.getLiveRangeMap())->end();
70 for( ; HMI != HMIEnd ; ++HMI ) {
74 LiveRange *L = (*HMI).second; // get the LiveRange
78 cout << "\n*?!?Warning: Null liver range found for: ";
79 printValue( (*HMI).first) ; cout << endl;
83 // if the Value * is not null, and LR
84 // is not yet written to the IGNodeList
85 if( !(L->getUserIGNode()) ) {
87 RegClass *const RC = // RegClass of first value in the LR
88 //RegClassList [MRI.getRegClassIDOfValue(*(L->begin()))];
89 RegClassList[ L->getRegClass()->getID() ];
91 RC-> addLRToIG( L ); // add this LR to an IG
97 for( unsigned int rc=0; rc < NumOfRegClasses ; rc++)
98 RegClassList[ rc ]->createInterferenceGraph();
101 cout << "LRLists Created!" << endl;
106 //----------------------------------------------------------------------------
107 // This method will add all interferences at for a given instruction.
108 // Interence occurs only if the LR of Def (Inst or Arg) is of the same reg
109 // class as that of live var. The live var passed to this function is the
110 // LVset AFTER the instruction
111 //----------------------------------------------------------------------------
113 void PhyRegAlloc::addInterference(const Value *const Def,
114 const LiveVarSet *const LVSet,
115 const bool isCallInst) {
117 LiveVarSet::const_iterator LIt = LVSet->begin();
119 // get the live range of instruction
120 const LiveRange *const LROfDef = LRI.getLiveRangeForValue( Def );
122 IGNode *const IGNodeOfDef = LROfDef->getUserIGNode();
123 assert( IGNodeOfDef );
125 RegClass *const RCOfDef = LROfDef->getRegClass();
127 // for each live var in live variable set
128 for( ; LIt != LVSet->end(); ++LIt) {
131 cout << "< Def="; printValue(Def);
132 cout << ", Lvar="; printValue( *LIt); cout << "> ";
135 // get the live range corresponding to live var
136 LiveRange *const LROfVar = LRI.getLiveRangeForValue(*LIt );
138 // LROfVar can be null if it is a const since a const
139 // doesn't have a dominating def - see Assumptions above
142 if(LROfDef == LROfVar) // do not set interf for same LR
145 // if 2 reg classes are the same set interference
146 if( RCOfDef == LROfVar->getRegClass() ){
147 RCOfDef->setInterference( LROfDef, LROfVar);
151 else if(DEBUG_RA > 1) {
152 // we will not have LRs for values not explicitly allocated in the
153 // instruction stream (e.g., constants)
154 cout << " warning: no live range for " ;
155 printValue( *LIt); cout << endl; }
164 //----------------------------------------------------------------------------
165 // For a call instruction, this method sets the CallInterference flag in
166 // the LR of each variable live int the Live Variable Set live after the
167 // call instruction (except the return value of the call instruction - since
168 // the return value does not interfere with that call itself).
169 //----------------------------------------------------------------------------
171 void PhyRegAlloc::setCallInterferences(const MachineInstr *MInst,
172 const LiveVarSet *const LVSetAft )
174 // Now find the LR of the return value of the call
177 // We do this because, we look at the LV set *after* the instruction
178 // to determine, which LRs must be saved across calls. The return value
179 // of the call is live in this set - but it does not interfere with call
180 // (i.e., we can allocate a volatile register to the return value)
182 LiveRange *RetValLR = NULL;
184 const Value *RetVal = MRI.getCallInstRetVal( MInst );
187 RetValLR = LRI.getLiveRangeForValue( RetVal );
188 assert( RetValLR && "No LR for RetValue of call");
192 cout << "\n For call inst: " << *MInst;
194 LiveVarSet::const_iterator LIt = LVSetAft->begin();
196 // for each live var in live variable set after machine inst
197 for( ; LIt != LVSetAft->end(); ++LIt) {
199 // get the live range corresponding to live var
200 LiveRange *const LR = LRI.getLiveRangeForValue(*LIt );
202 if( LR && DEBUG_RA) {
203 cout << "\n\tLR Aft Call: ";
208 // LR can be null if it is a const since a const
209 // doesn't have a dominating def - see Assumptions above
210 if( LR && (LR != RetValLR) ) {
211 LR->setCallInterference();
213 cout << "\n ++Added call interf for LR: " ;
223 //----------------------------------------------------------------------------
224 // This method will walk thru code and create interferences in the IG of
226 //----------------------------------------------------------------------------
228 void PhyRegAlloc::buildInterferenceGraphs()
231 if(DEBUG_RA) cout << "Creating interference graphs ..." << endl;
233 Method::const_iterator BBI = Meth->begin(); // random iterator for BBs
235 for( ; BBI != Meth->end(); ++BBI) { // traverse BBs in random order
237 // get the iterator for machine instructions
238 const MachineCodeForBasicBlock& MIVec = (*BBI)->getMachineInstrVec();
239 MachineCodeForBasicBlock::const_iterator
240 MInstIterator = MIVec.begin();
242 // iterate over all the machine instructions in BB
243 for( ; MInstIterator != MIVec.end(); ++MInstIterator) {
245 const MachineInstr * MInst = *MInstIterator;
247 // get the LV set after the instruction
248 const LiveVarSet *const LVSetAI =
249 LVI->getLiveVarSetAfterMInst(MInst, *BBI);
251 const bool isCallInst = TM.getInstrInfo().isCall(MInst->getOpCode());
254 //cout << "\nFor call inst: " << *MInst;
256 // set the isCallInterference flag of each live range wich extends
257 // accross this call instruction. This information is used by graph
258 // coloring algo to avoid allocating volatile colors to live ranges
259 // that span across calls (since they have to be saved/restored)
260 setCallInterferences( MInst, LVSetAI);
264 // iterate over MI operands to find defs
265 for( MachineInstr::val_op_const_iterator OpI(MInst);!OpI.done(); ++OpI) {
268 // create a new LR iff this operand is a def
269 addInterference(*OpI, LVSetAI, isCallInst );
273 } // for all operands
276 // Also add interference for any implicit definitions in a machine
277 // instr (currently, only calls have this).
279 unsigned NumOfImpRefs = MInst->getNumImplicitRefs();
280 if( NumOfImpRefs > 0 ) {
281 for(unsigned z=0; z < NumOfImpRefs; z++)
282 if( MInst->implicitRefIsDefined(z) )
283 addInterference( MInst->getImplicitRef(z), LVSetAI, isCallInst );
287 // record phi instrns in PhiInstList
288 if( TM.getInstrInfo().isDummyPhiInstr(MInst->getOpCode()) )
289 PhiInstList.push_back( MInst );
292 } // for all machine instructions in BB
294 } // for all BBs in method
297 // add interferences for method arguments. Since there are no explict
298 // defs in method for args, we have to add them manually
300 addInterferencesForArgs(); // add interference for method args
303 cout << "Interference graphs calculted!" << endl;
310 //----------------------------------------------------------------------------
311 // This method will add interferences for incoming arguments to a method.
312 //----------------------------------------------------------------------------
313 void PhyRegAlloc::addInterferencesForArgs()
315 // get the InSet of root BB
316 const LiveVarSet *const InSet = LVI->getInSetOfBB( Meth->front() );
318 // get the argument list
319 const Method::ArgumentListType& ArgList = Meth->getArgumentList();
321 // get an iterator to arg list
322 Method::ArgumentListType::const_iterator ArgIt = ArgList.begin();
325 for( ; ArgIt != ArgList.end() ; ++ArgIt) { // for each argument
326 addInterference( *ArgIt, InSet, false ); // add interferences between
327 // args and LVars at start
329 cout << " - %% adding interference for argument ";
330 printValue( (const Value *) *ArgIt); cout << endl;
336 //----------------------------------------------------------------------------
337 // This method is called after register allocation is complete to set the
338 // allocated reisters in the machine code. This code will add register numbers
339 // to MachineOperands that contain a Value.
340 //----------------------------------------------------------------------------
342 void PhyRegAlloc::updateMachineCode()
345 Method::const_iterator BBI = Meth->begin(); // random iterator for BBs
347 for( ; BBI != Meth->end(); ++BBI) { // traverse BBs in random order
349 // get the iterator for machine instructions
350 MachineCodeForBasicBlock& MIVec = (*BBI)->getMachineInstrVec();
351 MachineCodeForBasicBlock::iterator MInstIterator = MIVec.begin();
353 // iterate over all the machine instructions in BB
354 for( ; MInstIterator != MIVec.end(); ++MInstIterator) {
356 MachineInstr *MInst = *MInstIterator;
358 // if this machine instr is call, insert caller saving code
360 if( (TM.getInstrInfo()).isCall( MInst->getOpCode()) )
361 MRI.insertCallerSavingCode(MInst, *BBI, *this );
363 // If there are instructions to be added, *before* this machine
364 // instruction, add them now.
366 if( AddedInstrMap[ MInst ] ) {
368 deque<MachineInstr *> &IBef = (AddedInstrMap[MInst])->InstrnsBefore;
370 if( ! IBef.empty() ) {
372 deque<MachineInstr *>::iterator AdIt;
374 for( AdIt = IBef.begin(); AdIt != IBef.end() ; ++AdIt ) {
377 cerr << " *$* PREPENDed instr " << *AdIt << endl;
379 MInstIterator = MIVec.insert( MInstIterator, *AdIt );
387 // reset the stack offset for temporary variables since we may
388 // need that to spill
389 mcInfo.popAllTempValues(TM);
391 //for(MachineInstr::val_op_const_iterator OpI(MInst);!OpI.done();++OpI) {
393 for(unsigned OpNum=0; OpNum < MInst->getNumOperands(); ++OpNum) {
395 MachineOperand& Op = MInst->getOperand(OpNum);
397 if( Op.getOperandType() == MachineOperand::MO_VirtualRegister ||
398 Op.getOperandType() == MachineOperand::MO_CCRegister) {
400 const Value *const Val = Op.getVRegValue();
402 // delete this condition checking later (must assert if Val is null)
405 cout << "Warning: NULL Value found for operand" << endl;
408 assert( Val && "Value is NULL");
410 LiveRange *const LR = LRI.getLiveRangeForValue(Val);
414 // nothing to worry if it's a const or a label
417 cout << "*NO LR for operand : " << Op ;
418 cout << " [reg:" << Op.getAllocatedRegNum() << "]";
419 cout << " in inst:\t" << *MInst << endl;
422 // if register is not allocated, mark register as invalid
423 if( Op.getAllocatedRegNum() == -1)
424 Op.setRegForValue( MRI.getInvalidRegNum());
430 unsigned RCID = (LR->getRegClass())->getID();
432 if( LR->hasColor() ) {
433 Op.setRegForValue( MRI.getUnifiedRegNum(RCID, LR->getColor()) );
437 // LR did NOT receive a color (register). Now, insert spill code
438 // for spilled opeands in this machine instruction
440 assert(0 && "LR must be spilled");
441 // insertCode4SpilledLR(LR, MInst, *BBI, OpNum );
446 } // for each operand
449 // If there are instructions to be added *after* this machine
450 // instruction, add them now
452 if( AddedInstrMap[ MInst ] &&
453 ! (AddedInstrMap[ MInst ]->InstrnsAfter).empty() ) {
455 // if there are delay slots for this instruction, the instructions
456 // added after it must really go after the delayed instruction(s)
457 // So, we move the InstrAfter of the current instruction to the
458 // corresponding delayed instruction
461 if((delay=TM.getInstrInfo().getNumDelaySlots(MInst->getOpCode())) >0){
462 move2DelayedInstr(MInst, *(MInstIterator+delay) );
464 if(DEBUG_RA) cout<< "\nMoved an added instr after the delay slot";
470 // Here we can add the "instructions after" to the current
471 // instruction since there are no delay slots for this instruction
473 deque<MachineInstr *> &IAft = (AddedInstrMap[MInst])->InstrnsAfter;
475 if( ! IAft.empty() ) {
477 deque<MachineInstr *>::iterator AdIt;
479 ++MInstIterator; // advance to the next instruction
481 for( AdIt = IAft.begin(); AdIt != IAft.end() ; ++AdIt ) {
484 cerr << " *#* APPENDed instr opcode: " << *AdIt << endl;
486 MInstIterator = MIVec.insert( MInstIterator, *AdIt );
490 // MInsterator already points to the next instr. Since the
491 // for loop also increments it, decrement it to point to the
492 // instruction added last
501 } // for each machine instruction
506 //----------------------------------------------------------------------------
507 // We can use the following method to get a temporary register to be used
508 // BEFORE any given machine instruction. If there is a register available,
509 // this method will simply return that register and set MIBef = MIAft = NULL.
510 // Otherwise, it will return a register and MIAft and MIBef will contain
511 // two instructions used to free up this returned register.
512 // Returned register number is the UNIFIED register number
513 //----------------------------------------------------------------------------
515 int PhyRegAlloc::getUsableRegAtMI(RegClass *RC,
517 const MachineInstr *MInst,
518 const LiveVarSet *LVSetBef,
520 MachineInstr *MIAft) {
522 int Reg = getUnusedRegAtMI(RC, MInst, LVSetBef);
523 Reg = MRI.getUnifiedRegNum(RC->getID(), Reg);
526 // we found an unused register, so we can simply used
527 MIBef = MIAft = NULL;
530 // we couldn't find an unused register. Generate code to free up a reg by
531 // saving it on stack and restoring after the instruction
533 /**** NOTE: THIS SHOULD USE THE RIGHT SIZE FOR THE REG BEING PUSHED ****/
534 int TmpOff = mcInfo.pushTempValue(TM, /*size*/ 8);
536 Reg = getRegNotUsedByThisInst(RC, MInst);
537 MIBef = MRI.cpReg2MemMI(Reg, MRI.getFramePointer(), TmpOff, RegType );
538 MIAft = MRI.cpMem2RegMI(MRI.getFramePointer(), TmpOff, Reg, RegType );
544 //----------------------------------------------------------------------------
545 // This method is called to get a new unused register that can be used to
546 // accomodate a spilled value.
547 // This method may be called several times for a single machine instruction
548 // if it contains many spilled operands. Each time it is called, it finds
549 // a register which is not live at that instruction and also which is not
550 // used by other spilled operands of the same instruction.
551 // Return register number is relative to the register class. NOT
553 //----------------------------------------------------------------------------
554 int PhyRegAlloc::getUnusedRegAtMI(RegClass *RC,
555 const MachineInstr *MInst,
556 const LiveVarSet *LVSetBef) {
558 unsigned NumAvailRegs = RC->getNumOfAvailRegs();
560 bool *IsColorUsedArr = RC->getIsColorUsedArr();
562 for(unsigned i=0; i < NumAvailRegs; i++)
563 IsColorUsedArr[i] = false;
565 LiveVarSet::const_iterator LIt = LVSetBef->begin();
567 // for each live var in live variable set after machine inst
568 for( ; LIt != LVSetBef->end(); ++LIt) {
570 // get the live range corresponding to live var
571 LiveRange *const LRofLV = LRI.getLiveRangeForValue(*LIt );
573 // LR can be null if it is a const since a const
574 // doesn't have a dominating def - see Assumptions above
576 if( LRofLV->hasColor() )
577 IsColorUsedArr[ LRofLV->getColor() ] = true;
580 // It is possible that one operand of this MInst was already spilled
581 // and it received some register temporarily. If that's the case,
582 // it is recorded in machine operand. We must skip such registers.
584 setRegsUsedByThisInst(RC, MInst);
586 unsigned c; // find first unused color
587 for( c=0; c < NumAvailRegs; c++)
588 if( ! IsColorUsedArr[ c ] ) break;
600 //----------------------------------------------------------------------------
601 // This method modifies the IsColorUsedArr of the register class passed to it.
602 // It sets the bits corresponding to the registers used by this machine
603 // instructions. Explicit operands are set.
604 //----------------------------------------------------------------------------
605 void PhyRegAlloc::setRegsUsedByThisInst(RegClass *RC,
606 const MachineInstr *MInst ) {
608 bool *IsColorUsedArr = RC->getIsColorUsedArr();
610 for(unsigned OpNum=0; OpNum < MInst->getNumOperands(); ++OpNum) {
612 const MachineOperand& Op = MInst->getOperand(OpNum);
614 if( Op.getOperandType() == MachineOperand::MO_VirtualRegister ||
615 Op.getOperandType() == MachineOperand::MO_CCRegister) {
617 const Value *const Val = Op.getVRegValue();
620 if( MRI.getRegClassIDOfValue( Val )== RC->getID() ) {
622 if( (Reg=Op.getAllocatedRegNum()) != -1)
623 IsColorUsedArr[ Reg ] = true;
629 // If there are implicit references, mark them as well
631 for(unsigned z=0; z < MInst->getNumImplicitRefs(); z++) {
633 LiveRange *const LRofImpRef =
634 LRI.getLiveRangeForValue( MInst->getImplicitRef(z) );
637 if( LRofImpRef->hasColor() )
638 IsColorUsedArr[ LRofImpRef->getColor() ] = true;
647 //----------------------------------------------------------------------------
648 // Get any other register in a register class, other than what is used
649 // by operands of a machine instruction.
650 //----------------------------------------------------------------------------
651 int PhyRegAlloc::getRegNotUsedByThisInst(RegClass *RC,
652 const MachineInstr *MInst) {
654 bool *IsColorUsedArr = RC->getIsColorUsedArr();
655 unsigned NumAvailRegs = RC->getNumOfAvailRegs();
658 for(unsigned i=0; i < NumAvailRegs ; i++)
659 IsColorUsedArr[i] = false;
661 setRegsUsedByThisInst(RC, MInst);
663 unsigned c; // find first unused color
664 for( c=0; c < RC->getNumOfAvailRegs(); c++)
665 if( ! IsColorUsedArr[ c ] ) break;
670 assert( 0 && "FATAL: No free register could be found in reg class!!");
678 //----------------------------------------------------------------------------
679 // If there are delay slots for an instruction, the instructions
680 // added after it must really go after the delayed instruction(s).
681 // So, we move the InstrAfter of that instruction to the
682 // corresponding delayed instruction using the following method.
684 //----------------------------------------------------------------------------
685 void PhyRegAlloc:: move2DelayedInstr(const MachineInstr *OrigMI,
686 const MachineInstr *DelayedMI) {
689 // "added after" instructions of the original instr
690 deque<MachineInstr *> &OrigAft = (AddedInstrMap[OrigMI])->InstrnsAfter;
692 // "added instructions" of the delayed instr
693 AddedInstrns *DelayAdI = AddedInstrMap[DelayedMI];
695 if(! DelayAdI ) { // create a new "added after" if necessary
696 DelayAdI = new AddedInstrns();
697 AddedInstrMap[DelayedMI] = DelayAdI;
700 // "added after" instructions of the delayed instr
701 deque<MachineInstr *> &DelayedAft = DelayAdI->InstrnsAfter;
703 // go thru all the "added after instructions" of the original instruction
704 // and append them to the "addded after instructions" of the delayed
707 deque<MachineInstr *>::iterator OrigAdIt;
709 for( OrigAdIt = OrigAft.begin(); OrigAdIt != OrigAft.end() ; ++OrigAdIt ) {
710 DelayedAft.push_back( *OrigAdIt );
713 // empty the "added after instructions" of the original instruction
718 //----------------------------------------------------------------------------
719 // This method prints the code with registers after register allocation is
721 //----------------------------------------------------------------------------
722 void PhyRegAlloc::printMachineCode()
725 cout << endl << ";************** Method ";
726 cout << Meth->getName() << " *****************" << endl;
728 Method::const_iterator BBI = Meth->begin(); // random iterator for BBs
730 for( ; BBI != Meth->end(); ++BBI) { // traverse BBs in random order
732 cout << endl ; printLabel( *BBI); cout << ": ";
734 // get the iterator for machine instructions
735 MachineCodeForBasicBlock& MIVec = (*BBI)->getMachineInstrVec();
736 MachineCodeForBasicBlock::iterator MInstIterator = MIVec.begin();
738 // iterate over all the machine instructions in BB
739 for( ; MInstIterator != MIVec.end(); ++MInstIterator) {
741 MachineInstr *const MInst = *MInstIterator;
744 cout << endl << "\t";
745 cout << TargetInstrDescriptors[MInst->getOpCode()].opCodeString;
748 //for(MachineInstr::val_op_const_iterator OpI(MInst);!OpI.done();++OpI) {
750 for(unsigned OpNum=0; OpNum < MInst->getNumOperands(); ++OpNum) {
752 MachineOperand& Op = MInst->getOperand(OpNum);
754 if( Op.getOperandType() == MachineOperand::MO_VirtualRegister ||
755 Op.getOperandType() == MachineOperand::MO_CCRegister /*||
756 Op.getOperandType() == MachineOperand::MO_PCRelativeDisp*/ ) {
758 const Value *const Val = Op.getVRegValue () ;
759 // ****this code is temporary till NULL Values are fixed
761 cout << "\t<*NULL*>";
765 // if a label or a constant
766 if( (Val->getValueType() == Value::BasicBlockVal) ) {
768 cout << "\t"; printLabel( Op.getVRegValue () );
771 // else it must be a register value
772 const int RegNum = Op.getAllocatedRegNum();
774 cout << "\t" << "%" << MRI.getUnifiedRegName( RegNum );
778 else if(Op.getOperandType() == MachineOperand::MO_MachineRegister) {
779 cout << "\t" << "%" << MRI.getUnifiedRegName(Op.getMachineRegNum());
783 cout << "\t" << Op; // use dump field
788 unsigned NumOfImpRefs = MInst->getNumImplicitRefs();
789 if( NumOfImpRefs > 0 ) {
791 cout << "\tImplicit:";
793 for(unsigned z=0; z < NumOfImpRefs; z++) {
794 printValue( MInst->getImplicitRef(z) );
800 } // for all machine instructions
811 //----------------------------------------------------------------------------
813 //----------------------------------------------------------------------------
815 void PhyRegAlloc::colorCallRetArgs()
818 CallRetInstrListType &CallRetInstList = LRI.getCallRetInstrList();
819 CallRetInstrListType::const_iterator It = CallRetInstList.begin();
821 for( ; It != CallRetInstList.end(); ++It ) {
823 const MachineInstr *const CRMI = *It;
824 unsigned OpCode = CRMI->getOpCode();
826 // get the added instructions for this Call/Ret instruciton
827 AddedInstrns *AI = AddedInstrMap[ CRMI ];
829 AI = new AddedInstrns();
830 AddedInstrMap[ CRMI ] = AI;
833 // Tmp stack poistions are needed by some calls that have spilled args
834 // So reset it before we call each such method
835 mcInfo.popAllTempValues(TM);
837 if( (TM.getInstrInfo()).isCall( OpCode ) )
838 MRI.colorCallArgs( CRMI, LRI, AI, *this );
840 else if ( (TM.getInstrInfo()).isReturn(OpCode) )
841 MRI.colorRetValue( CRMI, LRI, AI );
843 else assert( 0 && "Non Call/Ret instrn in CallRetInstrList\n" );
851 //----------------------------------------------------------------------------
853 //----------------------------------------------------------------------------
854 void PhyRegAlloc::colorIncomingArgs()
856 const BasicBlock *const FirstBB = Meth->front();
857 const MachineInstr *FirstMI = *((FirstBB->getMachineInstrVec()).begin());
858 assert( FirstMI && "No machine instruction in entry BB");
860 AddedInstrns *AI = AddedInstrMap[ FirstMI ];
862 AI = new AddedInstrns();
863 AddedInstrMap[ FirstMI ] = AI;
866 MRI.colorMethodArgs(Meth, LRI, AI );
870 //----------------------------------------------------------------------------
871 // Used to generate a label for a basic block
872 //----------------------------------------------------------------------------
873 void PhyRegAlloc::printLabel(const Value *const Val)
876 cout << Val->getName();
878 cout << "Label" << Val;
882 //----------------------------------------------------------------------------
883 // This method calls setSugColorUsable method of each live range. This
884 // will determine whether the suggested color of LR is really usable.
885 // A suggested color is not usable when the suggested color is volatile
886 // AND when there are call interferences
887 //----------------------------------------------------------------------------
889 void PhyRegAlloc::markUnusableSugColors()
891 if(DEBUG_RA ) cout << "\nmarking unusable suggested colors ..." << endl;
894 LiveRangeMapType::const_iterator HMI = (LRI.getLiveRangeMap())->begin();
895 LiveRangeMapType::const_iterator HMIEnd = (LRI.getLiveRangeMap())->end();
897 for( ; HMI != HMIEnd ; ++HMI ) {
901 LiveRange *L = (*HMI).second; // get the LiveRange
904 if( L->hasSuggestedColor() ) {
906 int RCID = (L->getRegClass())->getID();
907 if( MRI.isRegVolatile( RCID, L->getSuggestedColor()) &&
908 L->isCallInterference() )
909 L->setSuggestedColorUsable( false );
911 L->setSuggestedColorUsable( true );
913 } // if L->hasSuggestedColor()
915 } // for all LR's in hash map
920 //----------------------------------------------------------------------------
921 // The following method will set the stack offsets of the live ranges that
922 // are decided to be spillled. This must be called just after coloring the
923 // LRs using the graph coloring algo. For each live range that is spilled,
924 // this method allocate a new spill position on the stack.
925 //----------------------------------------------------------------------------
927 void PhyRegAlloc::allocateStackSpace4SpilledLRs()
929 if(DEBUG_RA ) cout << "\nsetting LR stack offsets ..." << endl;
932 LiveRangeMapType::const_iterator HMI = (LRI.getLiveRangeMap())->begin();
933 LiveRangeMapType::const_iterator HMIEnd = (LRI.getLiveRangeMap())->end();
935 for( ; HMI != HMIEnd ; ++HMI ) {
937 LiveRange *L = (*HMI).second; // get the LiveRange
939 if( ! L->hasColor() )
940 L->setSpillOffFromFP(mcInfo.allocateSpilledValue(TM,L->getType()));
942 } // for all LR's in hash map
947 //----------------------------------------------------------------------------
948 // The entry pont to Register Allocation
949 //----------------------------------------------------------------------------
951 void PhyRegAlloc::allocateRegisters()
954 // make sure that we put all register classes into the RegClassList
955 // before we call constructLiveRanges (now done in the constructor of
956 // PhyRegAlloc class).
958 constructLiveRanges(); // create LR info
961 LRI.printLiveRanges();
963 createIGNodeListsAndIGs(); // create IGNode list and IGs
965 buildInterferenceGraphs(); // build IGs in all reg classes
969 // print all LRs in all reg classes
970 for( unsigned int rc=0; rc < NumOfRegClasses ; rc++)
971 RegClassList[ rc ]->printIGNodeList();
973 // print IGs in all register classes
974 for( unsigned int rc=0; rc < NumOfRegClasses ; rc++)
975 RegClassList[ rc ]->printIG();
978 LRI.coalesceLRs(); // coalesce all live ranges
980 // coalscing could not get rid of all phi's, add phi elimination
982 // insertPhiEleminateInstrns();
985 // print all LRs in all reg classes
986 for( unsigned int rc=0; rc < NumOfRegClasses ; rc++)
987 RegClassList[ rc ]->printIGNodeList();
989 // print IGs in all register classes
990 for( unsigned int rc=0; rc < NumOfRegClasses ; rc++)
991 RegClassList[ rc ]->printIG();
995 // mark un-usable suggested color before graph coloring algorithm.
996 // When this is done, the graph coloring algo will not reserve
997 // suggested color unnecessarily - they can be used by another LR
998 markUnusableSugColors();
1000 // color all register classes using the graph coloring algo
1001 for( unsigned int rc=0; rc < NumOfRegClasses ; rc++)
1002 RegClassList[ rc ]->colorAllRegs();
1004 // Atter grpah coloring, if some LRs did not receive a color (i.e, spilled)
1005 // a poistion for such spilled LRs
1006 allocateStackSpace4SpilledLRs();
1008 // color incoming args and call args
1009 colorIncomingArgs();
1013 updateMachineCode();
1015 MachineCodeForMethod::get(Meth).dump();
1016 printMachineCode(); // only for DEBUGGING