2 //***************************************************************************
7 // Register allocation for LLVM.
10 // 9/10/01 - Ruchira Sasanka - created.
11 //**************************************************************************/
13 #include "llvm/CodeGen/PhyRegAlloc.h"
14 #include "llvm/CodeGen/MachineInstr.h"
15 #include "llvm/Target/TargetMachine.h"
16 #include "llvm/Target/MachineFrameInfo.h"
19 // ***TODO: There are several places we add instructions. Validate the order
20 // of adding these instructions.
24 cl::Enum<RegAllocDebugLevel_t> DEBUG_RA("dregalloc", cl::NoFlags,
25 "enable register allocation debugging information",
26 clEnumValN(RA_DEBUG_None , "n", "disable debug output"),
27 clEnumValN(RA_DEBUG_Normal , "y", "enable debug output"),
28 clEnumValN(RA_DEBUG_Verbose, "v", "enable extra debug output"), 0);
31 //----------------------------------------------------------------------------
32 // Constructor: Init local composite objects and create register classes.
33 //----------------------------------------------------------------------------
34 PhyRegAlloc::PhyRegAlloc(Method *M,
35 const TargetMachine& tm,
36 MethodLiveVarInfo *const Lvi)
40 mcInfo(MachineCodeForMethod::get(M)),
41 LVI(Lvi), LRI(M, tm, RegClassList),
42 MRI( tm.getRegInfo() ),
43 NumOfRegClasses(MRI.getNumOfRegClasses()),
47 // **TODO: use an actual reserved color list
48 ReservedColorListType *RCL = new ReservedColorListType();
50 // create each RegisterClass and put in RegClassList
51 for( unsigned int rc=0; rc < NumOfRegClasses; rc++)
52 RegClassList.push_back( new RegClass(M, MRI.getMachineRegClass(rc), RCL) );
55 //----------------------------------------------------------------------------
56 // This method initally creates interference graphs (one in each reg class)
57 // and IGNodeList (one in each IG). The actual nodes will be pushed later.
58 //----------------------------------------------------------------------------
60 void PhyRegAlloc::createIGNodeListsAndIGs()
62 if(DEBUG_RA ) cout << "Creating LR lists ..." << endl;
65 LiveRangeMapType::const_iterator HMI = (LRI.getLiveRangeMap())->begin();
68 LiveRangeMapType::const_iterator HMIEnd = (LRI.getLiveRangeMap())->end();
70 for( ; HMI != HMIEnd ; ++HMI ) {
74 LiveRange *L = (*HMI).second; // get the LiveRange
78 cout << "\n*?!?Warning: Null liver range found for: ";
79 printValue( (*HMI).first) ; cout << endl;
83 // if the Value * is not null, and LR
84 // is not yet written to the IGNodeList
85 if( !(L->getUserIGNode()) ) {
87 RegClass *const RC = // RegClass of first value in the LR
88 //RegClassList [MRI.getRegClassIDOfValue(*(L->begin()))];
89 RegClassList[ L->getRegClass()->getID() ];
91 RC-> addLRToIG( L ); // add this LR to an IG
97 for( unsigned int rc=0; rc < NumOfRegClasses ; rc++)
98 RegClassList[ rc ]->createInterferenceGraph();
101 cout << "LRLists Created!" << endl;
106 //----------------------------------------------------------------------------
107 // This method will add all interferences at for a given instruction.
108 // Interence occurs only if the LR of Def (Inst or Arg) is of the same reg
109 // class as that of live var. The live var passed to this function is the
110 // LVset AFTER the instruction
111 //----------------------------------------------------------------------------
113 void PhyRegAlloc::addInterference(const Value *const Def,
114 const LiveVarSet *const LVSet,
115 const bool isCallInst) {
117 LiveVarSet::const_iterator LIt = LVSet->begin();
119 // get the live range of instruction
120 const LiveRange *const LROfDef = LRI.getLiveRangeForValue( Def );
122 IGNode *const IGNodeOfDef = LROfDef->getUserIGNode();
123 assert( IGNodeOfDef );
125 RegClass *const RCOfDef = LROfDef->getRegClass();
127 // for each live var in live variable set
128 for( ; LIt != LVSet->end(); ++LIt) {
131 cout << "< Def="; printValue(Def);
132 cout << ", Lvar="; printValue( *LIt); cout << "> ";
135 // get the live range corresponding to live var
136 LiveRange *const LROfVar = LRI.getLiveRangeForValue(*LIt );
138 // LROfVar can be null if it is a const since a const
139 // doesn't have a dominating def - see Assumptions above
142 if(LROfDef == LROfVar) // do not set interf for same LR
145 // if 2 reg classes are the same set interference
146 if( RCOfDef == LROfVar->getRegClass() ){
147 RCOfDef->setInterference( LROfDef, LROfVar);
151 else if(DEBUG_RA > 1) {
152 // we will not have LRs for values not explicitly allocated in the
153 // instruction stream (e.g., constants)
154 cout << " warning: no live range for " ;
155 printValue( *LIt); cout << endl; }
164 //----------------------------------------------------------------------------
165 // For a call instruction, this method sets the CallInterference flag in
166 // the LR of each variable live int the Live Variable Set live after the
167 // call instruction (except the return value of the call instruction - since
168 // the return value does not interfere with that call itself).
169 //----------------------------------------------------------------------------
171 void PhyRegAlloc::setCallInterferences(const MachineInstr *MInst,
172 const LiveVarSet *const LVSetAft )
174 // Now find the LR of the return value of the call
177 // We do this because, we look at the LV set *after* the instruction
178 // to determine, which LRs must be saved across calls. The return value
179 // of the call is live in this set - but it does not interfere with call
180 // (i.e., we can allocate a volatile register to the return value)
182 LiveRange *RetValLR = NULL;
184 const Value *RetVal = MRI.getCallInstRetVal( MInst );
187 RetValLR = LRI.getLiveRangeForValue( RetVal );
188 assert( RetValLR && "No LR for RetValue of call");
192 cout << "\n For call inst: " << *MInst;
194 LiveVarSet::const_iterator LIt = LVSetAft->begin();
196 // for each live var in live variable set after machine inst
197 for( ; LIt != LVSetAft->end(); ++LIt) {
199 // get the live range corresponding to live var
200 LiveRange *const LR = LRI.getLiveRangeForValue(*LIt );
202 if( LR && DEBUG_RA) {
203 cout << "\n\tLR Aft Call: ";
208 // LR can be null if it is a const since a const
209 // doesn't have a dominating def - see Assumptions above
210 if( LR && (LR != RetValLR) ) {
211 LR->setCallInterference();
213 cout << "\n ++Added call interf for LR: " ;
223 //----------------------------------------------------------------------------
224 // This method will walk thru code and create interferences in the IG of
226 //----------------------------------------------------------------------------
228 void PhyRegAlloc::buildInterferenceGraphs()
231 if(DEBUG_RA) cout << "Creating interference graphs ..." << endl;
233 Method::const_iterator BBI = Meth->begin(); // random iterator for BBs
235 for( ; BBI != Meth->end(); ++BBI) { // traverse BBs in random order
237 // get the iterator for machine instructions
238 const MachineCodeForBasicBlock& MIVec = (*BBI)->getMachineInstrVec();
239 MachineCodeForBasicBlock::const_iterator
240 MInstIterator = MIVec.begin();
242 // iterate over all the machine instructions in BB
243 for( ; MInstIterator != MIVec.end(); ++MInstIterator) {
245 const MachineInstr * MInst = *MInstIterator;
247 // get the LV set after the instruction
248 const LiveVarSet *const LVSetAI =
249 LVI->getLiveVarSetAfterMInst(MInst, *BBI);
251 const bool isCallInst = TM.getInstrInfo().isCall(MInst->getOpCode());
254 //cout << "\nFor call inst: " << *MInst;
256 // set the isCallInterference flag of each live range wich extends
257 // accross this call instruction. This information is used by graph
258 // coloring algo to avoid allocating volatile colors to live ranges
259 // that span across calls (since they have to be saved/restored)
260 setCallInterferences( MInst, LVSetAI);
264 // iterate over MI operands to find defs
265 for( MachineInstr::val_op_const_iterator OpI(MInst);!OpI.done(); ++OpI) {
268 // create a new LR iff this operand is a def
269 addInterference(*OpI, LVSetAI, isCallInst );
271 } // for all operands
274 // if there are multiple defs in this instruction e.g. in SETX
276 if( (TM.getInstrInfo()).isPseudoInstr( MInst->getOpCode()) )
277 addInterf4PseudoInstr(MInst);
280 // Also add interference for any implicit definitions in a machine
281 // instr (currently, only calls have this).
283 unsigned NumOfImpRefs = MInst->getNumImplicitRefs();
284 if( NumOfImpRefs > 0 ) {
285 for(unsigned z=0; z < NumOfImpRefs; z++)
286 if( MInst->implicitRefIsDefined(z) )
287 addInterference( MInst->getImplicitRef(z), LVSetAI, isCallInst );
291 // record phi instrns in PhiInstList
292 if( TM.getInstrInfo().isDummyPhiInstr(MInst->getOpCode()) )
293 PhiInstList.push_back( MInst );
296 } // for all machine instructions in BB
298 } // for all BBs in method
301 // add interferences for method arguments. Since there are no explict
302 // defs in method for args, we have to add them manually
304 addInterferencesForArgs(); // add interference for method args
307 cout << "Interference graphs calculted!" << endl;
311 //--------------------------------------------------------------------------
312 // Pseudo instructions will be exapnded to multiple instructions by the
313 // assembler. Consequently, all the opernds must get distinct registers
314 //--------------------------------------------------------------------------
316 void PhyRegAlloc::addInterf4PseudoInstr(const MachineInstr *MInst) {
318 // iterate over MI operands to find defs
319 for( MachineInstr::val_op_const_iterator It1(MInst);!It1.done(); ++It1) {
321 const LiveRange *const LROfOp1 = LRI.getLiveRangeForValue( *It1 );
323 if( !LROfOp1 ) continue;
325 MachineInstr::val_op_const_iterator It2 = It1;
328 for( ; !It2.done(); ++It2) {
330 const LiveRange *const LROfOp2 = LRI.getLiveRangeForValue( *It2 );
334 RegClass *const RCOfOp1 = LROfOp1->getRegClass();
335 RegClass *const RCOfOp2 = LROfOp2->getRegClass();
337 if( RCOfOp1 == RCOfOp2 ){
338 RCOfOp1->setInterference( LROfOp1, LROfOp2 );
339 //cerr << "\nSet interfs for PSEUDO inst: " << *MInst;
344 } // for all other defs in machine instr
346 } // for all operands in an instruction
354 //----------------------------------------------------------------------------
355 // This method will add interferences for incoming arguments to a method.
356 //----------------------------------------------------------------------------
357 void PhyRegAlloc::addInterferencesForArgs()
359 // get the InSet of root BB
360 const LiveVarSet *const InSet = LVI->getInSetOfBB( Meth->front() );
362 // get the argument list
363 const Method::ArgumentListType& ArgList = Meth->getArgumentList();
365 // get an iterator to arg list
366 Method::ArgumentListType::const_iterator ArgIt = ArgList.begin();
369 for( ; ArgIt != ArgList.end() ; ++ArgIt) { // for each argument
370 addInterference( *ArgIt, InSet, false ); // add interferences between
371 // args and LVars at start
373 cout << " - %% adding interference for argument ";
374 printValue( (const Value *) *ArgIt); cout << endl;
380 //----------------------------------------------------------------------------
381 // This method is called after register allocation is complete to set the
382 // allocated reisters in the machine code. This code will add register numbers
383 // to MachineOperands that contain a Value.
384 //----------------------------------------------------------------------------
386 void PhyRegAlloc::updateMachineCode()
389 Method::const_iterator BBI = Meth->begin(); // random iterator for BBs
391 for( ; BBI != Meth->end(); ++BBI) { // traverse BBs in random order
393 // get the iterator for machine instructions
394 MachineCodeForBasicBlock& MIVec = (*BBI)->getMachineInstrVec();
395 MachineCodeForBasicBlock::iterator MInstIterator = MIVec.begin();
397 // iterate over all the machine instructions in BB
398 for( ; MInstIterator != MIVec.end(); ++MInstIterator) {
400 MachineInstr *MInst = *MInstIterator;
402 // do not process Phis
403 if( (TM.getInstrInfo()).isPhi( MInst->getOpCode()) )
407 // if this machine instr is call, insert caller saving code
409 if( (TM.getInstrInfo()).isCall( MInst->getOpCode()) )
410 MRI.insertCallerSavingCode(MInst, *BBI, *this );
413 // reset the stack offset for temporary variables since we may
414 // need that to spill
415 mcInfo.popAllTempValues(TM);
417 //for(MachineInstr::val_op_const_iterator OpI(MInst);!OpI.done();++OpI) {
420 // Now replace set the registers for operands in the machine instruction
422 for(unsigned OpNum=0; OpNum < MInst->getNumOperands(); ++OpNum) {
424 MachineOperand& Op = MInst->getOperand(OpNum);
426 if( Op.getOperandType() == MachineOperand::MO_VirtualRegister ||
427 Op.getOperandType() == MachineOperand::MO_CCRegister) {
429 const Value *const Val = Op.getVRegValue();
431 // delete this condition checking later (must assert if Val is null)
434 cout << "Warning: NULL Value found for operand" << endl;
437 assert( Val && "Value is NULL");
439 LiveRange *const LR = LRI.getLiveRangeForValue(Val);
443 // nothing to worry if it's a const or a label
446 cout << "*NO LR for operand : " << Op ;
447 cout << " [reg:" << Op.getAllocatedRegNum() << "]";
448 cout << " in inst:\t" << *MInst << endl;
451 // if register is not allocated, mark register as invalid
452 if( Op.getAllocatedRegNum() == -1)
453 Op.setRegForValue( MRI.getInvalidRegNum());
459 unsigned RCID = (LR->getRegClass())->getID();
461 if( LR->hasColor() ) {
462 Op.setRegForValue( MRI.getUnifiedRegNum(RCID, LR->getColor()) );
466 // LR did NOT receive a color (register). Now, insert spill code
467 // for spilled opeands in this machine instruction
469 //assert(0 && "LR must be spilled");
470 insertCode4SpilledLR(LR, MInst, *BBI, OpNum );
475 } // for each operand
478 // If there are instructions to be added, *before* this machine
479 // instruction, add them now.
481 if( AddedInstrMap[ MInst ] ) {
483 deque<MachineInstr *> &IBef = (AddedInstrMap[MInst])->InstrnsBefore;
485 if( ! IBef.empty() ) {
487 deque<MachineInstr *>::iterator AdIt;
489 for( AdIt = IBef.begin(); AdIt != IBef.end() ; ++AdIt ) {
492 cerr << "For inst " << *MInst;
493 cerr << " PREPENDed instr: " << **AdIt << endl;
496 MInstIterator = MIVec.insert( MInstIterator, *AdIt );
504 // If there are instructions to be added *after* this machine
505 // instruction, add them now
507 if( AddedInstrMap[ MInst ] &&
508 ! (AddedInstrMap[ MInst ]->InstrnsAfter).empty() ) {
510 // if there are delay slots for this instruction, the instructions
511 // added after it must really go after the delayed instruction(s)
512 // So, we move the InstrAfter of the current instruction to the
513 // corresponding delayed instruction
516 if((delay=TM.getInstrInfo().getNumDelaySlots(MInst->getOpCode())) >0){
517 move2DelayedInstr(MInst, *(MInstIterator+delay) );
519 if(DEBUG_RA) cout<< "\nMoved an added instr after the delay slot";
525 // Here we can add the "instructions after" to the current
526 // instruction since there are no delay slots for this instruction
528 deque<MachineInstr *> &IAft = (AddedInstrMap[MInst])->InstrnsAfter;
530 if( ! IAft.empty() ) {
532 deque<MachineInstr *>::iterator AdIt;
534 ++MInstIterator; // advance to the next instruction
536 for( AdIt = IAft.begin(); AdIt != IAft.end() ; ++AdIt ) {
539 cerr << "For inst " << *MInst;
540 cerr << " APPENDed instr: " << **AdIt << endl;
543 MInstIterator = MIVec.insert( MInstIterator, *AdIt );
547 // MInsterator already points to the next instr. Since the
548 // for loop also increments it, decrement it to point to the
549 // instruction added last
558 } // for each machine instruction
564 //----------------------------------------------------------------------------
565 // This method inserts spill code for AN operand whose LR was spilled.
566 // This method may be called several times for a single machine instruction
567 // if it contains many spilled operands. Each time it is called, it finds
568 // a register which is not live at that instruction and also which is not
569 // used by other spilled operands of the same instruction. Then it uses
570 // this register temporarily to accomodate the spilled value.
571 //----------------------------------------------------------------------------
572 void PhyRegAlloc::insertCode4SpilledLR(const LiveRange *LR,
574 const BasicBlock *BB,
575 const unsigned OpNum) {
577 MachineOperand& Op = MInst->getOperand(OpNum);
578 bool isDef = MInst->operandIsDefined(OpNum);
579 unsigned RegType = MRI.getRegType( LR );
580 int SpillOff = LR->getSpillOffFromFP();
581 RegClass *RC = LR->getRegClass();
582 const LiveVarSet *LVSetBef = LVI->getLiveVarSetBeforeMInst(MInst, BB);
584 /**** NOTE: THIS SHOULD USE THE RIGHT SIZE FOR THE REG BEING PUSHED ****/
586 mcInfo.pushTempValue(TM, 8 /* TM.findOptimalStorageSize(LR->getType()) */);
588 MachineInstr *MIBef=NULL, *AdIMid=NULL, *MIAft=NULL;
591 TmpReg = getUsableRegAtMI(RC, RegType, MInst,LVSetBef, MIBef, MIAft);
592 TmpReg = MRI.getUnifiedRegNum( RC->getID(), TmpReg );
595 // get the added instructions for this instruciton
596 AddedInstrns *AI = AddedInstrMap[ MInst ];
598 AI = new AddedInstrns();
599 AddedInstrMap[ MInst ] = AI;
606 // for a USE, we have to load the value of LR from stack to a TmpReg
607 // and use the TmpReg as one operand of instruction
609 // actual loading instruction
610 AdIMid = MRI.cpMem2RegMI(MRI.getFramePointer(), SpillOff, TmpReg, RegType);
613 (AI->InstrnsBefore).push_back(MIBef);
615 (AI->InstrnsBefore).push_back(AdIMid);
618 (AI->InstrnsAfter).push_front(MIAft);
622 else { // if this is a Def
624 // for a DEF, we have to store the value produced by this instruction
625 // on the stack position allocated for this LR
627 // actual storing instruction
628 AdIMid = MRI.cpReg2MemMI(TmpReg, MRI.getFramePointer(), SpillOff, RegType);
631 (AI->InstrnsBefore).push_back(MIBef);
633 (AI->InstrnsAfter).push_front(AdIMid);
636 (AI->InstrnsAfter).push_front(MIAft);
640 cerr << "\nFor Inst " << *MInst;
641 cerr << " - SPILLED LR: "; LR->printSet();
642 cerr << "\n - Added Instructions:";
643 if( MIBef ) cerr << *MIBef;
645 if( MIAft ) cerr << *MIAft;
647 Op.setRegForValue( TmpReg ); // set the opearnd
657 //----------------------------------------------------------------------------
658 // We can use the following method to get a temporary register to be used
659 // BEFORE any given machine instruction. If there is a register available,
660 // this method will simply return that register and set MIBef = MIAft = NULL.
661 // Otherwise, it will return a register and MIAft and MIBef will contain
662 // two instructions used to free up this returned register.
663 // Returned register number is the UNIFIED register number
664 //----------------------------------------------------------------------------
666 int PhyRegAlloc::getUsableRegAtMI(RegClass *RC,
668 const MachineInstr *MInst,
669 const LiveVarSet *LVSetBef,
671 MachineInstr *MIAft) {
673 int Reg = getUnusedRegAtMI(RC, MInst, LVSetBef);
674 Reg = MRI.getUnifiedRegNum(RC->getID(), Reg);
677 // we found an unused register, so we can simply used
678 MIBef = MIAft = NULL;
681 // we couldn't find an unused register. Generate code to free up a reg by
682 // saving it on stack and restoring after the instruction
684 /**** NOTE: THIS SHOULD USE THE RIGHT SIZE FOR THE REG BEING PUSHED ****/
685 int TmpOff = mcInfo.pushTempValue(TM, /*size*/ 8);
687 Reg = getRegNotUsedByThisInst(RC, MInst);
688 MIBef = MRI.cpReg2MemMI(Reg, MRI.getFramePointer(), TmpOff, RegType );
689 MIAft = MRI.cpMem2RegMI(MRI.getFramePointer(), TmpOff, Reg, RegType );
695 //----------------------------------------------------------------------------
696 // This method is called to get a new unused register that can be used to
697 // accomodate a spilled value.
698 // This method may be called several times for a single machine instruction
699 // if it contains many spilled operands. Each time it is called, it finds
700 // a register which is not live at that instruction and also which is not
701 // used by other spilled operands of the same instruction.
702 // Return register number is relative to the register class. NOT
704 //----------------------------------------------------------------------------
705 int PhyRegAlloc::getUnusedRegAtMI(RegClass *RC,
706 const MachineInstr *MInst,
707 const LiveVarSet *LVSetBef) {
709 unsigned NumAvailRegs = RC->getNumOfAvailRegs();
711 bool *IsColorUsedArr = RC->getIsColorUsedArr();
713 for(unsigned i=0; i < NumAvailRegs; i++)
714 IsColorUsedArr[i] = false;
716 LiveVarSet::const_iterator LIt = LVSetBef->begin();
718 // for each live var in live variable set after machine inst
719 for( ; LIt != LVSetBef->end(); ++LIt) {
721 // get the live range corresponding to live var
722 LiveRange *const LRofLV = LRI.getLiveRangeForValue(*LIt );
724 // LR can be null if it is a const since a const
725 // doesn't have a dominating def - see Assumptions above
727 if( LRofLV->hasColor() )
728 IsColorUsedArr[ LRofLV->getColor() ] = true;
731 // It is possible that one operand of this MInst was already spilled
732 // and it received some register temporarily. If that's the case,
733 // it is recorded in machine operand. We must skip such registers.
735 setRegsUsedByThisInst(RC, MInst);
737 unsigned c; // find first unused color
738 for( c=0; c < NumAvailRegs; c++)
739 if( ! IsColorUsedArr[ c ] ) break;
751 //----------------------------------------------------------------------------
752 // This method modifies the IsColorUsedArr of the register class passed to it.
753 // It sets the bits corresponding to the registers used by this machine
754 // instructions. Explicit operands are set.
755 //----------------------------------------------------------------------------
756 void PhyRegAlloc::setRegsUsedByThisInst(RegClass *RC,
757 const MachineInstr *MInst ) {
759 bool *IsColorUsedArr = RC->getIsColorUsedArr();
761 for(unsigned OpNum=0; OpNum < MInst->getNumOperands(); ++OpNum) {
763 const MachineOperand& Op = MInst->getOperand(OpNum);
765 if( Op.getOperandType() == MachineOperand::MO_VirtualRegister ||
766 Op.getOperandType() == MachineOperand::MO_CCRegister) {
768 const Value *const Val = Op.getVRegValue();
771 if( MRI.getRegClassIDOfValue( Val )== RC->getID() ) {
773 if( (Reg=Op.getAllocatedRegNum()) != -1)
774 IsColorUsedArr[ Reg ] = true;
780 // If there are implicit references, mark them as well
782 for(unsigned z=0; z < MInst->getNumImplicitRefs(); z++) {
784 LiveRange *const LRofImpRef =
785 LRI.getLiveRangeForValue( MInst->getImplicitRef(z) );
788 if( LRofImpRef->hasColor() )
789 IsColorUsedArr[ LRofImpRef->getColor() ] = true;
798 //----------------------------------------------------------------------------
799 // Get any other register in a register class, other than what is used
800 // by operands of a machine instruction.
801 //----------------------------------------------------------------------------
802 int PhyRegAlloc::getRegNotUsedByThisInst(RegClass *RC,
803 const MachineInstr *MInst) {
805 bool *IsColorUsedArr = RC->getIsColorUsedArr();
806 unsigned NumAvailRegs = RC->getNumOfAvailRegs();
809 for(unsigned i=0; i < NumAvailRegs ; i++)
810 IsColorUsedArr[i] = false;
812 setRegsUsedByThisInst(RC, MInst);
814 unsigned c; // find first unused color
815 for( c=0; c < RC->getNumOfAvailRegs(); c++)
816 if( ! IsColorUsedArr[ c ] ) break;
821 assert( 0 && "FATAL: No free register could be found in reg class!!");
829 //----------------------------------------------------------------------------
830 // If there are delay slots for an instruction, the instructions
831 // added after it must really go after the delayed instruction(s).
832 // So, we move the InstrAfter of that instruction to the
833 // corresponding delayed instruction using the following method.
835 //----------------------------------------------------------------------------
836 void PhyRegAlloc:: move2DelayedInstr(const MachineInstr *OrigMI,
837 const MachineInstr *DelayedMI) {
840 // "added after" instructions of the original instr
841 deque<MachineInstr *> &OrigAft = (AddedInstrMap[OrigMI])->InstrnsAfter;
843 // "added instructions" of the delayed instr
844 AddedInstrns *DelayAdI = AddedInstrMap[DelayedMI];
846 if(! DelayAdI ) { // create a new "added after" if necessary
847 DelayAdI = new AddedInstrns();
848 AddedInstrMap[DelayedMI] = DelayAdI;
851 // "added after" instructions of the delayed instr
852 deque<MachineInstr *> &DelayedAft = DelayAdI->InstrnsAfter;
854 // go thru all the "added after instructions" of the original instruction
855 // and append them to the "addded after instructions" of the delayed
858 deque<MachineInstr *>::iterator OrigAdIt;
860 for( OrigAdIt = OrigAft.begin(); OrigAdIt != OrigAft.end() ; ++OrigAdIt ) {
861 DelayedAft.push_back( *OrigAdIt );
864 // empty the "added after instructions" of the original instruction
869 //----------------------------------------------------------------------------
870 // This method prints the code with registers after register allocation is
872 //----------------------------------------------------------------------------
873 void PhyRegAlloc::printMachineCode()
876 cout << endl << ";************** Method ";
877 cout << Meth->getName() << " *****************" << endl;
879 Method::const_iterator BBI = Meth->begin(); // random iterator for BBs
881 for( ; BBI != Meth->end(); ++BBI) { // traverse BBs in random order
883 cout << endl ; printLabel( *BBI); cout << ": ";
885 // get the iterator for machine instructions
886 MachineCodeForBasicBlock& MIVec = (*BBI)->getMachineInstrVec();
887 MachineCodeForBasicBlock::iterator MInstIterator = MIVec.begin();
889 // iterate over all the machine instructions in BB
890 for( ; MInstIterator != MIVec.end(); ++MInstIterator) {
892 MachineInstr *const MInst = *MInstIterator;
895 cout << endl << "\t";
896 cout << TargetInstrDescriptors[MInst->getOpCode()].opCodeString;
899 //for(MachineInstr::val_op_const_iterator OpI(MInst);!OpI.done();++OpI) {
901 for(unsigned OpNum=0; OpNum < MInst->getNumOperands(); ++OpNum) {
903 MachineOperand& Op = MInst->getOperand(OpNum);
905 if( Op.getOperandType() == MachineOperand::MO_VirtualRegister ||
906 Op.getOperandType() == MachineOperand::MO_CCRegister /*||
907 Op.getOperandType() == MachineOperand::MO_PCRelativeDisp*/ ) {
909 const Value *const Val = Op.getVRegValue () ;
910 // ****this code is temporary till NULL Values are fixed
912 cout << "\t<*NULL*>";
916 // if a label or a constant
917 if( (Val->getValueType() == Value::BasicBlockVal) ) {
919 cout << "\t"; printLabel( Op.getVRegValue () );
922 // else it must be a register value
923 const int RegNum = Op.getAllocatedRegNum();
925 cout << "\t" << "%" << MRI.getUnifiedRegName( RegNum );
929 else if(Op.getOperandType() == MachineOperand::MO_MachineRegister) {
930 cout << "\t" << "%" << MRI.getUnifiedRegName(Op.getMachineRegNum());
934 cout << "\t" << Op; // use dump field
939 unsigned NumOfImpRefs = MInst->getNumImplicitRefs();
940 if( NumOfImpRefs > 0 ) {
942 cout << "\tImplicit:";
944 for(unsigned z=0; z < NumOfImpRefs; z++) {
945 printValue( MInst->getImplicitRef(z) );
951 } // for all machine instructions
962 //----------------------------------------------------------------------------
964 //----------------------------------------------------------------------------
966 void PhyRegAlloc::colorCallRetArgs()
969 CallRetInstrListType &CallRetInstList = LRI.getCallRetInstrList();
970 CallRetInstrListType::const_iterator It = CallRetInstList.begin();
972 for( ; It != CallRetInstList.end(); ++It ) {
974 const MachineInstr *const CRMI = *It;
975 unsigned OpCode = CRMI->getOpCode();
977 // get the added instructions for this Call/Ret instruciton
978 AddedInstrns *AI = AddedInstrMap[ CRMI ];
980 AI = new AddedInstrns();
981 AddedInstrMap[ CRMI ] = AI;
984 // Tmp stack poistions are needed by some calls that have spilled args
985 // So reset it before we call each such method
986 mcInfo.popAllTempValues(TM);
988 if( (TM.getInstrInfo()).isCall( OpCode ) )
989 MRI.colorCallArgs( CRMI, LRI, AI, *this );
991 else if ( (TM.getInstrInfo()).isReturn(OpCode) )
992 MRI.colorRetValue( CRMI, LRI, AI );
994 else assert( 0 && "Non Call/Ret instrn in CallRetInstrList\n" );
1002 //----------------------------------------------------------------------------
1004 //----------------------------------------------------------------------------
1005 void PhyRegAlloc::colorIncomingArgs()
1007 const BasicBlock *const FirstBB = Meth->front();
1008 const MachineInstr *FirstMI = *((FirstBB->getMachineInstrVec()).begin());
1009 assert( FirstMI && "No machine instruction in entry BB");
1011 AddedInstrns *AI = AddedInstrMap[ FirstMI ];
1013 AI = new AddedInstrns();
1014 AddedInstrMap[ FirstMI ] = AI;
1017 MRI.colorMethodArgs(Meth, LRI, AI );
1021 //----------------------------------------------------------------------------
1022 // Used to generate a label for a basic block
1023 //----------------------------------------------------------------------------
1024 void PhyRegAlloc::printLabel(const Value *const Val)
1026 if( Val->hasName() )
1027 cout << Val->getName();
1029 cout << "Label" << Val;
1033 //----------------------------------------------------------------------------
1034 // This method calls setSugColorUsable method of each live range. This
1035 // will determine whether the suggested color of LR is really usable.
1036 // A suggested color is not usable when the suggested color is volatile
1037 // AND when there are call interferences
1038 //----------------------------------------------------------------------------
1040 void PhyRegAlloc::markUnusableSugColors()
1042 if(DEBUG_RA ) cout << "\nmarking unusable suggested colors ..." << endl;
1044 // hash map iterator
1045 LiveRangeMapType::const_iterator HMI = (LRI.getLiveRangeMap())->begin();
1046 LiveRangeMapType::const_iterator HMIEnd = (LRI.getLiveRangeMap())->end();
1048 for( ; HMI != HMIEnd ; ++HMI ) {
1050 if( (*HMI).first ) {
1052 LiveRange *L = (*HMI).second; // get the LiveRange
1055 if( L->hasSuggestedColor() ) {
1057 int RCID = (L->getRegClass())->getID();
1058 if( MRI.isRegVolatile( RCID, L->getSuggestedColor()) &&
1059 L->isCallInterference() )
1060 L->setSuggestedColorUsable( false );
1062 L->setSuggestedColorUsable( true );
1064 } // if L->hasSuggestedColor()
1066 } // for all LR's in hash map
1071 //----------------------------------------------------------------------------
1072 // The following method will set the stack offsets of the live ranges that
1073 // are decided to be spillled. This must be called just after coloring the
1074 // LRs using the graph coloring algo. For each live range that is spilled,
1075 // this method allocate a new spill position on the stack.
1076 //----------------------------------------------------------------------------
1078 void PhyRegAlloc::allocateStackSpace4SpilledLRs()
1080 if(DEBUG_RA ) cout << "\nsetting LR stack offsets ..." << endl;
1082 // hash map iterator
1083 LiveRangeMapType::const_iterator HMI = (LRI.getLiveRangeMap())->begin();
1084 LiveRangeMapType::const_iterator HMIEnd = (LRI.getLiveRangeMap())->end();
1086 for( ; HMI != HMIEnd ; ++HMI ) {
1087 if( (*HMI).first ) {
1088 LiveRange *L = (*HMI).second; // get the LiveRange
1090 if( ! L->hasColor() )
1091 /**** NOTE: THIS SHOULD USE THE RIGHT SIZE FOR THE REG BEING PUSHED ****/
1092 L->setSpillOffFromFP(mcInfo.allocateSpilledValue(TM, Type::LongTy /*L->getType()*/ ));
1094 } // for all LR's in hash map
1099 //----------------------------------------------------------------------------
1100 // The entry pont to Register Allocation
1101 //----------------------------------------------------------------------------
1103 void PhyRegAlloc::allocateRegisters()
1106 // make sure that we put all register classes into the RegClassList
1107 // before we call constructLiveRanges (now done in the constructor of
1108 // PhyRegAlloc class).
1110 constructLiveRanges(); // create LR info
1113 LRI.printLiveRanges();
1115 createIGNodeListsAndIGs(); // create IGNode list and IGs
1117 buildInterferenceGraphs(); // build IGs in all reg classes
1121 // print all LRs in all reg classes
1122 for( unsigned int rc=0; rc < NumOfRegClasses ; rc++)
1123 RegClassList[ rc ]->printIGNodeList();
1125 // print IGs in all register classes
1126 for( unsigned int rc=0; rc < NumOfRegClasses ; rc++)
1127 RegClassList[ rc ]->printIG();
1130 LRI.coalesceLRs(); // coalesce all live ranges
1132 // coalscing could not get rid of all phi's, add phi elimination
1134 // insertPhiEleminateInstrns();
1137 // print all LRs in all reg classes
1138 for( unsigned int rc=0; rc < NumOfRegClasses ; rc++)
1139 RegClassList[ rc ]->printIGNodeList();
1141 // print IGs in all register classes
1142 for( unsigned int rc=0; rc < NumOfRegClasses ; rc++)
1143 RegClassList[ rc ]->printIG();
1147 // mark un-usable suggested color before graph coloring algorithm.
1148 // When this is done, the graph coloring algo will not reserve
1149 // suggested color unnecessarily - they can be used by another LR
1150 markUnusableSugColors();
1152 // color all register classes using the graph coloring algo
1153 for( unsigned int rc=0; rc < NumOfRegClasses ; rc++)
1154 RegClassList[ rc ]->colorAllRegs();
1156 // Atter grpah coloring, if some LRs did not receive a color (i.e, spilled)
1157 // a poistion for such spilled LRs
1158 allocateStackSpace4SpilledLRs();
1160 // color incoming args and call args
1161 colorIncomingArgs();
1165 updateMachineCode();
1167 MachineCodeForMethod::get(Meth).dump();
1168 printMachineCode(); // only for DEBUGGING