1 #include "llvm/CodeGen/PhyRegAlloc.h"
3 cl::Enum<RegAllocDebugLevel_t> DEBUG_RA("dregalloc", cl::NoFlags,
4 "enable register allocation debugging information",
5 clEnumValN(RA_DEBUG_None , "n", "disable debug output"),
6 clEnumValN(RA_DEBUG_Normal , "y", "enable debug output"),
7 clEnumValN(RA_DEBUG_Verbose, "v", "enable extra debug output"), 0);
10 //----------------------------------------------------------------------------
11 // Constructor: Init local composite objects and create register classes.
12 //----------------------------------------------------------------------------
13 PhyRegAlloc::PhyRegAlloc(const Method *const M,
14 const TargetMachine& tm,
15 MethodLiveVarInfo *const Lvi)
17 Meth(M), TM(tm), LVI(Lvi), LRI(M, tm, RegClassList),
18 MRI( tm.getRegInfo() ),
19 NumOfRegClasses(MRI.getNumOfRegClasses()),
23 // **TODO: use an actual reserved color list
24 ReservedColorListType *RCL = new ReservedColorListType();
26 // create each RegisterClass and put in RegClassList
27 for( unsigned int rc=0; rc < NumOfRegClasses; rc++)
28 RegClassList.push_back( new RegClass(M, MRI.getMachineRegClass(rc), RCL) );
32 //----------------------------------------------------------------------------
33 // This method initally creates interference graphs (one in each reg class)
34 // and IGNodeList (one in each IG). The actual nodes will be pushed later.
35 //----------------------------------------------------------------------------
37 void PhyRegAlloc::createIGNodeListsAndIGs()
39 if(DEBUG_RA ) cout << "Creating LR lists ..." << endl;
42 LiveRangeMapType::const_iterator HMI = (LRI.getLiveRangeMap())->begin();
45 LiveRangeMapType::const_iterator HMIEnd = (LRI.getLiveRangeMap())->end();
47 for( ; HMI != HMIEnd ; ++HMI ) {
51 LiveRange *L = (*HMI).second; // get the LiveRange
55 cout << "\n*?!?Warning: Null liver range found for: ";
56 printValue( (*HMI).first) ; cout << endl;
60 // if the Value * is not null, and LR
61 // is not yet written to the IGNodeList
62 if( !(L->getUserIGNode()) ) {
64 RegClass *const RC = // RegClass of first value in the LR
65 //RegClassList [MRI.getRegClassIDOfValue(*(L->begin()))];
66 RegClassList[ L->getRegClass()->getID() ];
68 RC-> addLRToIG( L ); // add this LR to an IG
74 for( unsigned int rc=0; rc < NumOfRegClasses ; rc++)
75 RegClassList[ rc ]->createInterferenceGraph();
78 cout << "LRLists Created!" << endl;
83 //----------------------------------------------------------------------------
84 // This method will add all interferences at for a given instruction.
85 // Interence occurs only if the LR of Def (Inst or Arg) is of the same reg
86 // class as that of live var. The live var passed to this function is the
87 // LVset AFTER the instruction
88 //----------------------------------------------------------------------------
90 void PhyRegAlloc::addInterference(const Value *const Def,
91 const LiveVarSet *const LVSet,
92 const bool isCallInst) {
94 LiveVarSet::const_iterator LIt = LVSet->begin();
96 // get the live range of instruction
97 const LiveRange *const LROfDef = LRI.getLiveRangeForValue( Def );
99 IGNode *const IGNodeOfDef = LROfDef->getUserIGNode();
100 assert( IGNodeOfDef );
102 RegClass *const RCOfDef = LROfDef->getRegClass();
104 // for each live var in live variable set
105 for( ; LIt != LVSet->end(); ++LIt) {
108 cout << "< Def="; printValue(Def);
109 cout << ", Lvar="; printValue( *LIt); cout << "> ";
112 // get the live range corresponding to live var
113 LiveRange *const LROfVar = LRI.getLiveRangeForValue(*LIt );
115 // LROfVar can be null if it is a const since a const
116 // doesn't have a dominating def - see Assumptions above
119 if(LROfDef == LROfVar) // do not set interf for same LR
122 // if 2 reg classes are the same set interference
123 if( RCOfDef == LROfVar->getRegClass() ){
124 RCOfDef->setInterference( LROfDef, LROfVar);
128 else if(DEBUG_RA > 1) {
129 // we will not have LRs for values not explicitly allocated in the
130 // instruction stream (e.g., constants)
131 cout << " warning: no live range for " ;
132 printValue( *LIt); cout << endl; }
141 //----------------------------------------------------------------------------
142 // For a call instruction, this method sets the CallInterference flag in
143 // the LR of each variable live int the Live Variable Set live after the
144 // call instruction (except the return value of the call instruction - since
145 // the return value does not interfere with that call itself).
146 //----------------------------------------------------------------------------
148 void PhyRegAlloc::setCallInterferences(const MachineInstr *MInst,
149 const LiveVarSet *const LVSetAft )
151 // Now find the LR of the return value of the call
154 // We do this because, we look at the LV set *after* the instruction
155 // to determine, which LRs must be saved across calls. The return value
156 // of the call is live in this set - but it does not interfere with call
157 // (i.e., we can allocate a volatile register to the return value)
159 LiveRange *RetValLR = NULL;
161 const Value *RetVal = MRI.getCallInstRetVal( MInst );
164 RetValLR = LRI.getLiveRangeForValue( RetVal );
165 assert( RetValLR && "No LR for RetValue of call");
169 cout << "\n For call inst: " << *MInst;
171 LiveVarSet::const_iterator LIt = LVSetAft->begin();
173 // for each live var in live variable set after machine inst
174 for( ; LIt != LVSetAft->end(); ++LIt) {
176 // get the live range corresponding to live var
177 LiveRange *const LR = LRI.getLiveRangeForValue(*LIt );
179 if( LR && DEBUG_RA) {
180 cout << "\n\tLR Aft Call: ";
185 // LR can be null if it is a const since a const
186 // doesn't have a dominating def - see Assumptions above
187 if( LR && (LR != RetValLR) ) {
188 LR->setCallInterference();
190 cout << "\n ++Added call interf for LR: " ;
200 //----------------------------------------------------------------------------
201 // This method will walk thru code and create interferences in the IG of
203 //----------------------------------------------------------------------------
205 void PhyRegAlloc::buildInterferenceGraphs()
208 if(DEBUG_RA) cout << "Creating interference graphs ..." << endl;
210 Method::const_iterator BBI = Meth->begin(); // random iterator for BBs
212 for( ; BBI != Meth->end(); ++BBI) { // traverse BBs in random order
214 // get the iterator for machine instructions
215 const MachineCodeForBasicBlock& MIVec = (*BBI)->getMachineInstrVec();
216 MachineCodeForBasicBlock::const_iterator
217 MInstIterator = MIVec.begin();
219 // iterate over all the machine instructions in BB
220 for( ; MInstIterator != MIVec.end(); ++MInstIterator) {
222 const MachineInstr *const MInst = *MInstIterator;
224 // get the LV set after the instruction
225 const LiveVarSet *const LVSetAI =
226 LVI->getLiveVarSetAfterMInst(MInst, *BBI);
228 const bool isCallInst = TM.getInstrInfo().isCall(MInst->getOpCode());
231 //cout << "\nFor call inst: " << *MInst;
233 // set the isCallInterference flag of each live range wich extends
234 // accross this call instruction. This information is used by graph
235 // coloring algo to avoid allocating volatile colors to live ranges
236 // that span across calls (since they have to be saved/restored)
237 setCallInterferences( MInst, LVSetAI);
241 // iterate over MI operands to find defs
242 for( MachineInstr::val_op_const_iterator OpI(MInst);!OpI.done(); ++OpI) {
245 // create a new LR iff this operand is a def
246 addInterference(*OpI, LVSetAI, isCallInst );
250 } // for all operands
253 // Also add interference for any implicit definitions in a machine
254 // instr (currently, only calls have this).
256 unsigned NumOfImpRefs = MInst->getNumImplicitRefs();
257 if( NumOfImpRefs > 0 ) {
258 for(unsigned z=0; z < NumOfImpRefs; z++)
259 if( MInst->implicitRefIsDefined(z) )
260 addInterference( MInst->getImplicitRef(z), LVSetAI, isCallInst );
263 } // for all machine instructions in BB
268 // go thru LLVM instructions in the basic block and record all CALL
269 // instructions and Return instructions in the CallInstrList
270 // This is done because since there are no reverse pointers in machine
271 // instructions to find the llvm instruction, when we encounter a call
272 // or a return whose args must be specailly colored (e.g., %o's for args)
273 BasicBlock::const_iterator InstIt = (*BBI)->begin();
275 for( ; InstIt != (*BBI)->end() ; ++ InstIt) {
276 unsigned OpCode = (*InstIt)->getOpcode();
278 if( OpCode == Instruction::Call )
279 CallInstrList.push_back( *InstIt );
281 else if( OpCode == Instruction::Ret )
282 RetInstrList.push_back( *InstIt );
288 } // for all BBs in method
291 // add interferences for method arguments. Since there are no explict
292 // defs in method for args, we have to add them manually
294 addInterferencesForArgs(); // add interference for method args
297 cout << "Interference graphs calculted!" << endl;
304 //----------------------------------------------------------------------------
305 // This method will add interferences for incoming arguments to a method.
306 //----------------------------------------------------------------------------
307 void PhyRegAlloc::addInterferencesForArgs()
309 // get the InSet of root BB
310 const LiveVarSet *const InSet = LVI->getInSetOfBB( Meth->front() );
312 // get the argument list
313 const Method::ArgumentListType& ArgList = Meth->getArgumentList();
315 // get an iterator to arg list
316 Method::ArgumentListType::const_iterator ArgIt = ArgList.begin();
319 for( ; ArgIt != ArgList.end() ; ++ArgIt) { // for each argument
320 addInterference( *ArgIt, InSet, false ); // add interferences between
321 // args and LVars at start
323 cout << " - %% adding interference for argument ";
324 printValue( (const Value *) *ArgIt); cout << endl;
331 //----------------------------------------------------------------------------
332 // This method inserts caller saving/restoring instructons before/after
333 // a call machine instruction.
334 //----------------------------------------------------------------------------
337 void PhyRegAlloc::insertCallerSavingCode(const MachineInstr *MInst,
338 const BasicBlock *BB )
340 // assert( (TM.getInstrInfo()).isCall( MInst->getOpCode() ) );
342 int StackOff = -8; // ****TODO : Change
343 hash_set<unsigned> PushedRegSet;
345 // Now find the LR of the return value of the call
346 // The last *implicit operand* is the return value of a call
347 // Insert it to to he PushedRegSet since we must not save that register
348 // and restore it after the call.
349 // We do this because, we look at the LV set *after* the instruction
350 // to determine, which LRs must be saved across calls. The return value
351 // of the call is live in this set - but we must not save/restore it.
354 const Value *RetVal = MRI.getCallInstRetVal( MInst );
358 LiveRange *RetValLR = LRI.getLiveRangeForValue( RetVal );
359 assert( RetValLR && "No LR for RetValue of call");
362 MRI.getUnifiedRegNum((RetValLR->getRegClass())->getID(),
363 RetValLR->getColor() ) );
367 const LiveVarSet *LVSetAft = LVI->getLiveVarSetAfterMInst(MInst, BB);
369 LiveVarSet::const_iterator LIt = LVSetAft->begin();
371 // for each live var in live variable set after machine inst
372 for( ; LIt != LVSetAft->end(); ++LIt) {
374 // get the live range corresponding to live var
375 LiveRange *const LR = LRI.getLiveRangeForValue(*LIt );
377 // LR can be null if it is a const since a const
378 // doesn't have a dominating def - see Assumptions above
381 if( LR->hasColor() ) {
383 unsigned RCID = (LR->getRegClass())->getID();
384 unsigned Color = LR->getColor();
386 if ( MRI.isRegVolatile(RCID, Color) ) {
388 // if the value is in both LV sets (i.e., live before and after
389 // the call machine instruction)
391 unsigned Reg = MRI.getUnifiedRegNum(RCID, Color);
393 if( PushedRegSet.find(Reg) == PushedRegSet.end() ) {
395 // if we haven't already pushed that register
397 unsigned RegType = MRI.getRegType( LR );
399 // Now get two instructions - to push on stack and pop from stack
400 // and add them to InstrnsBefore and InstrnsAfter of the
403 MachineInstr *AdIBef =
404 MRI.cpReg2MemMI(Reg, MRI.getFramePointer(), StackOff, RegType );
406 MachineInstr *AdIAft =
407 MRI.cpMem2RegMI(MRI.getFramePointer(), StackOff, Reg, RegType );
409 ((AddedInstrMap[MInst])->InstrnsBefore).push_front(AdIBef);
410 ((AddedInstrMap[MInst])->InstrnsAfter).push_back(AdIAft);
412 PushedRegSet.insert( Reg );
413 StackOff -= 8; // ****TODO: Correct ??????
416 cerr << "\nFor callee save call inst:" << *MInst;
417 cerr << "\n -inserted caller saving instrs:\n\t ";
418 cerr << *AdIBef << "\n\t" << *AdIAft ;
420 } // if not already pushed
422 } // if LR has a volatile color
426 } // if there is a LR for Var
428 } // for each value in the LV set after instruction
433 //----------------------------------------------------------------------------
434 // This method is called after register allocation is complete to set the
435 // allocated reisters in the machine code. This code will add register numbers
436 // to MachineOperands that contain a Value.
437 //----------------------------------------------------------------------------
439 void PhyRegAlloc::updateMachineCode()
442 Method::const_iterator BBI = Meth->begin(); // random iterator for BBs
444 for( ; BBI != Meth->end(); ++BBI) { // traverse BBs in random order
446 // get the iterator for machine instructions
447 MachineCodeForBasicBlock& MIVec = (*BBI)->getMachineInstrVec();
448 MachineCodeForBasicBlock::iterator MInstIterator = MIVec.begin();
450 // iterate over all the machine instructions in BB
451 for( ; MInstIterator != MIVec.end(); ++MInstIterator) {
453 MachineInstr *MInst = *MInstIterator;
455 // if this machine instr is call, insert caller saving code
457 if( (TM.getInstrInfo()).isCall( MInst->getOpCode()) )
458 insertCallerSavingCode(MInst, *BBI );
460 // If there are instructions to be added, *before* this machine
461 // instruction, add them now.
463 if( AddedInstrMap[ MInst ] ) {
465 deque<MachineInstr *> &IBef = (AddedInstrMap[MInst])->InstrnsBefore;
467 if( ! IBef.empty() ) {
469 deque<MachineInstr *>::iterator AdIt;
471 for( AdIt = IBef.begin(); AdIt != IBef.end() ; ++AdIt ) {
474 cerr << " *$* PREPENDed instr " << *AdIt << endl;
476 MInstIterator = MIVec.insert( MInstIterator, *AdIt );
486 //for(MachineInstr::val_op_const_iterator OpI(MInst);!OpI.done();++OpI) {
488 for(unsigned OpNum=0; OpNum < MInst->getNumOperands(); ++OpNum) {
490 MachineOperand& Op = MInst->getOperand(OpNum);
492 if( Op.getOperandType() == MachineOperand::MO_VirtualRegister ||
493 Op.getOperandType() == MachineOperand::MO_CCRegister) {
495 const Value *const Val = Op.getVRegValue();
497 // delete this condition checking later (must assert if Val is null)
500 cout << "Warning: NULL Value found for operand" << endl;
503 assert( Val && "Value is NULL");
505 const LiveRange *const LR = LRI.getLiveRangeForValue(Val);
509 // nothing to worry if it's a const or a label
512 cout << "*NO LR for operand : " << Op ;
513 cout << " [reg:" << Op.getAllocatedRegNum() << "]";
514 cout << " in inst:\t" << *MInst << endl;
517 // if register is not allocated, mark register as invalid
518 if( Op.getAllocatedRegNum() == -1)
519 Op.setRegForValue( MRI.getInvalidRegNum());
522 if( ((Val->getType())->isLabelType()) ||
523 (Val->getValueType() == Value::ConstantVal) )
526 // The return address is not explicitly defined within a
527 // method. So, it is not colored by usual algorithm. In that case
530 //else if (TM.getInstrInfo().isCall(MInst->getOpCode()))
531 //Op.setRegForValue( MRI.getCallAddressReg() );
533 //TM.getInstrInfo().isReturn(MInst->getOpCode())
534 else if(TM.getInstrInfo().isReturn(MInst->getOpCode()) ) {
535 if (DEBUG_RA) cout << endl << "RETURN found" << endl;
536 Op.setRegForValue( MRI.getReturnAddressReg() );
540 if (Val->getValueType() == Value::InstructionVal)
543 cout << "!Warning: No LiveRange for: ";
544 printValue( Val); cout << " Type: " << Val->getValueType();
545 cout << " RegVal=" << Op.getAllocatedRegNum() << endl;
554 unsigned RCID = (LR->getRegClass())->getID();
556 Op.setRegForValue( MRI.getUnifiedRegNum(RCID, LR->getColor()) );
558 int RegNum = MRI.getUnifiedRegNum(RCID, LR->getColor());
562 } // for each operand
565 // If there are instructions to be added *after* this machine
566 // instruction, add them now
568 if( AddedInstrMap[ MInst ] &&
569 ! (AddedInstrMap[ MInst ]->InstrnsAfter).empty() ) {
571 // if there are delay slots for this instruction, the instructions
572 // added after it must really go after the delayed instruction(s)
573 // So, we move the InstrAfter of the current instruction to the
574 // corresponding delayed instruction
577 if((delay=TM.getInstrInfo().getNumDelaySlots(MInst->getOpCode())) >0){
578 move2DelayedInstr(MInst, *(MInstIterator+delay) );
580 if(DEBUG_RA) cout<< "\nMoved an added instr after the delay slot";
586 // Here we can add the "instructions after" to the current
587 // instruction since there are no delay slots for this instruction
589 deque<MachineInstr *> &IAft = (AddedInstrMap[MInst])->InstrnsAfter;
591 if( ! IAft.empty() ) {
593 deque<MachineInstr *>::iterator AdIt;
595 ++MInstIterator; // advance to the next instruction
597 for( AdIt = IAft.begin(); AdIt != IAft.end() ; ++AdIt ) {
600 cerr << " *#* APPENDed instr opcode: " << *AdIt << endl;
602 MInstIterator = MIVec.insert( MInstIterator, *AdIt );
606 // MInsterator already points to the next instr. Since the
607 // for loop also increments it, decrement it to point to the
608 // instruction added last
617 } // for each machine instruction
622 //----------------------------------------------------------------------------
624 // If there are delay slots for an instruction, the instructions
625 // added after it must really go after the delayed instruction(s).
626 // So, we move the InstrAfter of that instruction to the
627 // corresponding delayed instruction using the following method.
629 //----------------------------------------------------------------------------
630 void PhyRegAlloc:: move2DelayedInstr(const MachineInstr *OrigMI,
631 const MachineInstr *DelayedMI) {
634 // "added after" instructions of the original instr
635 deque<MachineInstr *> &OrigAft = (AddedInstrMap[OrigMI])->InstrnsAfter;
637 // "added instructions" of the delayed instr
638 AddedInstrns *DelayAdI = AddedInstrMap[DelayedMI];
640 if(! DelayAdI ) { // create a new "added after" if necessary
641 DelayAdI = new AddedInstrns();
642 AddedInstrMap[DelayedMI] = DelayAdI;
645 // "added after" instructions of the delayed instr
646 deque<MachineInstr *> &DelayedAft = DelayAdI->InstrnsAfter;
648 // go thru all the "added after instructions" of the original instruction
649 // and append them to the "addded after instructions" of the delayed
652 deque<MachineInstr *>::iterator OrigAdIt;
654 for( OrigAdIt = OrigAft.begin(); OrigAdIt != OrigAft.end() ; ++OrigAdIt ) {
655 DelayedAft.push_back( *OrigAdIt );
658 // empty the "added after instructions" of the original instruction
663 //----------------------------------------------------------------------------
664 // This method prints the code with registers after register allocation is
666 //----------------------------------------------------------------------------
667 void PhyRegAlloc::printMachineCode()
670 cout << endl << ";************** Method ";
671 cout << Meth->getName() << " *****************" << endl;
673 Method::const_iterator BBI = Meth->begin(); // random iterator for BBs
675 for( ; BBI != Meth->end(); ++BBI) { // traverse BBs in random order
677 cout << endl ; printLabel( *BBI); cout << ": ";
679 // get the iterator for machine instructions
680 MachineCodeForBasicBlock& MIVec = (*BBI)->getMachineInstrVec();
681 MachineCodeForBasicBlock::iterator MInstIterator = MIVec.begin();
683 // iterate over all the machine instructions in BB
684 for( ; MInstIterator != MIVec.end(); ++MInstIterator) {
686 MachineInstr *const MInst = *MInstIterator;
689 cout << endl << "\t";
690 cout << TargetInstrDescriptors[MInst->getOpCode()].opCodeString;
693 //for(MachineInstr::val_op_const_iterator OpI(MInst);!OpI.done();++OpI) {
695 for(unsigned OpNum=0; OpNum < MInst->getNumOperands(); ++OpNum) {
697 MachineOperand& Op = MInst->getOperand(OpNum);
699 if( Op.getOperandType() == MachineOperand::MO_VirtualRegister ||
700 Op.getOperandType() == MachineOperand::MO_CCRegister /*||
701 Op.getOperandType() == MachineOperand::MO_PCRelativeDisp*/ ) {
703 const Value *const Val = Op.getVRegValue () ;
704 // ****this code is temporary till NULL Values are fixed
706 cout << "\t<*NULL*>";
710 // if a label or a constant
711 if( (Val->getValueType() == Value::BasicBlockVal) ) {
713 cout << "\t"; printLabel( Op.getVRegValue () );
716 // else it must be a register value
717 const int RegNum = Op.getAllocatedRegNum();
719 cout << "\t" << "%" << MRI.getUnifiedRegName( RegNum );
723 else if(Op.getOperandType() == MachineOperand::MO_MachineRegister) {
724 cout << "\t" << "%" << MRI.getUnifiedRegName(Op.getMachineRegNum());
728 cout << "\t" << Op; // use dump field
733 unsigned NumOfImpRefs = MInst->getNumImplicitRefs();
734 if( NumOfImpRefs > 0 ) {
736 cout << "\tImplicit:";
738 for(unsigned z=0; z < NumOfImpRefs; z++) {
739 printValue( MInst->getImplicitRef(z) );
745 } // for all machine instructions
756 //----------------------------------------------------------------------------
758 //----------------------------------------------------------------------------
760 void PhyRegAlloc::colorCallRetArgs()
763 CallRetInstrListType &CallRetInstList = LRI.getCallRetInstrList();
764 CallRetInstrListType::const_iterator It = CallRetInstList.begin();
766 for( ; It != CallRetInstList.end(); ++It ) {
768 const MachineInstr *const CRMI = *It;
769 unsigned OpCode = CRMI->getOpCode();
771 // get the added instructions for this Call/Ret instruciton
772 AddedInstrns *AI = AddedInstrMap[ CRMI ];
774 AI = new AddedInstrns();
775 AddedInstrMap[ CRMI ] = AI;
778 if( (TM.getInstrInfo()).isCall( OpCode ) )
779 MRI.colorCallArgs( CRMI, LRI, AI );
781 else if ( (TM.getInstrInfo()).isReturn(OpCode) )
782 MRI.colorRetValue( CRMI, LRI, AI );
784 else assert( 0 && "Non Call/Ret instrn in CallRetInstrList\n" );
792 //----------------------------------------------------------------------------
794 //----------------------------------------------------------------------------
795 void PhyRegAlloc::colorIncomingArgs()
797 const BasicBlock *const FirstBB = Meth->front();
798 const MachineInstr *FirstMI = *((FirstBB->getMachineInstrVec()).begin());
799 assert( FirstMI && "No machine instruction in entry BB");
801 AddedInstrns *AI = AddedInstrMap[ FirstMI ];
803 AI = new AddedInstrns();
804 AddedInstrMap[ FirstMI ] = AI;
807 MRI.colorMethodArgs(Meth, LRI, AI );
811 //----------------------------------------------------------------------------
812 // Used to generate a label for a basic block
813 //----------------------------------------------------------------------------
814 void PhyRegAlloc::printLabel(const Value *const Val)
817 cout << Val->getName();
819 cout << "Label" << Val;
823 //----------------------------------------------------------------------------
824 // This method calls setSugColorUsable method of each live range. This
825 // will determine whether the suggested color of LR is really usable.
826 // A suggested color is not usable when the suggested color is volatile
827 // AND when there are call interferences
828 //----------------------------------------------------------------------------
830 void PhyRegAlloc::markUnusableSugColors()
832 if(DEBUG_RA ) cout << "Creating LR lists ..." << endl;
835 LiveRangeMapType::const_iterator HMI = (LRI.getLiveRangeMap())->begin();
836 LiveRangeMapType::const_iterator HMIEnd = (LRI.getLiveRangeMap())->end();
838 for( ; HMI != HMIEnd ; ++HMI ) {
842 LiveRange *L = (*HMI).second; // get the LiveRange
845 if( L->hasSuggestedColor() ) {
847 int RCID = (L->getRegClass())->getID();
848 if( MRI.isRegVolatile( RCID, L->getSuggestedColor()) &&
849 L->isCallInterference() )
850 L->setSuggestedColorUsable( false );
852 L->setSuggestedColorUsable( true );
854 } // if L->hasSuggestedColor()
856 } // for all LR's in hash map
869 //----------------------------------------------------------------------------
870 // The entry pont to Register Allocation
871 //----------------------------------------------------------------------------
873 void PhyRegAlloc::allocateRegisters()
876 // make sure that we put all register classes into the RegClassList
877 // before we call constructLiveRanges (now done in the constructor of
878 // PhyRegAlloc class).
880 constructLiveRanges(); // create LR info
883 LRI.printLiveRanges();
885 createIGNodeListsAndIGs(); // create IGNode list and IGs
887 buildInterferenceGraphs(); // build IGs in all reg classes
891 // print all LRs in all reg classes
892 for( unsigned int rc=0; rc < NumOfRegClasses ; rc++)
893 RegClassList[ rc ]->printIGNodeList();
895 // print IGs in all register classes
896 for( unsigned int rc=0; rc < NumOfRegClasses ; rc++)
897 RegClassList[ rc ]->printIG();
900 LRI.coalesceLRs(); // coalesce all live ranges
903 // print all LRs in all reg classes
904 for( unsigned int rc=0; rc < NumOfRegClasses ; rc++)
905 RegClassList[ rc ]->printIGNodeList();
907 // print IGs in all register classes
908 for( unsigned int rc=0; rc < NumOfRegClasses ; rc++)
909 RegClassList[ rc ]->printIG();
913 // mark un-usable suggested color before graph coloring algorithm.
914 // When this is done, the graph coloring algo will not reserve
915 // suggested color unnecessarily - they can be used by another LR
916 markUnusableSugColors();
918 // color all register classes using the graph coloring algo
919 for( unsigned int rc=0; rc < NumOfRegClasses ; rc++)
920 RegClassList[ rc ]->colorAllRegs();
923 // color incoming args and call args
930 Meth->getMachineCode().dump();
931 printMachineCode(); // only for DEBUGGING