1 //===-- PhyRegAlloc.cpp ---------------------------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Traditional graph-coloring global register allocator currently used
11 // by the SPARC back-end.
13 // NOTE: This register allocator has some special support
14 // for the Reoptimizer, such as not saving some registers on calls to
15 // the first-level instrumentation function.
17 // NOTE 2: This register allocator can save its state in a global
18 // variable in the module it's working on. This feature is not
19 // thread-safe; if you have doubts, leave it turned off.
21 //===----------------------------------------------------------------------===//
23 #include "AllocInfo.h"
25 #include "PhyRegAlloc.h"
26 #include "RegAllocCommon.h"
28 #include "../LiveVar/FunctionLiveVarInfo.h"
29 #include "llvm/Constants.h"
30 #include "llvm/DerivedTypes.h"
31 #include "llvm/iPHINode.h"
32 #include "llvm/iOther.h"
33 #include "llvm/Module.h"
34 #include "llvm/Type.h"
35 #include "llvm/Analysis/LoopInfo.h"
36 #include "llvm/CodeGen/InstrSelection.h"
37 #include "llvm/CodeGen/MachineCodeForInstruction.h"
38 #include "llvm/CodeGen/MachineFunction.h"
39 #include "llvm/CodeGen/MachineFunctionInfo.h"
40 #include "llvm/CodeGen/MachineInstr.h"
41 #include "llvm/CodeGen/MachineInstrBuilder.h"
42 #include "../MachineInstrAnnot.h"
43 #include "llvm/CodeGen/Passes.h"
44 #include "llvm/Support/InstIterator.h"
45 #include "llvm/Target/TargetInstrInfo.h"
46 #include "Support/CommandLine.h"
47 #include "Support/SetOperations.h"
48 #include "Support/STLExtras.h"
53 RegAllocDebugLevel_t DEBUG_RA;
55 static cl::opt<RegAllocDebugLevel_t, true>
56 DRA_opt("dregalloc", cl::Hidden, cl::location(DEBUG_RA),
57 cl::desc("enable register allocation debugging information"),
59 clEnumValN(RA_DEBUG_None , "n", "disable debug output"),
60 clEnumValN(RA_DEBUG_Results, "y", "debug output for allocation results"),
61 clEnumValN(RA_DEBUG_Coloring, "c", "debug output for graph coloring step"),
62 clEnumValN(RA_DEBUG_Interference,"ig","debug output for interference graphs"),
63 clEnumValN(RA_DEBUG_LiveRanges , "lr","debug output for live ranges"),
64 clEnumValN(RA_DEBUG_Verbose, "v", "extra debug output"),
67 /// The reoptimizer wants to be able to grovel through the register
68 /// allocator's state after it has done its job. This is a hack.
70 PhyRegAlloc::SavedStateMapTy ExportedFnAllocState;
71 bool SaveRegAllocState = false;
72 bool SaveStateToModule = true;
73 static cl::opt<bool, true>
74 SaveRegAllocStateOpt("save-ra-state", cl::Hidden,
75 cl::location (SaveRegAllocState),
77 cl::desc("write reg. allocator state into module"));
79 FunctionPass *getRegisterAllocator(TargetMachine &T) {
80 return new PhyRegAlloc (T);
83 void PhyRegAlloc::getAnalysisUsage(AnalysisUsage &AU) const {
84 AU.addRequired<LoopInfo> ();
85 AU.addRequired<FunctionLiveVarInfo> ();
89 /// Initialize interference graphs (one in each reg class) and IGNodeLists
90 /// (one in each IG). The actual nodes will be pushed later.
92 void PhyRegAlloc::createIGNodeListsAndIGs() {
93 if (DEBUG_RA >= RA_DEBUG_LiveRanges) std::cerr << "Creating LR lists ...\n";
95 LiveRangeMapType::const_iterator HMI = LRI->getLiveRangeMap()->begin();
96 LiveRangeMapType::const_iterator HMIEnd = LRI->getLiveRangeMap()->end();
98 for (; HMI != HMIEnd ; ++HMI ) {
100 LiveRange *L = HMI->second; // get the LiveRange
102 if (DEBUG_RA && !isa<ConstantIntegral> (HMI->first))
103 std::cerr << "\n**** ?!?WARNING: NULL LIVE RANGE FOUND FOR: "
104 << RAV(HMI->first) << "****\n";
108 // if the Value * is not null, and LR is not yet written to the IGNodeList
109 if (!(L->getUserIGNode()) ) {
110 RegClass *const RC = // RegClass of first value in the LR
111 RegClassList[ L->getRegClassID() ];
112 RC->addLRToIG(L); // add this LR to an IG
118 for ( unsigned rc=0; rc < NumOfRegClasses ; rc++)
119 RegClassList[rc]->createInterferenceGraph();
121 if (DEBUG_RA >= RA_DEBUG_LiveRanges) std::cerr << "LRLists Created!\n";
125 /// Add all interferences for a given instruction. Interference occurs only
126 /// if the LR of Def (Inst or Arg) is of the same reg class as that of live
127 /// var. The live var passed to this function is the LVset AFTER the
130 void PhyRegAlloc::addInterference(const Value *Def, const ValueSet *LVSet,
132 ValueSet::const_iterator LIt = LVSet->begin();
134 // get the live range of instruction
135 const LiveRange *const LROfDef = LRI->getLiveRangeForValue( Def );
137 IGNode *const IGNodeOfDef = LROfDef->getUserIGNode();
138 assert( IGNodeOfDef );
140 RegClass *const RCOfDef = LROfDef->getRegClass();
142 // for each live var in live variable set
143 for ( ; LIt != LVSet->end(); ++LIt) {
145 if (DEBUG_RA >= RA_DEBUG_Verbose)
146 std::cerr << "< Def=" << RAV(Def) << ", Lvar=" << RAV(*LIt) << "> ";
148 // get the live range corresponding to live var
149 LiveRange *LROfVar = LRI->getLiveRangeForValue(*LIt);
151 // LROfVar can be null if it is a const since a const
152 // doesn't have a dominating def - see Assumptions above
154 if (LROfDef != LROfVar) // do not set interf for same LR
155 if (RCOfDef == LROfVar->getRegClass()) // 2 reg classes are the same
156 RCOfDef->setInterference( LROfDef, LROfVar);
161 /// For a call instruction, this method sets the CallInterference flag in
162 /// the LR of each variable live in the Live Variable Set live after the
163 /// call instruction (except the return value of the call instruction - since
164 /// the return value does not interfere with that call itself).
166 void PhyRegAlloc::setCallInterferences(const MachineInstr *MInst,
167 const ValueSet *LVSetAft) {
168 if (DEBUG_RA >= RA_DEBUG_Interference)
169 std::cerr << "\n For call inst: " << *MInst;
171 // for each live var in live variable set after machine inst
172 for (ValueSet::const_iterator LIt = LVSetAft->begin(), LEnd = LVSetAft->end();
173 LIt != LEnd; ++LIt) {
175 // get the live range corresponding to live var
176 LiveRange *const LR = LRI->getLiveRangeForValue(*LIt );
178 // LR can be null if it is a const since a const
179 // doesn't have a dominating def - see Assumptions above
181 if (DEBUG_RA >= RA_DEBUG_Interference) {
182 std::cerr << "\n\tLR after Call: ";
185 LR->setCallInterference();
186 if (DEBUG_RA >= RA_DEBUG_Interference) {
187 std::cerr << "\n ++After adding call interference for LR: " ;
194 // Now find the LR of the return value of the call
195 // We do this because, we look at the LV set *after* the instruction
196 // to determine, which LRs must be saved across calls. The return value
197 // of the call is live in this set - but it does not interfere with call
198 // (i.e., we can allocate a volatile register to the return value)
199 CallArgsDescriptor* argDesc = CallArgsDescriptor::get(MInst);
201 if (const Value *RetVal = argDesc->getReturnValue()) {
202 LiveRange *RetValLR = LRI->getLiveRangeForValue( RetVal );
203 assert( RetValLR && "No LR for RetValue of call");
204 RetValLR->clearCallInterference();
207 // If the CALL is an indirect call, find the LR of the function pointer.
208 // That has a call interference because it conflicts with outgoing args.
209 if (const Value *AddrVal = argDesc->getIndirectFuncPtr()) {
210 LiveRange *AddrValLR = LRI->getLiveRangeForValue( AddrVal );
211 assert( AddrValLR && "No LR for indirect addr val of call");
212 AddrValLR->setCallInterference();
217 /// Create interferences in the IG of each RegClass, and calculate the spill
218 /// cost of each Live Range (it is done in this method to save another pass
221 void PhyRegAlloc::buildInterferenceGraphs() {
222 if (DEBUG_RA >= RA_DEBUG_Interference)
223 std::cerr << "Creating interference graphs ...\n";
225 unsigned BBLoopDepthCost;
226 for (MachineFunction::iterator BBI = MF->begin(), BBE = MF->end();
228 const MachineBasicBlock &MBB = *BBI;
229 const BasicBlock *BB = MBB.getBasicBlock();
231 // find the 10^(loop_depth) of this BB
232 BBLoopDepthCost = (unsigned)pow(10.0, LoopDepthCalc->getLoopDepth(BB));
234 // get the iterator for machine instructions
235 MachineBasicBlock::const_iterator MII = MBB.begin();
237 // iterate over all the machine instructions in BB
238 for ( ; MII != MBB.end(); ++MII) {
239 const MachineInstr *MInst = MII;
241 // get the LV set after the instruction
242 const ValueSet &LVSetAI = LVI->getLiveVarSetAfterMInst(MInst, BB);
243 bool isCallInst = TM.getInstrInfo().isCall(MInst->getOpcode());
246 // set the isCallInterference flag of each live range which extends
247 // across this call instruction. This information is used by graph
248 // coloring algorithm to avoid allocating volatile colors to live ranges
249 // that span across calls (since they have to be saved/restored)
250 setCallInterferences(MInst, &LVSetAI);
253 // iterate over all MI operands to find defs
254 for (MachineInstr::const_val_op_iterator OpI = MInst->begin(),
255 OpE = MInst->end(); OpI != OpE; ++OpI) {
256 if (OpI.isDef()) // create a new LR since def
257 addInterference(*OpI, &LVSetAI, isCallInst);
259 // Calculate the spill cost of each live range
260 LiveRange *LR = LRI->getLiveRangeForValue(*OpI);
261 if (LR) LR->addSpillCost(BBLoopDepthCost);
264 // Mark all operands of pseudo-instructions as interfering with one
265 // another. This must be done because pseudo-instructions may be
266 // expanded to multiple instructions by the assembler, so all the
267 // operands must get distinct registers.
268 if (TM.getInstrInfo().isPseudoInstr(MInst->getOpcode()))
269 addInterf4PseudoInstr(MInst);
271 // Also add interference for any implicit definitions in a machine
272 // instr (currently, only calls have this).
273 unsigned NumOfImpRefs = MInst->getNumImplicitRefs();
274 for (unsigned z=0; z < NumOfImpRefs; z++)
275 if (MInst->getImplicitOp(z).isDef())
276 addInterference( MInst->getImplicitRef(z), &LVSetAI, isCallInst );
278 } // for all machine instructions in BB
279 } // for all BBs in function
281 // add interferences for function arguments. Since there are no explicit
282 // defs in the function for args, we have to add them manually
283 addInterferencesForArgs();
285 if (DEBUG_RA >= RA_DEBUG_Interference)
286 std::cerr << "Interference graphs calculated!\n";
290 /// Mark all operands of the given MachineInstr as interfering with one
293 void PhyRegAlloc::addInterf4PseudoInstr(const MachineInstr *MInst) {
294 bool setInterf = false;
296 // iterate over MI operands to find defs
297 for (MachineInstr::const_val_op_iterator It1 = MInst->begin(),
298 ItE = MInst->end(); It1 != ItE; ++It1) {
299 const LiveRange *LROfOp1 = LRI->getLiveRangeForValue(*It1);
300 assert((LROfOp1 || It1.isDef()) && "No LR for Def in PSEUDO insruction");
302 MachineInstr::const_val_op_iterator It2 = It1;
303 for (++It2; It2 != ItE; ++It2) {
304 const LiveRange *LROfOp2 = LRI->getLiveRangeForValue(*It2);
307 RegClass *RCOfOp1 = LROfOp1->getRegClass();
308 RegClass *RCOfOp2 = LROfOp2->getRegClass();
310 if (RCOfOp1 == RCOfOp2 ){
311 RCOfOp1->setInterference( LROfOp1, LROfOp2 );
315 } // for all other defs in machine instr
316 } // for all operands in an instruction
318 if (!setInterf && MInst->getNumOperands() > 2) {
319 std::cerr << "\nInterf not set for any operand in pseudo instr:\n";
321 assert(0 && "Interf not set for pseudo instr with > 2 operands" );
326 /// Add interferences for incoming arguments to a function.
328 void PhyRegAlloc::addInterferencesForArgs() {
329 // get the InSet of root BB
330 const ValueSet &InSet = LVI->getInSetOfBB(&Fn->front());
332 for (Function::const_aiterator AI = Fn->abegin(); AI != Fn->aend(); ++AI) {
333 // add interferences between args and LVars at start
334 addInterference(AI, &InSet, false);
336 if (DEBUG_RA >= RA_DEBUG_Interference)
337 std::cerr << " - %% adding interference for argument " << RAV(AI) << "\n";
342 /// The following are utility functions used solely by updateMachineCode and
343 /// the functions that it calls. They should probably be folded back into
344 /// updateMachineCode at some point.
347 // used by: updateMachineCode (1 time), PrependInstructions (1 time)
348 inline void InsertBefore(MachineInstr* newMI, MachineBasicBlock& MBB,
349 MachineBasicBlock::iterator& MII) {
350 MII = MBB.insert(MII, newMI);
354 // used by: AppendInstructions (1 time)
355 inline void InsertAfter(MachineInstr* newMI, MachineBasicBlock& MBB,
356 MachineBasicBlock::iterator& MII) {
357 ++MII; // insert before the next instruction
358 MII = MBB.insert(MII, newMI);
361 // used by: updateMachineCode (2 times)
362 inline void PrependInstructions(std::vector<MachineInstr *> &IBef,
363 MachineBasicBlock& MBB,
364 MachineBasicBlock::iterator& MII,
365 const std::string& msg) {
367 MachineInstr* OrigMI = MII;
368 std::vector<MachineInstr *>::iterator AdIt;
369 for (AdIt = IBef.begin(); AdIt != IBef.end() ; ++AdIt) {
371 if (OrigMI) std::cerr << "For MInst:\n " << *OrigMI;
372 std::cerr << msg << "PREPENDed instr:\n " << **AdIt << "\n";
374 InsertBefore(*AdIt, MBB, MII);
379 // used by: updateMachineCode (1 time)
380 inline void AppendInstructions(std::vector<MachineInstr *> &IAft,
381 MachineBasicBlock& MBB,
382 MachineBasicBlock::iterator& MII,
383 const std::string& msg) {
385 MachineInstr* OrigMI = MII;
386 std::vector<MachineInstr *>::iterator AdIt;
387 for ( AdIt = IAft.begin(); AdIt != IAft.end() ; ++AdIt ) {
389 if (OrigMI) std::cerr << "For MInst:\n " << *OrigMI;
390 std::cerr << msg << "APPENDed instr:\n " << **AdIt << "\n";
392 InsertAfter(*AdIt, MBB, MII);
397 /// Set the registers for operands in the given MachineInstr, if a register was
398 /// successfully allocated. Return true if any of its operands has been marked
401 bool PhyRegAlloc::markAllocatedRegs(MachineInstr* MInst)
403 bool instrNeedsSpills = false;
405 // First, set the registers for operands in the machine instruction
406 // if a register was successfully allocated. Do this first because we
407 // will need to know which registers are already used by this instr'n.
408 for (unsigned OpNum=0; OpNum < MInst->getNumOperands(); ++OpNum) {
409 MachineOperand& Op = MInst->getOperand(OpNum);
410 if (Op.getType() == MachineOperand::MO_VirtualRegister ||
411 Op.getType() == MachineOperand::MO_CCRegister) {
412 const Value *const Val = Op.getVRegValue();
413 if (const LiveRange* LR = LRI->getLiveRangeForValue(Val)) {
414 // Remember if any operand needs spilling
415 instrNeedsSpills |= LR->isMarkedForSpill();
417 // An operand may have a color whether or not it needs spilling
419 MInst->SetRegForOperand(OpNum,
420 MRI.getUnifiedRegNum(LR->getRegClassID(),
424 } // for each operand
426 return instrNeedsSpills;
429 /// Mark allocated registers (using markAllocatedRegs()) on the instruction
430 /// that MII points to. Then, if it's a call instruction, insert caller-saving
431 /// code before and after it. Finally, insert spill code before and after it,
432 /// using insertCode4SpilledLR().
434 void PhyRegAlloc::updateInstruction(MachineBasicBlock::iterator& MII,
435 MachineBasicBlock &MBB) {
436 MachineInstr* MInst = MII;
437 unsigned Opcode = MInst->getOpcode();
439 // Reset tmp stack positions so they can be reused for each machine instr.
440 MF->getInfo()->popAllTempValues();
442 // Mark the operands for which regs have been allocated.
443 bool instrNeedsSpills = markAllocatedRegs(MII);
446 // Mark that the operands have been updated. Later,
447 // setRelRegsUsedByThisInst() is called to find registers used by each
448 // MachineInst, and it should not be used for an instruction until
449 // this is done. This flag just serves as a sanity check.
450 OperandsColoredMap[MInst] = true;
453 // Now insert caller-saving code before/after the call.
454 // Do this before inserting spill code since some registers must be
455 // used by save/restore and spill code should not use those registers.
456 if (TM.getInstrInfo().isCall(Opcode)) {
457 AddedInstrns &AI = AddedInstrMap[MInst];
458 insertCallerSavingCode(AI.InstrnsBefore, AI.InstrnsAfter, MInst,
459 MBB.getBasicBlock());
462 // Now insert spill code for remaining operands not allocated to
463 // registers. This must be done even for call return instructions
464 // since those are not handled by the special code above.
465 if (instrNeedsSpills)
466 for (unsigned OpNum=0; OpNum < MInst->getNumOperands(); ++OpNum) {
467 MachineOperand& Op = MInst->getOperand(OpNum);
468 if (Op.getType() == MachineOperand::MO_VirtualRegister ||
469 Op.getType() == MachineOperand::MO_CCRegister) {
470 const Value* Val = Op.getVRegValue();
471 if (const LiveRange *LR = LRI->getLiveRangeForValue(Val))
472 if (LR->isMarkedForSpill())
473 insertCode4SpilledLR(LR, MII, MBB, OpNum);
475 } // for each operand
478 /// Iterate over all the MachineBasicBlocks in the current function and set
479 /// the allocated registers for each instruction (using updateInstruction()),
480 /// after register allocation is complete. Then move code out of delay slots.
482 void PhyRegAlloc::updateMachineCode()
484 // Insert any instructions needed at method entry
485 MachineBasicBlock::iterator MII = MF->front().begin();
486 PrependInstructions(AddedInstrAtEntry.InstrnsBefore, MF->front(), MII,
487 "At function entry: \n");
488 assert(AddedInstrAtEntry.InstrnsAfter.empty() &&
489 "InstrsAfter should be unnecessary since we are just inserting at "
490 "the function entry point here.");
492 for (MachineFunction::iterator BBI = MF->begin(), BBE = MF->end();
494 MachineBasicBlock &MBB = *BBI;
496 // Iterate over all machine instructions in BB and mark operands with
497 // their assigned registers or insert spill code, as appropriate.
498 // Also, fix operands of call/return instructions.
499 for (MachineBasicBlock::iterator MII = MBB.begin(); MII != MBB.end(); ++MII)
500 if (! TM.getInstrInfo().isDummyPhiInstr(MII->getOpcode()))
501 updateInstruction(MII, MBB);
503 // Now, move code out of delay slots of branches and returns if needed.
504 // (Also, move "after" code from calls to the last delay slot instruction.)
505 // Moving code out of delay slots is needed in 2 situations:
506 // (1) If this is a branch and it needs instructions inserted after it,
507 // move any existing instructions out of the delay slot so that the
508 // instructions can go into the delay slot. This only supports the
509 // case that #instrsAfter <= #delay slots.
511 // (2) If any instruction in the delay slot needs
512 // instructions inserted, move it out of the delay slot and before the
513 // branch because putting code before or after it would be VERY BAD!
515 // If the annul bit of the branch is set, neither of these is legal!
516 // If so, we need to handle spill differently but annulling is not yet used.
517 for (MachineBasicBlock::iterator MII = MBB.begin(); MII != MBB.end(); ++MII)
518 if (unsigned delaySlots =
519 TM.getInstrInfo().getNumDelaySlots(MII->getOpcode())) {
520 MachineBasicBlock::iterator DelaySlotMI = next(MII);
521 assert(DelaySlotMI != MBB.end() && "no instruction for delay slot");
523 // Check the 2 conditions above:
524 // (1) Does a branch need instructions added after it?
525 // (2) O/w does delay slot instr. need instrns before or after?
526 bool isBranch = (TM.getInstrInfo().isBranch(MII->getOpcode()) ||
527 TM.getInstrInfo().isReturn(MII->getOpcode()));
528 bool cond1 = (isBranch &&
529 AddedInstrMap.count(MII) &&
530 AddedInstrMap[MII].InstrnsAfter.size() > 0);
531 bool cond2 = (AddedInstrMap.count(DelaySlotMI) &&
532 (AddedInstrMap[DelaySlotMI].InstrnsBefore.size() > 0 ||
533 AddedInstrMap[DelaySlotMI].InstrnsAfter.size() > 0));
535 if (cond1 || cond2) {
536 assert(delaySlots==1 &&
537 "InsertBefore does not yet handle >1 delay slots!");
540 std::cerr << "\nRegAlloc: Moved instr. with added code: "
542 << " out of delay slots of instr: " << *MII;
545 // move instruction before branch
546 MBB.insert(MII, MBB.remove(DelaySlotMI++));
548 // On cond1 we are done (we already moved the
549 // instruction out of the delay slot). On cond2 we need
550 // to insert a nop in place of the moved instruction
552 MBB.insert(MII, BuildMI(TM.getInstrInfo().getNOPOpCode(),1));
556 // For non-branch instr with delay slots (probably a call), move
557 // InstrAfter to the instr. in the last delay slot.
558 MachineBasicBlock::iterator tmp = next(MII, delaySlots);
559 move2DelayedInstr(MII, tmp);
563 // Finally iterate over all instructions in BB and insert before/after
564 for (MachineBasicBlock::iterator MII=MBB.begin(); MII != MBB.end(); ++MII) {
565 MachineInstr *MInst = MII;
567 // do not process Phis
568 if (TM.getInstrInfo().isDummyPhiInstr(MInst->getOpcode()))
571 // if there are any added instructions...
572 if (AddedInstrMap.count(MInst)) {
573 AddedInstrns &CallAI = AddedInstrMap[MInst];
576 bool isBranch = (TM.getInstrInfo().isBranch(MInst->getOpcode()) ||
577 TM.getInstrInfo().isReturn(MInst->getOpcode()));
579 AddedInstrMap[MInst].InstrnsAfter.size() <=
580 TM.getInstrInfo().getNumDelaySlots(MInst->getOpcode())) &&
581 "Cannot put more than #delaySlots instrns after "
582 "branch or return! Need to handle temps differently.");
586 // Temporary sanity checking code to detect whether the same machine
587 // instruction is ever inserted twice before/after a call.
588 // I suspect this is happening but am not sure. --Vikram, 7/1/03.
589 std::set<const MachineInstr*> instrsSeen;
590 for (int i = 0, N = CallAI.InstrnsBefore.size(); i < N; ++i) {
591 assert(instrsSeen.count(CallAI.InstrnsBefore[i]) == 0 &&
592 "Duplicate machine instruction in InstrnsBefore!");
593 instrsSeen.insert(CallAI.InstrnsBefore[i]);
595 for (int i = 0, N = CallAI.InstrnsAfter.size(); i < N; ++i) {
596 assert(instrsSeen.count(CallAI.InstrnsAfter[i]) == 0 &&
597 "Duplicate machine instruction in InstrnsBefore/After!");
598 instrsSeen.insert(CallAI.InstrnsAfter[i]);
602 // Now add the instructions before/after this MI.
603 // We do this here to ensure that spill for an instruction is inserted
604 // as close as possible to an instruction (see above insertCode4Spill)
605 if (! CallAI.InstrnsBefore.empty())
606 PrependInstructions(CallAI.InstrnsBefore, MBB, MII,"");
608 if (! CallAI.InstrnsAfter.empty())
609 AppendInstructions(CallAI.InstrnsAfter, MBB, MII,"");
611 } // if there are any added instructions
612 } // for each machine instruction
617 /// Insert spill code for AN operand whose LR was spilled. May be called
618 /// repeatedly for a single MachineInstr if it has many spilled operands. On
619 /// each call, it finds a register which is not live at that instruction and
620 /// also which is not used by other spilled operands of the same
621 /// instruction. Then it uses this register temporarily to accommodate the
624 void PhyRegAlloc::insertCode4SpilledLR(const LiveRange *LR,
625 MachineBasicBlock::iterator& MII,
626 MachineBasicBlock &MBB,
627 const unsigned OpNum) {
628 MachineInstr *MInst = MII;
629 const BasicBlock *BB = MBB.getBasicBlock();
631 assert((! TM.getInstrInfo().isCall(MInst->getOpcode()) || OpNum == 0) &&
632 "Outgoing arg of a call must be handled elsewhere (func arg ok)");
633 assert(! TM.getInstrInfo().isReturn(MInst->getOpcode()) &&
634 "Return value of a ret must be handled elsewhere");
636 MachineOperand& Op = MInst->getOperand(OpNum);
637 bool isDef = Op.isDef();
638 bool isUse = Op.isUse();
639 unsigned RegType = MRI.getRegTypeForLR(LR);
640 int SpillOff = LR->getSpillOffFromFP();
641 RegClass *RC = LR->getRegClass();
643 // Get the live-variable set to find registers free before this instr.
644 const ValueSet &LVSetBef = LVI->getLiveVarSetBeforeMInst(MInst, BB);
647 // If this instr. is in the delay slot of a branch or return, we need to
648 // include all live variables before that branch or return -- we don't want to
649 // trample those! Verify that the set is included in the LV set before MInst.
650 if (MII != MBB.begin()) {
651 MachineBasicBlock::iterator PredMI = prior(MII);
652 if (unsigned DS = TM.getInstrInfo().getNumDelaySlots(PredMI->getOpcode()))
653 assert(set_difference(LVI->getLiveVarSetBeforeMInst(PredMI), LVSetBef)
654 .empty() && "Live-var set before branch should be included in "
655 "live-var set of each delay slot instruction!");
659 MF->getInfo()->pushTempValue(MRI.getSpilledRegSize(RegType));
661 std::vector<MachineInstr*> MIBef, MIAft;
662 std::vector<MachineInstr*> AdIMid;
664 // Choose a register to hold the spilled value, if one was not preallocated.
665 // This may insert code before and after MInst to free up the value. If so,
666 // this code should be first/last in the spill sequence before/after MInst.
667 int TmpRegU=(LR->hasColor()
668 ? MRI.getUnifiedRegNum(LR->getRegClassID(),LR->getColor())
669 : getUsableUniRegAtMI(RegType, &LVSetBef, MInst, MIBef,MIAft));
671 // Set the operand first so that it this register does not get used
672 // as a scratch register for later calls to getUsableUniRegAtMI below
673 MInst->SetRegForOperand(OpNum, TmpRegU);
675 // get the added instructions for this instruction
676 AddedInstrns &AI = AddedInstrMap[MInst];
678 // We may need a scratch register to copy the spilled value to/from memory.
679 // This may itself have to insert code to free up a scratch register.
680 // Any such code should go before (after) the spill code for a load (store).
681 // The scratch reg is not marked as used because it is only used
682 // for the copy and not used across MInst.
683 int scratchRegType = -1;
685 if (MRI.regTypeNeedsScratchReg(RegType, scratchRegType)) {
686 scratchReg = getUsableUniRegAtMI(scratchRegType, &LVSetBef,
687 MInst, MIBef, MIAft);
688 assert(scratchReg != MRI.getInvalidRegNum());
692 // for a USE, we have to load the value of LR from stack to a TmpReg
693 // and use the TmpReg as one operand of instruction
695 // actual loading instruction(s)
696 MRI.cpMem2RegMI(AdIMid, MRI.getFramePointer(), SpillOff, TmpRegU,
697 RegType, scratchReg);
699 // the actual load should be after the instructions to free up TmpRegU
700 MIBef.insert(MIBef.end(), AdIMid.begin(), AdIMid.end());
704 if (isDef) { // if this is a Def
705 // for a DEF, we have to store the value produced by this instruction
706 // on the stack position allocated for this LR
708 // actual storing instruction(s)
709 MRI.cpReg2MemMI(AdIMid, TmpRegU, MRI.getFramePointer(), SpillOff,
710 RegType, scratchReg);
712 MIAft.insert(MIAft.begin(), AdIMid.begin(), AdIMid.end());
715 // Finally, insert the entire spill code sequences before/after MInst
716 AI.InstrnsBefore.insert(AI.InstrnsBefore.end(), MIBef.begin(), MIBef.end());
717 AI.InstrnsAfter.insert(AI.InstrnsAfter.begin(), MIAft.begin(), MIAft.end());
720 std::cerr << "\nFor Inst:\n " << *MInst;
721 std::cerr << "SPILLED LR# " << LR->getUserIGNode()->getIndex();
722 std::cerr << "; added Instructions:";
723 for_each(MIBef.begin(), MIBef.end(), std::mem_fun(&MachineInstr::dump));
724 for_each(MIAft.begin(), MIAft.end(), std::mem_fun(&MachineInstr::dump));
729 /// Insert caller saving/restoring instructions before/after a call machine
730 /// instruction (before or after any other instructions that were inserted for
734 PhyRegAlloc::insertCallerSavingCode(std::vector<MachineInstr*> &instrnsBefore,
735 std::vector<MachineInstr*> &instrnsAfter,
736 MachineInstr *CallMI,
737 const BasicBlock *BB) {
738 assert(TM.getInstrInfo().isCall(CallMI->getOpcode()));
740 // hash set to record which registers were saved/restored
741 hash_set<unsigned> PushedRegSet;
743 CallArgsDescriptor* argDesc = CallArgsDescriptor::get(CallMI);
745 // if the call is to a instrumentation function, do not insert save and
746 // restore instructions the instrumentation function takes care of save
747 // restore for volatile regs.
749 // FIXME: this should be made general, not specific to the reoptimizer!
750 const Function *Callee = argDesc->getCallInst()->getCalledFunction();
751 bool isLLVMFirstTrigger = Callee && Callee->getName() == "llvm_first_trigger";
753 // Now check if the call has a return value (using argDesc) and if so,
754 // find the LR of the TmpInstruction representing the return value register.
755 // (using the last or second-last *implicit operand* of the call MI).
756 // Insert it to to the PushedRegSet since we must not save that register
757 // and restore it after the call.
758 // We do this because, we look at the LV set *after* the instruction
759 // to determine, which LRs must be saved across calls. The return value
760 // of the call is live in this set - but we must not save/restore it.
761 if (const Value *origRetVal = argDesc->getReturnValue()) {
762 unsigned retValRefNum = (CallMI->getNumImplicitRefs() -
763 (argDesc->getIndirectFuncPtr()? 1 : 2));
764 const TmpInstruction* tmpRetVal =
765 cast<TmpInstruction>(CallMI->getImplicitRef(retValRefNum));
766 assert(tmpRetVal->getOperand(0) == origRetVal &&
767 tmpRetVal->getType() == origRetVal->getType() &&
768 "Wrong implicit ref?");
769 LiveRange *RetValLR = LRI->getLiveRangeForValue(tmpRetVal);
770 assert(RetValLR && "No LR for RetValue of call");
772 if (! RetValLR->isMarkedForSpill())
773 PushedRegSet.insert(MRI.getUnifiedRegNum(RetValLR->getRegClassID(),
774 RetValLR->getColor()));
777 const ValueSet &LVSetAft = LVI->getLiveVarSetAfterMInst(CallMI, BB);
778 ValueSet::const_iterator LIt = LVSetAft.begin();
780 // for each live var in live variable set after machine inst
781 for( ; LIt != LVSetAft.end(); ++LIt) {
782 // get the live range corresponding to live var
783 LiveRange *const LR = LRI->getLiveRangeForValue(*LIt);
785 // LR can be null if it is a const since a const
786 // doesn't have a dominating def - see Assumptions above
788 if (! LR->isMarkedForSpill()) {
789 assert(LR->hasColor() && "LR is neither spilled nor colored?");
790 unsigned RCID = LR->getRegClassID();
791 unsigned Color = LR->getColor();
793 if (MRI.isRegVolatile(RCID, Color) ) {
794 // if this is a call to the first-level reoptimizer
795 // instrumentation entry point, and the register is not
796 // modified by call, don't save and restore it.
797 if (isLLVMFirstTrigger && !MRI.modifiedByCall(RCID, Color))
800 // if the value is in both LV sets (i.e., live before and after
801 // the call machine instruction)
802 unsigned Reg = MRI.getUnifiedRegNum(RCID, Color);
804 // if we haven't already pushed this register...
805 if( PushedRegSet.find(Reg) == PushedRegSet.end() ) {
806 unsigned RegType = MRI.getRegTypeForLR(LR);
808 // Now get two instructions - to push on stack and pop from stack
809 // and add them to InstrnsBefore and InstrnsAfter of the
812 MF->getInfo()->pushTempValue(MRI.getSpilledRegSize(RegType));
814 //---- Insert code for pushing the reg on stack ----------
816 std::vector<MachineInstr*> AdIBef, AdIAft;
818 // We may need a scratch register to copy the saved value
819 // to/from memory. This may itself have to insert code to
820 // free up a scratch register. Any such code should go before
821 // the save code. The scratch register, if any, is by default
822 // temporary and not "used" by the instruction unless the
823 // copy code itself decides to keep the value in the scratch reg.
824 int scratchRegType = -1;
826 if (MRI.regTypeNeedsScratchReg(RegType, scratchRegType))
827 { // Find a register not live in the LVSet before CallMI
828 const ValueSet &LVSetBef =
829 LVI->getLiveVarSetBeforeMInst(CallMI, BB);
830 scratchReg = getUsableUniRegAtMI(scratchRegType, &LVSetBef,
831 CallMI, AdIBef, AdIAft);
832 assert(scratchReg != MRI.getInvalidRegNum());
835 if (AdIBef.size() > 0)
836 instrnsBefore.insert(instrnsBefore.end(),
837 AdIBef.begin(), AdIBef.end());
839 MRI.cpReg2MemMI(instrnsBefore, Reg, MRI.getFramePointer(),
840 StackOff, RegType, scratchReg);
842 if (AdIAft.size() > 0)
843 instrnsBefore.insert(instrnsBefore.end(),
844 AdIAft.begin(), AdIAft.end());
846 //---- Insert code for popping the reg from the stack ----------
850 // We may need a scratch register to copy the saved value
851 // from memory. This may itself have to insert code to
852 // free up a scratch register. Any such code should go
853 // after the save code. As above, scratch is not marked "used".
856 if (MRI.regTypeNeedsScratchReg(RegType, scratchRegType))
857 { // Find a register not live in the LVSet after CallMI
858 scratchReg = getUsableUniRegAtMI(scratchRegType, &LVSetAft,
859 CallMI, AdIBef, AdIAft);
860 assert(scratchReg != MRI.getInvalidRegNum());
863 if (AdIBef.size() > 0)
864 instrnsAfter.insert(instrnsAfter.end(),
865 AdIBef.begin(), AdIBef.end());
867 MRI.cpMem2RegMI(instrnsAfter, MRI.getFramePointer(), StackOff,
868 Reg, RegType, scratchReg);
870 if (AdIAft.size() > 0)
871 instrnsAfter.insert(instrnsAfter.end(),
872 AdIAft.begin(), AdIAft.end());
874 PushedRegSet.insert(Reg);
877 std::cerr << "\nFor call inst:" << *CallMI;
878 std::cerr << " -inserted caller saving instrs: Before:\n\t ";
879 for_each(instrnsBefore.begin(), instrnsBefore.end(),
880 std::mem_fun(&MachineInstr::dump));
881 std::cerr << " -and After:\n\t ";
882 for_each(instrnsAfter.begin(), instrnsAfter.end(),
883 std::mem_fun(&MachineInstr::dump));
885 } // if not already pushed
886 } // if LR has a volatile color
888 } // if there is a LR for Var
889 } // for each value in the LV set after instruction
893 /// Returns the unified register number of a temporary register to be used
894 /// BEFORE MInst. If no register is available, it will pick one and modify
895 /// MIBef and MIAft to contain instructions used to free up this returned
898 int PhyRegAlloc::getUsableUniRegAtMI(const int RegType,
899 const ValueSet *LVSetBef,
901 std::vector<MachineInstr*>& MIBef,
902 std::vector<MachineInstr*>& MIAft) {
903 RegClass* RC = getRegClassByID(MRI.getRegClassIDOfRegType(RegType));
905 int RegU = getUnusedUniRegAtMI(RC, RegType, MInst, LVSetBef);
908 // we couldn't find an unused register. Generate code to free up a reg by
909 // saving it on stack and restoring after the instruction
911 int TmpOff = MF->getInfo()->pushTempValue(MRI.getSpilledRegSize(RegType));
913 RegU = getUniRegNotUsedByThisInst(RC, RegType, MInst);
915 // Check if we need a scratch register to copy this register to memory.
916 int scratchRegType = -1;
917 if (MRI.regTypeNeedsScratchReg(RegType, scratchRegType)) {
918 int scratchReg = getUsableUniRegAtMI(scratchRegType, LVSetBef,
919 MInst, MIBef, MIAft);
920 assert(scratchReg != MRI.getInvalidRegNum());
922 // We may as well hold the value in the scratch register instead
923 // of copying it to memory and back. But we have to mark the
924 // register as used by this instruction, so it does not get used
925 // as a scratch reg. by another operand or anyone else.
926 ScratchRegsUsed.insert(std::make_pair(MInst, scratchReg));
927 MRI.cpReg2RegMI(MIBef, RegU, scratchReg, RegType);
928 MRI.cpReg2RegMI(MIAft, scratchReg, RegU, RegType);
929 } else { // the register can be copied directly to/from memory so do it.
930 MRI.cpReg2MemMI(MIBef, RegU, MRI.getFramePointer(), TmpOff, RegType);
931 MRI.cpMem2RegMI(MIAft, MRI.getFramePointer(), TmpOff, RegU, RegType);
939 /// Returns the register-class register number of a new unused register that
940 /// can be used to accommodate a temporary value. May be called repeatedly
941 /// for a single MachineInstr. On each call, it finds a register which is not
942 /// live at that instruction and which is not used by any spilled operands of
943 /// that instruction.
945 int PhyRegAlloc::getUnusedUniRegAtMI(RegClass *RC, const int RegType,
946 const MachineInstr *MInst,
947 const ValueSet* LVSetBef) {
948 RC->clearColorsUsed(); // Reset array
950 if (LVSetBef == NULL) {
951 LVSetBef = &LVI->getLiveVarSetBeforeMInst(MInst);
952 assert(LVSetBef != NULL && "Unable to get live-var set before MInst?");
955 ValueSet::const_iterator LIt = LVSetBef->begin();
957 // for each live var in live variable set after machine inst
958 for ( ; LIt != LVSetBef->end(); ++LIt) {
959 // Get the live range corresponding to live var, and its RegClass
960 LiveRange *const LRofLV = LRI->getLiveRangeForValue(*LIt );
962 // LR can be null if it is a const since a const
963 // doesn't have a dominating def - see Assumptions above
964 if (LRofLV && LRofLV->getRegClass() == RC && LRofLV->hasColor())
965 RC->markColorsUsed(LRofLV->getColor(),
966 MRI.getRegTypeForLR(LRofLV), RegType);
969 // It is possible that one operand of this MInst was already spilled
970 // and it received some register temporarily. If that's the case,
971 // it is recorded in machine operand. We must skip such registers.
972 setRelRegsUsedByThisInst(RC, RegType, MInst);
974 int unusedReg = RC->getUnusedColor(RegType); // find first unused color
976 return MRI.getUnifiedRegNum(RC->getID(), unusedReg);
982 /// Return the unified register number of a register in class RC which is not
983 /// used by any operands of MInst.
985 int PhyRegAlloc::getUniRegNotUsedByThisInst(RegClass *RC,
987 const MachineInstr *MInst) {
988 RC->clearColorsUsed();
990 setRelRegsUsedByThisInst(RC, RegType, MInst);
992 // find the first unused color
993 int unusedReg = RC->getUnusedColor(RegType);
994 assert(unusedReg >= 0 &&
995 "FATAL: No free register could be found in reg class!!");
997 return MRI.getUnifiedRegNum(RC->getID(), unusedReg);
1001 /// Modify the IsColorUsedArr of register class RC, by setting the bits
1002 /// corresponding to register RegNo. This is a helper method of
1003 /// setRelRegsUsedByThisInst().
1005 static void markRegisterUsed(int RegNo, RegClass *RC, int RegType,
1006 const TargetRegInfo &TRI) {
1007 unsigned classId = 0;
1008 int classRegNum = TRI.getClassRegNum(RegNo, classId);
1009 if (RC->getID() == classId)
1010 RC->markColorsUsed(classRegNum, RegType, RegType);
1013 void PhyRegAlloc::setRelRegsUsedByThisInst(RegClass *RC, int RegType,
1014 const MachineInstr *MI) {
1015 assert(OperandsColoredMap[MI] == true &&
1016 "Illegal to call setRelRegsUsedByThisInst() until colored operands "
1017 "are marked for an instruction.");
1019 // Add the registers already marked as used by the instruction. Both
1020 // explicit and implicit operands are set.
1021 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i)
1022 if (MI->getOperand(i).hasAllocatedReg())
1023 markRegisterUsed(MI->getOperand(i).getReg(), RC, RegType,MRI);
1025 for (unsigned i = 0, e = MI->getNumImplicitRefs(); i != e; ++i)
1026 if (MI->getImplicitOp(i).hasAllocatedReg())
1027 markRegisterUsed(MI->getImplicitOp(i).getReg(), RC, RegType,MRI);
1029 // Add all of the scratch registers that are used to save values across the
1030 // instruction (e.g., for saving state register values).
1031 std::pair<ScratchRegsUsedTy::iterator, ScratchRegsUsedTy::iterator>
1032 IR = ScratchRegsUsed.equal_range(MI);
1033 for (ScratchRegsUsedTy::iterator I = IR.first; I != IR.second; ++I)
1034 markRegisterUsed(I->second, RC, RegType, MRI);
1036 // If there are implicit references, mark their allocated regs as well
1037 for (unsigned z=0; z < MI->getNumImplicitRefs(); z++)
1038 if (const LiveRange*
1039 LRofImpRef = LRI->getLiveRangeForValue(MI->getImplicitRef(z)))
1040 if (LRofImpRef->hasColor())
1041 // this implicit reference is in a LR that received a color
1042 RC->markColorsUsed(LRofImpRef->getColor(),
1043 MRI.getRegTypeForLR(LRofImpRef), RegType);
1047 /// If there are delay slots for an instruction, the instructions added after
1048 /// it must really go after the delayed instruction(s). So, we Move the
1049 /// InstrAfter of that instruction to the corresponding delayed instruction
1050 /// using the following method.
1052 void PhyRegAlloc::move2DelayedInstr(const MachineInstr *OrigMI,
1053 const MachineInstr *DelayedMI)
1055 // "added after" instructions of the original instr
1056 std::vector<MachineInstr *> &OrigAft = AddedInstrMap[OrigMI].InstrnsAfter;
1058 if (DEBUG_RA && OrigAft.size() > 0) {
1059 std::cerr << "\nRegAlloc: Moved InstrnsAfter for: " << *OrigMI;
1060 std::cerr << " to last delay slot instrn: " << *DelayedMI;
1063 // "added after" instructions of the delayed instr
1064 std::vector<MachineInstr *> &DelayedAft=AddedInstrMap[DelayedMI].InstrnsAfter;
1066 // go thru all the "added after instructions" of the original instruction
1067 // and append them to the "added after instructions" of the delayed
1069 DelayedAft.insert(DelayedAft.end(), OrigAft.begin(), OrigAft.end());
1071 // empty the "added after instructions" of the original instruction
1076 void PhyRegAlloc::colorIncomingArgs()
1078 MRI.colorMethodArgs(Fn, *LRI, AddedInstrAtEntry.InstrnsBefore,
1079 AddedInstrAtEntry.InstrnsAfter);
1083 /// Determine whether the suggested color of each live range is really usable,
1084 /// and then call its setSuggestedColorUsable() method to record the answer. A
1085 /// suggested color is NOT usable when the suggested color is volatile AND
1086 /// when there are call interferences.
1088 void PhyRegAlloc::markUnusableSugColors()
1090 LiveRangeMapType::const_iterator HMI = (LRI->getLiveRangeMap())->begin();
1091 LiveRangeMapType::const_iterator HMIEnd = (LRI->getLiveRangeMap())->end();
1093 for (; HMI != HMIEnd ; ++HMI ) {
1095 LiveRange *L = HMI->second; // get the LiveRange
1096 if (L && L->hasSuggestedColor ())
1097 L->setSuggestedColorUsable
1098 (!(MRI.isRegVolatile (L->getRegClassID (), L->getSuggestedColor ())
1099 && L->isCallInterference ()));
1101 } // for all LR's in hash map
1105 /// For each live range that is spilled, allocates a new spill position on the
1106 /// stack, and set the stack offsets of the live range that will be spilled to
1107 /// that position. This must be called just after coloring the LRs.
1109 void PhyRegAlloc::allocateStackSpace4SpilledLRs() {
1110 if (DEBUG_RA) std::cerr << "\nSetting LR stack offsets for spills...\n";
1112 LiveRangeMapType::const_iterator HMI = LRI->getLiveRangeMap()->begin();
1113 LiveRangeMapType::const_iterator HMIEnd = LRI->getLiveRangeMap()->end();
1115 for ( ; HMI != HMIEnd ; ++HMI) {
1116 if (HMI->first && HMI->second) {
1117 LiveRange *L = HMI->second; // get the LiveRange
1118 if (L->isMarkedForSpill()) { // NOTE: allocating size of long Type **
1119 int stackOffset = MF->getInfo()->allocateSpilledValue(Type::LongTy);
1120 L->setSpillOffFromFP(stackOffset);
1122 std::cerr << " LR# " << L->getUserIGNode()->getIndex()
1123 << ": stack-offset = " << stackOffset << "\n";
1126 } // for all LR's in hash map
1130 void PhyRegAlloc::saveStateForValue (std::vector<AllocInfo> &state,
1131 const Value *V, int Insn, int Opnd) {
1132 LiveRangeMapType::const_iterator HMI = LRI->getLiveRangeMap ()->find (V);
1133 LiveRangeMapType::const_iterator HMIEnd = LRI->getLiveRangeMap ()->end ();
1134 AllocInfo::AllocStateTy AllocState = AllocInfo::NotAllocated;
1136 if ((HMI != HMIEnd) && HMI->second) {
1137 LiveRange *L = HMI->second;
1138 assert ((L->hasColor () || L->isMarkedForSpill ())
1139 && "Live range exists but not colored or spilled");
1140 if (L->hasColor ()) {
1141 AllocState = AllocInfo::Allocated;
1142 Placement = MRI.getUnifiedRegNum (L->getRegClassID (),
1144 } else if (L->isMarkedForSpill ()) {
1145 AllocState = AllocInfo::Spilled;
1146 assert (L->hasSpillOffset ()
1147 && "Live range marked for spill but has no spill offset");
1148 Placement = L->getSpillOffFromFP ();
1151 state.push_back (AllocInfo (Insn, Opnd, AllocState, Placement));
1155 /// Save the global register allocation decisions made by the register
1156 /// allocator so that they can be accessed later (sort of like "poor man's
1159 void PhyRegAlloc::saveState () {
1160 std::vector<AllocInfo> &state = FnAllocState[Fn];
1161 unsigned ArgNum = 0;
1162 // Arguments encoded as instruction # -1
1163 for (Function::const_aiterator i=Fn->abegin (), e=Fn->aend (); i != e; ++i) {
1164 const Argument *Arg = &*i;
1165 saveStateForValue (state, Arg, -1, ArgNum);
1168 unsigned InstCount = 0;
1169 // Instructions themselves encoded as operand # -1
1170 for (const_inst_iterator II=inst_begin (Fn), IE=inst_end (Fn); II!=IE; ++II){
1171 const Instruction *Inst = &*II;
1172 saveStateForValue (state, Inst, InstCount, -1);
1173 if (isa<PHINode> (Inst)) {
1174 MachineCodeForInstruction &MCforPN = MachineCodeForInstruction::get(Inst);
1175 // Last instr should be the copy...figure out what reg it is reading from
1176 if (Value *PhiCpRes = MCforPN.back()->getOperand(0).getVRegValueOrNull()){
1178 std::cerr << "Found Phi copy result: " << PhiCpRes->getName()
1179 << " in: " << *MCforPN.back() << "\n";
1180 saveStateForValue (state, PhiCpRes, InstCount, -2);
1188 /// Dump the saved state filled in by saveState() out to stderr. Only
1189 /// used when debugging.
1191 void PhyRegAlloc::dumpSavedState () {
1192 std::vector<AllocInfo> &state = FnAllocState[Fn];
1194 for (Function::const_aiterator i=Fn->abegin (), e=Fn->aend (); i != e; ++i) {
1195 const Argument *Arg = &*i;
1196 std::cerr << "Argument: " << *Arg << "\n"
1197 << "FnAllocState:\n";
1198 for (unsigned i = 0; i < state.size (); ++i) {
1199 AllocInfo &S = state[i];
1200 if (S.Instruction == -1 && S.Operand == ArgNum)
1201 std::cerr << " " << S << "\n";
1203 std::cerr << "----------\n";
1207 for (const_inst_iterator II=inst_begin (Fn), IE=inst_end (Fn); II!=IE; ++II) {
1208 const Instruction *I = &*II;
1209 MachineCodeForInstruction &Instrs = MachineCodeForInstruction::get (I);
1210 std::cerr << "Instruction: " << *I
1211 << "MachineCodeForInstruction:\n";
1212 for (unsigned i = 0, n = Instrs.size (); i != n; ++i)
1213 std::cerr << " " << *Instrs[i];
1214 std::cerr << "FnAllocState:\n";
1215 for (unsigned i = 0; i < state.size (); ++i) {
1216 AllocInfo &S = state[i];
1217 if (Insn == S.Instruction)
1218 std::cerr << " " << S << "\n";
1220 std::cerr << "----------\n";
1226 bool PhyRegAlloc::doFinalization (Module &M) {
1227 if (SaveRegAllocState) finishSavingState (M);
1232 /// Finish the job of saveState(), by collapsing FnAllocState into an LLVM
1233 /// Constant and stuffing it inside the Module.
1235 /// FIXME: There should be other, better ways of storing the saved
1236 /// state; this one is cumbersome and does not work well with the JIT.
1238 void PhyRegAlloc::finishSavingState (Module &M) {
1240 std::cerr << "---- Saving reg. alloc state; SaveStateToModule = "
1241 << SaveStateToModule << " ----\n";
1243 // If saving state into the module, just copy new elements to the
1245 if (!SaveStateToModule) {
1246 ExportedFnAllocState = FnAllocState;
1247 // FIXME: should ONLY copy new elements in FnAllocState
1251 // Convert FnAllocState to a single Constant array and add it
1253 ArrayType *AT = ArrayType::get (AllocInfo::getConstantType (), 0);
1254 std::vector<const Type *> TV;
1255 TV.push_back (Type::UIntTy);
1257 PointerType *PT = PointerType::get (StructType::get (TV));
1259 std::vector<Constant *> allstate;
1260 for (Module::iterator I = M.begin (), E = M.end (); I != E; ++I) {
1262 if (F->isExternal ()) continue;
1263 if (FnAllocState.find (F) == FnAllocState.end ()) {
1264 allstate.push_back (ConstantPointerNull::get (PT));
1266 std::vector<AllocInfo> &state = FnAllocState[F];
1268 // Convert state into an LLVM ConstantArray, and put it in a
1269 // ConstantStruct (named S) along with its size.
1270 std::vector<Constant *> stateConstants;
1271 for (unsigned i = 0, s = state.size (); i != s; ++i)
1272 stateConstants.push_back (state[i].toConstant ());
1273 unsigned Size = stateConstants.size ();
1274 ArrayType *AT = ArrayType::get (AllocInfo::getConstantType (), Size);
1275 std::vector<const Type *> TV;
1276 TV.push_back (Type::UIntTy);
1278 StructType *ST = StructType::get (TV);
1279 std::vector<Constant *> CV;
1280 CV.push_back (ConstantUInt::get (Type::UIntTy, Size));
1281 CV.push_back (ConstantArray::get (AT, stateConstants));
1282 Constant *S = ConstantStruct::get (ST, CV);
1284 GlobalVariable *GV =
1285 new GlobalVariable (ST, true,
1286 GlobalValue::InternalLinkage, S,
1287 F->getName () + ".regAllocState", &M);
1289 // Have: { uint, [Size x { uint, int, uint, int }] } *
1290 // Cast it to: { uint, [0 x { uint, int, uint, int }] } *
1291 Constant *CE = ConstantExpr::getCast (ConstantPointerRef::get (GV), PT);
1292 allstate.push_back (CE);
1296 unsigned Size = allstate.size ();
1297 // Final structure type is:
1298 // { uint, [Size x { uint, [0 x { uint, int, uint, int }] } *] }
1299 std::vector<const Type *> TV2;
1300 TV2.push_back (Type::UIntTy);
1301 ArrayType *AT2 = ArrayType::get (PT, Size);
1302 TV2.push_back (AT2);
1303 StructType *ST2 = StructType::get (TV2);
1304 std::vector<Constant *> CV2;
1305 CV2.push_back (ConstantUInt::get (Type::UIntTy, Size));
1306 CV2.push_back (ConstantArray::get (AT2, allstate));
1307 new GlobalVariable (ST2, true, GlobalValue::ExternalLinkage,
1308 ConstantStruct::get (ST2, CV2), "_llvm_regAllocState",
1313 /// Allocate registers for the machine code previously generated for F using
1314 /// the graph-coloring algorithm.
1316 bool PhyRegAlloc::runOnFunction (Function &F) {
1318 std::cerr << "\n********* Function "<< F.getName () << " ***********\n";
1321 MF = &MachineFunction::get (Fn);
1322 LVI = &getAnalysis<FunctionLiveVarInfo> ();
1323 LRI = new LiveRangeInfo (Fn, TM, RegClassList);
1324 LoopDepthCalc = &getAnalysis<LoopInfo> ();
1326 // Create each RegClass for the target machine and add it to the
1327 // RegClassList. This must be done before calling constructLiveRanges().
1328 for (unsigned rc = 0; rc != NumOfRegClasses; ++rc)
1329 RegClassList.push_back (new RegClass (Fn, &TM.getRegInfo (),
1330 MRI.getMachineRegClass (rc)));
1332 LRI->constructLiveRanges(); // create LR info
1333 if (DEBUG_RA >= RA_DEBUG_LiveRanges)
1334 LRI->printLiveRanges();
1336 createIGNodeListsAndIGs(); // create IGNode list and IGs
1338 buildInterferenceGraphs(); // build IGs in all reg classes
1340 if (DEBUG_RA >= RA_DEBUG_LiveRanges) {
1341 // print all LRs in all reg classes
1342 for ( unsigned rc=0; rc < NumOfRegClasses ; rc++)
1343 RegClassList[rc]->printIGNodeList();
1345 // print IGs in all register classes
1346 for ( unsigned rc=0; rc < NumOfRegClasses ; rc++)
1347 RegClassList[rc]->printIG();
1350 LRI->coalesceLRs(); // coalesce all live ranges
1352 if (DEBUG_RA >= RA_DEBUG_LiveRanges) {
1353 // print all LRs in all reg classes
1354 for (unsigned rc=0; rc < NumOfRegClasses; rc++)
1355 RegClassList[rc]->printIGNodeList();
1357 // print IGs in all register classes
1358 for (unsigned rc=0; rc < NumOfRegClasses; rc++)
1359 RegClassList[rc]->printIG();
1362 // mark un-usable suggested color before graph coloring algorithm.
1363 // When this is done, the graph coloring algo will not reserve
1364 // suggested color unnecessarily - they can be used by another LR
1365 markUnusableSugColors();
1367 // color all register classes using the graph coloring algo
1368 for (unsigned rc=0; rc < NumOfRegClasses ; rc++)
1369 RegClassList[rc]->colorAllRegs();
1371 // After graph coloring, if some LRs did not receive a color (i.e, spilled)
1372 // a position for such spilled LRs
1373 allocateStackSpace4SpilledLRs();
1375 // Reset the temp. area on the stack before use by the first instruction.
1376 // This will also happen after updating each instruction.
1377 MF->getInfo()->popAllTempValues();
1379 // color incoming args - if the correct color was not received
1380 // insert code to copy to the correct register
1381 colorIncomingArgs();
1383 // Save register allocation state for this function in a Constant.
1384 if (SaveRegAllocState) {
1388 // Now update the machine code with register names and add any additional
1389 // code inserted by the register allocator to the instruction stream.
1390 updateMachineCode();
1392 if (SaveRegAllocState) {
1393 if (DEBUG_RA) // Check our work.
1395 if (!SaveStateToModule)
1396 finishSavingState (const_cast<Module&> (*Fn->getParent ()));
1400 std::cerr << "\n**** Machine Code After Register Allocation:\n\n";
1404 // Tear down temporary data structures
1405 for (unsigned rc = 0; rc < NumOfRegClasses; ++rc)
1406 delete RegClassList[rc];
1407 RegClassList.clear ();
1408 AddedInstrMap.clear ();
1409 OperandsColoredMap.clear ();
1410 ScratchRegsUsed.clear ();
1411 AddedInstrAtEntry.clear ();
1414 if (DEBUG_RA) std::cerr << "\nRegister allocation complete!\n";
1415 return false; // Function was not modified
1418 } // End llvm namespace