1 //===-- PhyRegAlloc.cpp ---------------------------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Traditional graph-coloring global register allocator currently used
11 // by the SPARC back-end.
13 // NOTE: This register allocator has some special support
14 // for the Reoptimizer, such as not saving some registers on calls to
15 // the first-level instrumentation function.
17 // NOTE 2: This register allocator can save its state in a global
18 // variable in the module it's working on. This feature is not
19 // thread-safe; if you have doubts, leave it turned off.
21 //===----------------------------------------------------------------------===//
23 #include "AllocInfo.h"
25 #include "PhyRegAlloc.h"
26 #include "RegAllocCommon.h"
28 #include "llvm/Constants.h"
29 #include "llvm/DerivedTypes.h"
30 #include "llvm/iOther.h"
31 #include "llvm/Module.h"
32 #include "llvm/Type.h"
33 #include "llvm/Analysis/LoopInfo.h"
34 #include "llvm/CodeGen/FunctionLiveVarInfo.h"
35 #include "llvm/CodeGen/InstrSelection.h"
36 #include "llvm/CodeGen/MachineCodeForInstruction.h"
37 #include "llvm/CodeGen/MachineFunction.h"
38 #include "llvm/CodeGen/MachineFunctionInfo.h"
39 #include "llvm/CodeGen/MachineInstr.h"
40 #include "llvm/CodeGen/MachineInstrBuilder.h"
41 #include "llvm/CodeGen/MachineInstrAnnot.h"
42 #include "llvm/CodeGen/Passes.h"
43 #include "llvm/Support/InstIterator.h"
44 #include "llvm/Target/TargetInstrInfo.h"
45 #include "Support/CommandLine.h"
46 #include "Support/SetOperations.h"
47 #include "Support/STLExtras.h"
52 RegAllocDebugLevel_t DEBUG_RA;
54 /// The reoptimizer wants to be able to grovel through the register
55 /// allocator's state after it has done its job. This is a hack.
57 PhyRegAlloc::SavedStateMapTy ExportedFnAllocState;
58 const bool SaveStateToModule = true;
60 static cl::opt<RegAllocDebugLevel_t, true>
61 DRA_opt("dregalloc", cl::Hidden, cl::location(DEBUG_RA),
62 cl::desc("enable register allocation debugging information"),
64 clEnumValN(RA_DEBUG_None , "n", "disable debug output"),
65 clEnumValN(RA_DEBUG_Results, "y", "debug output for allocation results"),
66 clEnumValN(RA_DEBUG_Coloring, "c", "debug output for graph coloring step"),
67 clEnumValN(RA_DEBUG_Interference,"ig","debug output for interference graphs"),
68 clEnumValN(RA_DEBUG_LiveRanges , "lr","debug output for live ranges"),
69 clEnumValN(RA_DEBUG_Verbose, "v", "extra debug output"),
73 SaveRegAllocState("save-ra-state", cl::Hidden,
74 cl::desc("write reg. allocator state into module"));
76 FunctionPass *getRegisterAllocator(TargetMachine &T) {
77 return new PhyRegAlloc (T);
80 void PhyRegAlloc::getAnalysisUsage(AnalysisUsage &AU) const {
81 AU.addRequired<LoopInfo> ();
82 AU.addRequired<FunctionLiveVarInfo> ();
86 /// Initialize interference graphs (one in each reg class) and IGNodeLists
87 /// (one in each IG). The actual nodes will be pushed later.
89 void PhyRegAlloc::createIGNodeListsAndIGs() {
90 if (DEBUG_RA >= RA_DEBUG_LiveRanges) std::cerr << "Creating LR lists ...\n";
92 LiveRangeMapType::const_iterator HMI = LRI->getLiveRangeMap()->begin();
93 LiveRangeMapType::const_iterator HMIEnd = LRI->getLiveRangeMap()->end();
95 for (; HMI != HMIEnd ; ++HMI ) {
97 LiveRange *L = HMI->second; // get the LiveRange
100 std::cerr << "\n**** ?!?WARNING: NULL LIVE RANGE FOUND FOR: "
101 << RAV(HMI->first) << "****\n";
105 // if the Value * is not null, and LR is not yet written to the IGNodeList
106 if (!(L->getUserIGNode()) ) {
107 RegClass *const RC = // RegClass of first value in the LR
108 RegClassList[ L->getRegClassID() ];
109 RC->addLRToIG(L); // add this LR to an IG
115 for ( unsigned rc=0; rc < NumOfRegClasses ; rc++)
116 RegClassList[rc]->createInterferenceGraph();
118 if (DEBUG_RA >= RA_DEBUG_LiveRanges) std::cerr << "LRLists Created!\n";
122 /// Add all interferences for a given instruction. Interference occurs only
123 /// if the LR of Def (Inst or Arg) is of the same reg class as that of live
124 /// var. The live var passed to this function is the LVset AFTER the
127 void PhyRegAlloc::addInterference(const Value *Def, const ValueSet *LVSet,
129 ValueSet::const_iterator LIt = LVSet->begin();
131 // get the live range of instruction
132 const LiveRange *const LROfDef = LRI->getLiveRangeForValue( Def );
134 IGNode *const IGNodeOfDef = LROfDef->getUserIGNode();
135 assert( IGNodeOfDef );
137 RegClass *const RCOfDef = LROfDef->getRegClass();
139 // for each live var in live variable set
140 for ( ; LIt != LVSet->end(); ++LIt) {
142 if (DEBUG_RA >= RA_DEBUG_Verbose)
143 std::cerr << "< Def=" << RAV(Def) << ", Lvar=" << RAV(*LIt) << "> ";
145 // get the live range corresponding to live var
146 LiveRange *LROfVar = LRI->getLiveRangeForValue(*LIt);
148 // LROfVar can be null if it is a const since a const
149 // doesn't have a dominating def - see Assumptions above
151 if (LROfDef != LROfVar) // do not set interf for same LR
152 if (RCOfDef == LROfVar->getRegClass()) // 2 reg classes are the same
153 RCOfDef->setInterference( LROfDef, LROfVar);
158 /// For a call instruction, this method sets the CallInterference flag in
159 /// the LR of each variable live in the Live Variable Set live after the
160 /// call instruction (except the return value of the call instruction - since
161 /// the return value does not interfere with that call itself).
163 void PhyRegAlloc::setCallInterferences(const MachineInstr *MInst,
164 const ValueSet *LVSetAft) {
165 if (DEBUG_RA >= RA_DEBUG_Interference)
166 std::cerr << "\n For call inst: " << *MInst;
168 // for each live var in live variable set after machine inst
169 for (ValueSet::const_iterator LIt = LVSetAft->begin(), LEnd = LVSetAft->end();
170 LIt != LEnd; ++LIt) {
172 // get the live range corresponding to live var
173 LiveRange *const LR = LRI->getLiveRangeForValue(*LIt );
175 // LR can be null if it is a const since a const
176 // doesn't have a dominating def - see Assumptions above
178 if (DEBUG_RA >= RA_DEBUG_Interference) {
179 std::cerr << "\n\tLR after Call: ";
182 LR->setCallInterference();
183 if (DEBUG_RA >= RA_DEBUG_Interference) {
184 std::cerr << "\n ++After adding call interference for LR: " ;
191 // Now find the LR of the return value of the call
192 // We do this because, we look at the LV set *after* the instruction
193 // to determine, which LRs must be saved across calls. The return value
194 // of the call is live in this set - but it does not interfere with call
195 // (i.e., we can allocate a volatile register to the return value)
196 CallArgsDescriptor* argDesc = CallArgsDescriptor::get(MInst);
198 if (const Value *RetVal = argDesc->getReturnValue()) {
199 LiveRange *RetValLR = LRI->getLiveRangeForValue( RetVal );
200 assert( RetValLR && "No LR for RetValue of call");
201 RetValLR->clearCallInterference();
204 // If the CALL is an indirect call, find the LR of the function pointer.
205 // That has a call interference because it conflicts with outgoing args.
206 if (const Value *AddrVal = argDesc->getIndirectFuncPtr()) {
207 LiveRange *AddrValLR = LRI->getLiveRangeForValue( AddrVal );
208 assert( AddrValLR && "No LR for indirect addr val of call");
209 AddrValLR->setCallInterference();
214 /// Create interferences in the IG of each RegClass, and calculate the spill
215 /// cost of each Live Range (it is done in this method to save another pass
218 void PhyRegAlloc::buildInterferenceGraphs() {
219 if (DEBUG_RA >= RA_DEBUG_Interference)
220 std::cerr << "Creating interference graphs ...\n";
222 unsigned BBLoopDepthCost;
223 for (MachineFunction::iterator BBI = MF->begin(), BBE = MF->end();
225 const MachineBasicBlock &MBB = *BBI;
226 const BasicBlock *BB = MBB.getBasicBlock();
228 // find the 10^(loop_depth) of this BB
229 BBLoopDepthCost = (unsigned)pow(10.0, LoopDepthCalc->getLoopDepth(BB));
231 // get the iterator for machine instructions
232 MachineBasicBlock::const_iterator MII = MBB.begin();
234 // iterate over all the machine instructions in BB
235 for ( ; MII != MBB.end(); ++MII) {
236 const MachineInstr *MInst = MII;
238 // get the LV set after the instruction
239 const ValueSet &LVSetAI = LVI->getLiveVarSetAfterMInst(MInst, BB);
240 bool isCallInst = TM.getInstrInfo().isCall(MInst->getOpcode());
243 // set the isCallInterference flag of each live range which extends
244 // across this call instruction. This information is used by graph
245 // coloring algorithm to avoid allocating volatile colors to live ranges
246 // that span across calls (since they have to be saved/restored)
247 setCallInterferences(MInst, &LVSetAI);
250 // iterate over all MI operands to find defs
251 for (MachineInstr::const_val_op_iterator OpI = MInst->begin(),
252 OpE = MInst->end(); OpI != OpE; ++OpI) {
253 if (OpI.isDef()) // create a new LR since def
254 addInterference(*OpI, &LVSetAI, isCallInst);
256 // Calculate the spill cost of each live range
257 LiveRange *LR = LRI->getLiveRangeForValue(*OpI);
258 if (LR) LR->addSpillCost(BBLoopDepthCost);
261 // Mark all operands of pseudo-instructions as interfering with one
262 // another. This must be done because pseudo-instructions may be
263 // expanded to multiple instructions by the assembler, so all the
264 // operands must get distinct registers.
265 if (TM.getInstrInfo().isPseudoInstr(MInst->getOpcode()))
266 addInterf4PseudoInstr(MInst);
268 // Also add interference for any implicit definitions in a machine
269 // instr (currently, only calls have this).
270 unsigned NumOfImpRefs = MInst->getNumImplicitRefs();
271 for (unsigned z=0; z < NumOfImpRefs; z++)
272 if (MInst->getImplicitOp(z).isDef())
273 addInterference( MInst->getImplicitRef(z), &LVSetAI, isCallInst );
275 } // for all machine instructions in BB
276 } // for all BBs in function
278 // add interferences for function arguments. Since there are no explicit
279 // defs in the function for args, we have to add them manually
280 addInterferencesForArgs();
282 if (DEBUG_RA >= RA_DEBUG_Interference)
283 std::cerr << "Interference graphs calculated!\n";
287 /// Mark all operands of the given MachineInstr as interfering with one
290 void PhyRegAlloc::addInterf4PseudoInstr(const MachineInstr *MInst) {
291 bool setInterf = false;
293 // iterate over MI operands to find defs
294 for (MachineInstr::const_val_op_iterator It1 = MInst->begin(),
295 ItE = MInst->end(); It1 != ItE; ++It1) {
296 const LiveRange *LROfOp1 = LRI->getLiveRangeForValue(*It1);
297 assert((LROfOp1 || It1.isDef()) && "No LR for Def in PSEUDO insruction");
299 MachineInstr::const_val_op_iterator It2 = It1;
300 for (++It2; It2 != ItE; ++It2) {
301 const LiveRange *LROfOp2 = LRI->getLiveRangeForValue(*It2);
304 RegClass *RCOfOp1 = LROfOp1->getRegClass();
305 RegClass *RCOfOp2 = LROfOp2->getRegClass();
307 if (RCOfOp1 == RCOfOp2 ){
308 RCOfOp1->setInterference( LROfOp1, LROfOp2 );
312 } // for all other defs in machine instr
313 } // for all operands in an instruction
315 if (!setInterf && MInst->getNumOperands() > 2) {
316 std::cerr << "\nInterf not set for any operand in pseudo instr:\n";
318 assert(0 && "Interf not set for pseudo instr with > 2 operands" );
323 /// Add interferences for incoming arguments to a function.
325 void PhyRegAlloc::addInterferencesForArgs() {
326 // get the InSet of root BB
327 const ValueSet &InSet = LVI->getInSetOfBB(&Fn->front());
329 for (Function::const_aiterator AI = Fn->abegin(); AI != Fn->aend(); ++AI) {
330 // add interferences between args and LVars at start
331 addInterference(AI, &InSet, false);
333 if (DEBUG_RA >= RA_DEBUG_Interference)
334 std::cerr << " - %% adding interference for argument " << RAV(AI) << "\n";
339 /// The following are utility functions used solely by updateMachineCode and
340 /// the functions that it calls. They should probably be folded back into
341 /// updateMachineCode at some point.
344 // used by: updateMachineCode (1 time), PrependInstructions (1 time)
345 inline void InsertBefore(MachineInstr* newMI, MachineBasicBlock& MBB,
346 MachineBasicBlock::iterator& MII) {
347 MII = MBB.insert(MII, newMI);
351 // used by: AppendInstructions (1 time)
352 inline void InsertAfter(MachineInstr* newMI, MachineBasicBlock& MBB,
353 MachineBasicBlock::iterator& MII) {
354 ++MII; // insert before the next instruction
355 MII = MBB.insert(MII, newMI);
358 // used by: updateMachineCode (2 times)
359 inline void PrependInstructions(std::vector<MachineInstr *> &IBef,
360 MachineBasicBlock& MBB,
361 MachineBasicBlock::iterator& MII,
362 const std::string& msg) {
364 MachineInstr* OrigMI = MII;
365 std::vector<MachineInstr *>::iterator AdIt;
366 for (AdIt = IBef.begin(); AdIt != IBef.end() ; ++AdIt) {
368 if (OrigMI) std::cerr << "For MInst:\n " << *OrigMI;
369 std::cerr << msg << "PREPENDed instr:\n " << **AdIt << "\n";
371 InsertBefore(*AdIt, MBB, MII);
376 // used by: updateMachineCode (1 time)
377 inline void AppendInstructions(std::vector<MachineInstr *> &IAft,
378 MachineBasicBlock& MBB,
379 MachineBasicBlock::iterator& MII,
380 const std::string& msg) {
382 MachineInstr* OrigMI = MII;
383 std::vector<MachineInstr *>::iterator AdIt;
384 for ( AdIt = IAft.begin(); AdIt != IAft.end() ; ++AdIt ) {
386 if (OrigMI) std::cerr << "For MInst:\n " << *OrigMI;
387 std::cerr << msg << "APPENDed instr:\n " << **AdIt << "\n";
389 InsertAfter(*AdIt, MBB, MII);
394 /// Set the registers for operands in the given MachineInstr, if a register was
395 /// successfully allocated. Return true if any of its operands has been marked
398 bool PhyRegAlloc::markAllocatedRegs(MachineInstr* MInst)
400 bool instrNeedsSpills = false;
402 // First, set the registers for operands in the machine instruction
403 // if a register was successfully allocated. Do this first because we
404 // will need to know which registers are already used by this instr'n.
405 for (unsigned OpNum=0; OpNum < MInst->getNumOperands(); ++OpNum) {
406 MachineOperand& Op = MInst->getOperand(OpNum);
407 if (Op.getType() == MachineOperand::MO_VirtualRegister ||
408 Op.getType() == MachineOperand::MO_CCRegister) {
409 const Value *const Val = Op.getVRegValue();
410 if (const LiveRange* LR = LRI->getLiveRangeForValue(Val)) {
411 // Remember if any operand needs spilling
412 instrNeedsSpills |= LR->isMarkedForSpill();
414 // An operand may have a color whether or not it needs spilling
416 MInst->SetRegForOperand(OpNum,
417 MRI.getUnifiedRegNum(LR->getRegClassID(),
421 } // for each operand
423 return instrNeedsSpills;
426 /// Mark allocated registers (using markAllocatedRegs()) on the instruction
427 /// that MII points to. Then, if it's a call instruction, insert caller-saving
428 /// code before and after it. Finally, insert spill code before and after it,
429 /// using insertCode4SpilledLR().
431 void PhyRegAlloc::updateInstruction(MachineBasicBlock::iterator& MII,
432 MachineBasicBlock &MBB) {
433 MachineInstr* MInst = MII;
434 unsigned Opcode = MInst->getOpcode();
436 // Reset tmp stack positions so they can be reused for each machine instr.
437 MF->getInfo()->popAllTempValues();
439 // Mark the operands for which regs have been allocated.
440 bool instrNeedsSpills = markAllocatedRegs(MII);
443 // Mark that the operands have been updated. Later,
444 // setRelRegsUsedByThisInst() is called to find registers used by each
445 // MachineInst, and it should not be used for an instruction until
446 // this is done. This flag just serves as a sanity check.
447 OperandsColoredMap[MInst] = true;
450 // Now insert caller-saving code before/after the call.
451 // Do this before inserting spill code since some registers must be
452 // used by save/restore and spill code should not use those registers.
453 if (TM.getInstrInfo().isCall(Opcode)) {
454 AddedInstrns &AI = AddedInstrMap[MInst];
455 insertCallerSavingCode(AI.InstrnsBefore, AI.InstrnsAfter, MInst,
456 MBB.getBasicBlock());
459 // Now insert spill code for remaining operands not allocated to
460 // registers. This must be done even for call return instructions
461 // since those are not handled by the special code above.
462 if (instrNeedsSpills)
463 for (unsigned OpNum=0; OpNum < MInst->getNumOperands(); ++OpNum) {
464 MachineOperand& Op = MInst->getOperand(OpNum);
465 if (Op.getType() == MachineOperand::MO_VirtualRegister ||
466 Op.getType() == MachineOperand::MO_CCRegister) {
467 const Value* Val = Op.getVRegValue();
468 if (const LiveRange *LR = LRI->getLiveRangeForValue(Val))
469 if (LR->isMarkedForSpill())
470 insertCode4SpilledLR(LR, MII, MBB, OpNum);
472 } // for each operand
475 /// Iterate over all the MachineBasicBlocks in the current function and set
476 /// the allocated registers for each instruction (using updateInstruction()),
477 /// after register allocation is complete. Then move code out of delay slots.
479 void PhyRegAlloc::updateMachineCode()
481 // Insert any instructions needed at method entry
482 MachineBasicBlock::iterator MII = MF->front().begin();
483 PrependInstructions(AddedInstrAtEntry.InstrnsBefore, MF->front(), MII,
484 "At function entry: \n");
485 assert(AddedInstrAtEntry.InstrnsAfter.empty() &&
486 "InstrsAfter should be unnecessary since we are just inserting at "
487 "the function entry point here.");
489 for (MachineFunction::iterator BBI = MF->begin(), BBE = MF->end();
491 MachineBasicBlock &MBB = *BBI;
493 // Iterate over all machine instructions in BB and mark operands with
494 // their assigned registers or insert spill code, as appropriate.
495 // Also, fix operands of call/return instructions.
496 for (MachineBasicBlock::iterator MII = MBB.begin(); MII != MBB.end(); ++MII)
497 if (! TM.getInstrInfo().isDummyPhiInstr(MII->getOpcode()))
498 updateInstruction(MII, MBB);
500 // Now, move code out of delay slots of branches and returns if needed.
501 // (Also, move "after" code from calls to the last delay slot instruction.)
502 // Moving code out of delay slots is needed in 2 situations:
503 // (1) If this is a branch and it needs instructions inserted after it,
504 // move any existing instructions out of the delay slot so that the
505 // instructions can go into the delay slot. This only supports the
506 // case that #instrsAfter <= #delay slots.
508 // (2) If any instruction in the delay slot needs
509 // instructions inserted, move it out of the delay slot and before the
510 // branch because putting code before or after it would be VERY BAD!
512 // If the annul bit of the branch is set, neither of these is legal!
513 // If so, we need to handle spill differently but annulling is not yet used.
514 for (MachineBasicBlock::iterator MII = MBB.begin(); MII != MBB.end(); ++MII)
515 if (unsigned delaySlots =
516 TM.getInstrInfo().getNumDelaySlots(MII->getOpcode())) {
517 MachineBasicBlock::iterator DelaySlotMI = MII; ++DelaySlotMI;
518 assert(DelaySlotMI != MBB.end() && "no instruction for delay slot");
520 // Check the 2 conditions above:
521 // (1) Does a branch need instructions added after it?
522 // (2) O/w does delay slot instr. need instrns before or after?
523 bool isBranch = (TM.getInstrInfo().isBranch(MII->getOpcode()) ||
524 TM.getInstrInfo().isReturn(MII->getOpcode()));
525 bool cond1 = (isBranch &&
526 AddedInstrMap.count(MII) &&
527 AddedInstrMap[MII].InstrnsAfter.size() > 0);
528 bool cond2 = (AddedInstrMap.count(DelaySlotMI) &&
529 (AddedInstrMap[DelaySlotMI].InstrnsBefore.size() > 0 ||
530 AddedInstrMap[DelaySlotMI].InstrnsAfter.size() > 0));
532 if (cond1 || cond2) {
533 assert((MII->getOpCodeFlags() & AnnulFlag) == 0 &&
534 "FIXME: Moving an annulled delay slot instruction!");
535 assert(delaySlots==1 &&
536 "InsertBefore does not yet handle >1 delay slots!");
539 std::cerr << "\nRegAlloc: Moved instr. with added code: "
541 << " out of delay slots of instr: " << *MII;
544 // move instruction before branch
545 MBB.insert(MII, MBB.remove(DelaySlotMI));
547 // On cond1 we are done (we already moved the
548 // instruction out of the delay slot). On cond2 we need
549 // to insert a nop in place of the moved instruction
551 MBB.insert(MII, BuildMI(TM.getInstrInfo().getNOPOpCode(),1));
555 // For non-branch instr with delay slots (probably a call), move
556 // InstrAfter to the instr. in the last delay slot.
557 MachineBasicBlock::iterator tmp = MII;
558 std::advance(tmp, delaySlots);
559 move2DelayedInstr(MII, tmp);
563 // Finally iterate over all instructions in BB and insert before/after
564 for (MachineBasicBlock::iterator MII=MBB.begin(); MII != MBB.end(); ++MII) {
565 MachineInstr *MInst = MII;
567 // do not process Phis
568 if (TM.getInstrInfo().isDummyPhiInstr(MInst->getOpcode()))
571 // if there are any added instructions...
572 if (AddedInstrMap.count(MInst)) {
573 AddedInstrns &CallAI = AddedInstrMap[MInst];
576 bool isBranch = (TM.getInstrInfo().isBranch(MInst->getOpcode()) ||
577 TM.getInstrInfo().isReturn(MInst->getOpcode()));
579 AddedInstrMap[MInst].InstrnsAfter.size() <=
580 TM.getInstrInfo().getNumDelaySlots(MInst->getOpcode())) &&
581 "Cannot put more than #delaySlots instrns after "
582 "branch or return! Need to handle temps differently.");
586 // Temporary sanity checking code to detect whether the same machine
587 // instruction is ever inserted twice before/after a call.
588 // I suspect this is happening but am not sure. --Vikram, 7/1/03.
589 std::set<const MachineInstr*> instrsSeen;
590 for (int i = 0, N = CallAI.InstrnsBefore.size(); i < N; ++i) {
591 assert(instrsSeen.count(CallAI.InstrnsBefore[i]) == 0 &&
592 "Duplicate machine instruction in InstrnsBefore!");
593 instrsSeen.insert(CallAI.InstrnsBefore[i]);
595 for (int i = 0, N = CallAI.InstrnsAfter.size(); i < N; ++i) {
596 assert(instrsSeen.count(CallAI.InstrnsAfter[i]) == 0 &&
597 "Duplicate machine instruction in InstrnsBefore/After!");
598 instrsSeen.insert(CallAI.InstrnsAfter[i]);
602 // Now add the instructions before/after this MI.
603 // We do this here to ensure that spill for an instruction is inserted
604 // as close as possible to an instruction (see above insertCode4Spill)
605 if (! CallAI.InstrnsBefore.empty())
606 PrependInstructions(CallAI.InstrnsBefore, MBB, MII,"");
608 if (! CallAI.InstrnsAfter.empty())
609 AppendInstructions(CallAI.InstrnsAfter, MBB, MII,"");
611 } // if there are any added instructions
612 } // for each machine instruction
617 /// Insert spill code for AN operand whose LR was spilled. May be called
618 /// repeatedly for a single MachineInstr if it has many spilled operands. On
619 /// each call, it finds a register which is not live at that instruction and
620 /// also which is not used by other spilled operands of the same
621 /// instruction. Then it uses this register temporarily to accommodate the
624 void PhyRegAlloc::insertCode4SpilledLR(const LiveRange *LR,
625 MachineBasicBlock::iterator& MII,
626 MachineBasicBlock &MBB,
627 const unsigned OpNum) {
628 MachineInstr *MInst = MII;
629 const BasicBlock *BB = MBB.getBasicBlock();
631 assert((! TM.getInstrInfo().isCall(MInst->getOpcode()) || OpNum == 0) &&
632 "Outgoing arg of a call must be handled elsewhere (func arg ok)");
633 assert(! TM.getInstrInfo().isReturn(MInst->getOpcode()) &&
634 "Return value of a ret must be handled elsewhere");
636 MachineOperand& Op = MInst->getOperand(OpNum);
637 bool isDef = Op.isDef();
638 bool isUse = Op.isUse();
639 unsigned RegType = MRI.getRegTypeForLR(LR);
640 int SpillOff = LR->getSpillOffFromFP();
641 RegClass *RC = LR->getRegClass();
643 // Get the live-variable set to find registers free before this instr.
644 const ValueSet &LVSetBef = LVI->getLiveVarSetBeforeMInst(MInst, BB);
647 // If this instr. is in the delay slot of a branch or return, we need to
648 // include all live variables before that branch or return -- we don't want to
649 // trample those! Verify that the set is included in the LV set before MInst.
650 if (MII != MBB.begin()) {
651 MachineBasicBlock::iterator PredMI = MII;
653 if (unsigned DS = TM.getInstrInfo().getNumDelaySlots(PredMI->getOpcode()))
654 assert(set_difference(LVI->getLiveVarSetBeforeMInst(PredMI), LVSetBef)
655 .empty() && "Live-var set before branch should be included in "
656 "live-var set of each delay slot instruction!");
660 MF->getInfo()->pushTempValue(MRI.getSpilledRegSize(RegType));
662 std::vector<MachineInstr*> MIBef, MIAft;
663 std::vector<MachineInstr*> AdIMid;
665 // Choose a register to hold the spilled value, if one was not preallocated.
666 // This may insert code before and after MInst to free up the value. If so,
667 // this code should be first/last in the spill sequence before/after MInst.
668 int TmpRegU=(LR->hasColor()
669 ? MRI.getUnifiedRegNum(LR->getRegClassID(),LR->getColor())
670 : getUsableUniRegAtMI(RegType, &LVSetBef, MInst, MIBef,MIAft));
672 // Set the operand first so that it this register does not get used
673 // as a scratch register for later calls to getUsableUniRegAtMI below
674 MInst->SetRegForOperand(OpNum, TmpRegU);
676 // get the added instructions for this instruction
677 AddedInstrns &AI = AddedInstrMap[MInst];
679 // We may need a scratch register to copy the spilled value to/from memory.
680 // This may itself have to insert code to free up a scratch register.
681 // Any such code should go before (after) the spill code for a load (store).
682 // The scratch reg is not marked as used because it is only used
683 // for the copy and not used across MInst.
684 int scratchRegType = -1;
686 if (MRI.regTypeNeedsScratchReg(RegType, scratchRegType)) {
687 scratchReg = getUsableUniRegAtMI(scratchRegType, &LVSetBef,
688 MInst, MIBef, MIAft);
689 assert(scratchReg != MRI.getInvalidRegNum());
693 // for a USE, we have to load the value of LR from stack to a TmpReg
694 // and use the TmpReg as one operand of instruction
696 // actual loading instruction(s)
697 MRI.cpMem2RegMI(AdIMid, MRI.getFramePointer(), SpillOff, TmpRegU,
698 RegType, scratchReg);
700 // the actual load should be after the instructions to free up TmpRegU
701 MIBef.insert(MIBef.end(), AdIMid.begin(), AdIMid.end());
705 if (isDef) { // if this is a Def
706 // for a DEF, we have to store the value produced by this instruction
707 // on the stack position allocated for this LR
709 // actual storing instruction(s)
710 MRI.cpReg2MemMI(AdIMid, TmpRegU, MRI.getFramePointer(), SpillOff,
711 RegType, scratchReg);
713 MIAft.insert(MIAft.begin(), AdIMid.begin(), AdIMid.end());
716 // Finally, insert the entire spill code sequences before/after MInst
717 AI.InstrnsBefore.insert(AI.InstrnsBefore.end(), MIBef.begin(), MIBef.end());
718 AI.InstrnsAfter.insert(AI.InstrnsAfter.begin(), MIAft.begin(), MIAft.end());
721 std::cerr << "\nFor Inst:\n " << *MInst;
722 std::cerr << "SPILLED LR# " << LR->getUserIGNode()->getIndex();
723 std::cerr << "; added Instructions:";
724 for_each(MIBef.begin(), MIBef.end(), std::mem_fun(&MachineInstr::dump));
725 for_each(MIAft.begin(), MIAft.end(), std::mem_fun(&MachineInstr::dump));
730 /// Insert caller saving/restoring instructions before/after a call machine
731 /// instruction (before or after any other instructions that were inserted for
735 PhyRegAlloc::insertCallerSavingCode(std::vector<MachineInstr*> &instrnsBefore,
736 std::vector<MachineInstr*> &instrnsAfter,
737 MachineInstr *CallMI,
738 const BasicBlock *BB) {
739 assert(TM.getInstrInfo().isCall(CallMI->getOpcode()));
741 // hash set to record which registers were saved/restored
742 hash_set<unsigned> PushedRegSet;
744 CallArgsDescriptor* argDesc = CallArgsDescriptor::get(CallMI);
746 // if the call is to a instrumentation function, do not insert save and
747 // restore instructions the instrumentation function takes care of save
748 // restore for volatile regs.
750 // FIXME: this should be made general, not specific to the reoptimizer!
751 const Function *Callee = argDesc->getCallInst()->getCalledFunction();
752 bool isLLVMFirstTrigger = Callee && Callee->getName() == "llvm_first_trigger";
754 // Now check if the call has a return value (using argDesc) and if so,
755 // find the LR of the TmpInstruction representing the return value register.
756 // (using the last or second-last *implicit operand* of the call MI).
757 // Insert it to to the PushedRegSet since we must not save that register
758 // and restore it after the call.
759 // We do this because, we look at the LV set *after* the instruction
760 // to determine, which LRs must be saved across calls. The return value
761 // of the call is live in this set - but we must not save/restore it.
762 if (const Value *origRetVal = argDesc->getReturnValue()) {
763 unsigned retValRefNum = (CallMI->getNumImplicitRefs() -
764 (argDesc->getIndirectFuncPtr()? 1 : 2));
765 const TmpInstruction* tmpRetVal =
766 cast<TmpInstruction>(CallMI->getImplicitRef(retValRefNum));
767 assert(tmpRetVal->getOperand(0) == origRetVal &&
768 tmpRetVal->getType() == origRetVal->getType() &&
769 "Wrong implicit ref?");
770 LiveRange *RetValLR = LRI->getLiveRangeForValue(tmpRetVal);
771 assert(RetValLR && "No LR for RetValue of call");
773 if (! RetValLR->isMarkedForSpill())
774 PushedRegSet.insert(MRI.getUnifiedRegNum(RetValLR->getRegClassID(),
775 RetValLR->getColor()));
778 const ValueSet &LVSetAft = LVI->getLiveVarSetAfterMInst(CallMI, BB);
779 ValueSet::const_iterator LIt = LVSetAft.begin();
781 // for each live var in live variable set after machine inst
782 for( ; LIt != LVSetAft.end(); ++LIt) {
783 // get the live range corresponding to live var
784 LiveRange *const LR = LRI->getLiveRangeForValue(*LIt);
786 // LR can be null if it is a const since a const
787 // doesn't have a dominating def - see Assumptions above
789 if (! LR->isMarkedForSpill()) {
790 assert(LR->hasColor() && "LR is neither spilled nor colored?");
791 unsigned RCID = LR->getRegClassID();
792 unsigned Color = LR->getColor();
794 if (MRI.isRegVolatile(RCID, Color) ) {
795 // if this is a call to the first-level reoptimizer
796 // instrumentation entry point, and the register is not
797 // modified by call, don't save and restore it.
798 if (isLLVMFirstTrigger && !MRI.modifiedByCall(RCID, Color))
801 // if the value is in both LV sets (i.e., live before and after
802 // the call machine instruction)
803 unsigned Reg = MRI.getUnifiedRegNum(RCID, Color);
805 // if we haven't already pushed this register...
806 if( PushedRegSet.find(Reg) == PushedRegSet.end() ) {
807 unsigned RegType = MRI.getRegTypeForLR(LR);
809 // Now get two instructions - to push on stack and pop from stack
810 // and add them to InstrnsBefore and InstrnsAfter of the
813 MF->getInfo()->pushTempValue(MRI.getSpilledRegSize(RegType));
815 //---- Insert code for pushing the reg on stack ----------
817 std::vector<MachineInstr*> AdIBef, AdIAft;
819 // We may need a scratch register to copy the saved value
820 // to/from memory. This may itself have to insert code to
821 // free up a scratch register. Any such code should go before
822 // the save code. The scratch register, if any, is by default
823 // temporary and not "used" by the instruction unless the
824 // copy code itself decides to keep the value in the scratch reg.
825 int scratchRegType = -1;
827 if (MRI.regTypeNeedsScratchReg(RegType, scratchRegType))
828 { // Find a register not live in the LVSet before CallMI
829 const ValueSet &LVSetBef =
830 LVI->getLiveVarSetBeforeMInst(CallMI, BB);
831 scratchReg = getUsableUniRegAtMI(scratchRegType, &LVSetBef,
832 CallMI, AdIBef, AdIAft);
833 assert(scratchReg != MRI.getInvalidRegNum());
836 if (AdIBef.size() > 0)
837 instrnsBefore.insert(instrnsBefore.end(),
838 AdIBef.begin(), AdIBef.end());
840 MRI.cpReg2MemMI(instrnsBefore, Reg, MRI.getFramePointer(),
841 StackOff, RegType, scratchReg);
843 if (AdIAft.size() > 0)
844 instrnsBefore.insert(instrnsBefore.end(),
845 AdIAft.begin(), AdIAft.end());
847 //---- Insert code for popping the reg from the stack ----------
851 // We may need a scratch register to copy the saved value
852 // from memory. This may itself have to insert code to
853 // free up a scratch register. Any such code should go
854 // after the save code. As above, scratch is not marked "used".
857 if (MRI.regTypeNeedsScratchReg(RegType, scratchRegType))
858 { // Find a register not live in the LVSet after CallMI
859 scratchReg = getUsableUniRegAtMI(scratchRegType, &LVSetAft,
860 CallMI, AdIBef, AdIAft);
861 assert(scratchReg != MRI.getInvalidRegNum());
864 if (AdIBef.size() > 0)
865 instrnsAfter.insert(instrnsAfter.end(),
866 AdIBef.begin(), AdIBef.end());
868 MRI.cpMem2RegMI(instrnsAfter, MRI.getFramePointer(), StackOff,
869 Reg, RegType, scratchReg);
871 if (AdIAft.size() > 0)
872 instrnsAfter.insert(instrnsAfter.end(),
873 AdIAft.begin(), AdIAft.end());
875 PushedRegSet.insert(Reg);
878 std::cerr << "\nFor call inst:" << *CallMI;
879 std::cerr << " -inserted caller saving instrs: Before:\n\t ";
880 for_each(instrnsBefore.begin(), instrnsBefore.end(),
881 std::mem_fun(&MachineInstr::dump));
882 std::cerr << " -and After:\n\t ";
883 for_each(instrnsAfter.begin(), instrnsAfter.end(),
884 std::mem_fun(&MachineInstr::dump));
886 } // if not already pushed
887 } // if LR has a volatile color
889 } // if there is a LR for Var
890 } // for each value in the LV set after instruction
894 /// Returns the unified register number of a temporary register to be used
895 /// BEFORE MInst. If no register is available, it will pick one and modify
896 /// MIBef and MIAft to contain instructions used to free up this returned
899 int PhyRegAlloc::getUsableUniRegAtMI(const int RegType,
900 const ValueSet *LVSetBef,
902 std::vector<MachineInstr*>& MIBef,
903 std::vector<MachineInstr*>& MIAft) {
904 RegClass* RC = getRegClassByID(MRI.getRegClassIDOfRegType(RegType));
906 int RegU = getUnusedUniRegAtMI(RC, RegType, MInst, LVSetBef);
909 // we couldn't find an unused register. Generate code to free up a reg by
910 // saving it on stack and restoring after the instruction
912 int TmpOff = MF->getInfo()->pushTempValue(MRI.getSpilledRegSize(RegType));
914 RegU = getUniRegNotUsedByThisInst(RC, RegType, MInst);
916 // Check if we need a scratch register to copy this register to memory.
917 int scratchRegType = -1;
918 if (MRI.regTypeNeedsScratchReg(RegType, scratchRegType)) {
919 int scratchReg = getUsableUniRegAtMI(scratchRegType, LVSetBef,
920 MInst, MIBef, MIAft);
921 assert(scratchReg != MRI.getInvalidRegNum());
923 // We may as well hold the value in the scratch register instead
924 // of copying it to memory and back. But we have to mark the
925 // register as used by this instruction, so it does not get used
926 // as a scratch reg. by another operand or anyone else.
927 ScratchRegsUsed.insert(std::make_pair(MInst, scratchReg));
928 MRI.cpReg2RegMI(MIBef, RegU, scratchReg, RegType);
929 MRI.cpReg2RegMI(MIAft, scratchReg, RegU, RegType);
930 } else { // the register can be copied directly to/from memory so do it.
931 MRI.cpReg2MemMI(MIBef, RegU, MRI.getFramePointer(), TmpOff, RegType);
932 MRI.cpMem2RegMI(MIAft, MRI.getFramePointer(), TmpOff, RegU, RegType);
940 /// Returns the register-class register number of a new unused register that
941 /// can be used to accommodate a temporary value. May be called repeatedly
942 /// for a single MachineInstr. On each call, it finds a register which is not
943 /// live at that instruction and which is not used by any spilled operands of
944 /// that instruction.
946 int PhyRegAlloc::getUnusedUniRegAtMI(RegClass *RC, const int RegType,
947 const MachineInstr *MInst,
948 const ValueSet* LVSetBef) {
949 RC->clearColorsUsed(); // Reset array
951 if (LVSetBef == NULL) {
952 LVSetBef = &LVI->getLiveVarSetBeforeMInst(MInst);
953 assert(LVSetBef != NULL && "Unable to get live-var set before MInst?");
956 ValueSet::const_iterator LIt = LVSetBef->begin();
958 // for each live var in live variable set after machine inst
959 for ( ; LIt != LVSetBef->end(); ++LIt) {
960 // Get the live range corresponding to live var, and its RegClass
961 LiveRange *const LRofLV = LRI->getLiveRangeForValue(*LIt );
963 // LR can be null if it is a const since a const
964 // doesn't have a dominating def - see Assumptions above
965 if (LRofLV && LRofLV->getRegClass() == RC && LRofLV->hasColor())
966 RC->markColorsUsed(LRofLV->getColor(),
967 MRI.getRegTypeForLR(LRofLV), RegType);
970 // It is possible that one operand of this MInst was already spilled
971 // and it received some register temporarily. If that's the case,
972 // it is recorded in machine operand. We must skip such registers.
973 setRelRegsUsedByThisInst(RC, RegType, MInst);
975 int unusedReg = RC->getUnusedColor(RegType); // find first unused color
977 return MRI.getUnifiedRegNum(RC->getID(), unusedReg);
983 /// Return the unified register number of a register in class RC which is not
984 /// used by any operands of MInst.
986 int PhyRegAlloc::getUniRegNotUsedByThisInst(RegClass *RC,
988 const MachineInstr *MInst) {
989 RC->clearColorsUsed();
991 setRelRegsUsedByThisInst(RC, RegType, MInst);
993 // find the first unused color
994 int unusedReg = RC->getUnusedColor(RegType);
995 assert(unusedReg >= 0 &&
996 "FATAL: No free register could be found in reg class!!");
998 return MRI.getUnifiedRegNum(RC->getID(), unusedReg);
1002 /// Modify the IsColorUsedArr of register class RC, by setting the bits
1003 /// corresponding to register RegNo. This is a helper method of
1004 /// setRelRegsUsedByThisInst().
1006 static void markRegisterUsed(int RegNo, RegClass *RC, int RegType,
1007 const TargetRegInfo &TRI) {
1008 unsigned classId = 0;
1009 int classRegNum = TRI.getClassRegNum(RegNo, classId);
1010 if (RC->getID() == classId)
1011 RC->markColorsUsed(classRegNum, RegType, RegType);
1014 void PhyRegAlloc::setRelRegsUsedByThisInst(RegClass *RC, int RegType,
1015 const MachineInstr *MI) {
1016 assert(OperandsColoredMap[MI] == true &&
1017 "Illegal to call setRelRegsUsedByThisInst() until colored operands "
1018 "are marked for an instruction.");
1020 // Add the registers already marked as used by the instruction. Both
1021 // explicit and implicit operands are set.
1022 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i)
1023 if (MI->getOperand(i).hasAllocatedReg())
1024 markRegisterUsed(MI->getOperand(i).getAllocatedRegNum(), RC, RegType,MRI);
1026 for (unsigned i = 0, e = MI->getNumImplicitRefs(); i != e; ++i)
1027 if (MI->getImplicitOp(i).hasAllocatedReg())
1028 markRegisterUsed(MI->getImplicitOp(i).getAllocatedRegNum(), RC,
1031 // Add all of the scratch registers that are used to save values across the
1032 // instruction (e.g., for saving state register values).
1033 std::pair<ScratchRegsUsedTy::iterator, ScratchRegsUsedTy::iterator>
1034 IR = ScratchRegsUsed.equal_range(MI);
1035 for (ScratchRegsUsedTy::iterator I = IR.first; I != IR.second; ++I)
1036 markRegisterUsed(I->second, RC, RegType, MRI);
1038 // If there are implicit references, mark their allocated regs as well
1039 for (unsigned z=0; z < MI->getNumImplicitRefs(); z++)
1040 if (const LiveRange*
1041 LRofImpRef = LRI->getLiveRangeForValue(MI->getImplicitRef(z)))
1042 if (LRofImpRef->hasColor())
1043 // this implicit reference is in a LR that received a color
1044 RC->markColorsUsed(LRofImpRef->getColor(),
1045 MRI.getRegTypeForLR(LRofImpRef), RegType);
1049 /// If there are delay slots for an instruction, the instructions added after
1050 /// it must really go after the delayed instruction(s). So, we Move the
1051 /// InstrAfter of that instruction to the corresponding delayed instruction
1052 /// using the following method.
1054 void PhyRegAlloc::move2DelayedInstr(const MachineInstr *OrigMI,
1055 const MachineInstr *DelayedMI)
1057 // "added after" instructions of the original instr
1058 std::vector<MachineInstr *> &OrigAft = AddedInstrMap[OrigMI].InstrnsAfter;
1060 if (DEBUG_RA && OrigAft.size() > 0) {
1061 std::cerr << "\nRegAlloc: Moved InstrnsAfter for: " << *OrigMI;
1062 std::cerr << " to last delay slot instrn: " << *DelayedMI;
1065 // "added after" instructions of the delayed instr
1066 std::vector<MachineInstr *> &DelayedAft=AddedInstrMap[DelayedMI].InstrnsAfter;
1068 // go thru all the "added after instructions" of the original instruction
1069 // and append them to the "added after instructions" of the delayed
1071 DelayedAft.insert(DelayedAft.end(), OrigAft.begin(), OrigAft.end());
1073 // empty the "added after instructions" of the original instruction
1078 void PhyRegAlloc::colorIncomingArgs()
1080 MRI.colorMethodArgs(Fn, *LRI, AddedInstrAtEntry.InstrnsBefore,
1081 AddedInstrAtEntry.InstrnsAfter);
1085 /// Determine whether the suggested color of each live range is really usable,
1086 /// and then call its setSuggestedColorUsable() method to record the answer. A
1087 /// suggested color is NOT usable when the suggested color is volatile AND
1088 /// when there are call interferences.
1090 void PhyRegAlloc::markUnusableSugColors()
1092 LiveRangeMapType::const_iterator HMI = (LRI->getLiveRangeMap())->begin();
1093 LiveRangeMapType::const_iterator HMIEnd = (LRI->getLiveRangeMap())->end();
1095 for (; HMI != HMIEnd ; ++HMI ) {
1097 LiveRange *L = HMI->second; // get the LiveRange
1098 if (L && L->hasSuggestedColor ())
1099 L->setSuggestedColorUsable
1100 (!(MRI.isRegVolatile (L->getRegClassID (), L->getSuggestedColor ())
1101 && L->isCallInterference ()));
1103 } // for all LR's in hash map
1107 /// For each live range that is spilled, allocates a new spill position on the
1108 /// stack, and set the stack offsets of the live range that will be spilled to
1109 /// that position. This must be called just after coloring the LRs.
1111 void PhyRegAlloc::allocateStackSpace4SpilledLRs() {
1112 if (DEBUG_RA) std::cerr << "\nSetting LR stack offsets for spills...\n";
1114 LiveRangeMapType::const_iterator HMI = LRI->getLiveRangeMap()->begin();
1115 LiveRangeMapType::const_iterator HMIEnd = LRI->getLiveRangeMap()->end();
1117 for ( ; HMI != HMIEnd ; ++HMI) {
1118 if (HMI->first && HMI->second) {
1119 LiveRange *L = HMI->second; // get the LiveRange
1120 if (L->isMarkedForSpill()) { // NOTE: allocating size of long Type **
1121 int stackOffset = MF->getInfo()->allocateSpilledValue(Type::LongTy);
1122 L->setSpillOffFromFP(stackOffset);
1124 std::cerr << " LR# " << L->getUserIGNode()->getIndex()
1125 << ": stack-offset = " << stackOffset << "\n";
1128 } // for all LR's in hash map
1132 void PhyRegAlloc::saveStateForValue (std::vector<AllocInfo> &state,
1133 const Value *V, unsigned Insn, int Opnd) {
1134 LiveRangeMapType::const_iterator HMI = LRI->getLiveRangeMap ()->find (V);
1135 LiveRangeMapType::const_iterator HMIEnd = LRI->getLiveRangeMap ()->end ();
1136 AllocInfo::AllocStateTy AllocState = AllocInfo::NotAllocated;
1138 if ((HMI != HMIEnd) && HMI->second) {
1139 LiveRange *L = HMI->second;
1140 assert ((L->hasColor () || L->isMarkedForSpill ())
1141 && "Live range exists but not colored or spilled");
1142 if (L->hasColor ()) {
1143 AllocState = AllocInfo::Allocated;
1144 Placement = MRI.getUnifiedRegNum (L->getRegClassID (),
1146 } else if (L->isMarkedForSpill ()) {
1147 AllocState = AllocInfo::Spilled;
1148 assert (L->hasSpillOffset ()
1149 && "Live range marked for spill but has no spill offset");
1150 Placement = L->getSpillOffFromFP ();
1153 state.push_back (AllocInfo (Insn, Opnd, AllocState, Placement));
1157 /// Save the global register allocation decisions made by the register
1158 /// allocator so that they can be accessed later (sort of like "poor man's
1161 void PhyRegAlloc::saveState () {
1162 std::vector<AllocInfo> &state = FnAllocState[Fn];
1164 for (const_inst_iterator II=inst_begin (Fn), IE=inst_end (Fn); II!=IE; ++II){
1165 saveStateForValue (state, (*II), Insn, -1);
1166 for (unsigned i = 0; i < (*II)->getNumOperands (); ++i) {
1167 const Value *V = (*II)->getOperand (i);
1168 // Don't worry about it unless it's something whose reg. we'll need.
1169 if (!isa<Argument> (V) && !isa<Instruction> (V))
1171 saveStateForValue (state, V, Insn, i);
1178 /// Check the saved state filled in by saveState(), and abort if it looks
1179 /// wrong. Only used when debugging. FIXME: Currently it just prints out
1180 /// the state, which isn't quite as useful.
1182 void PhyRegAlloc::verifySavedState () {
1183 std::vector<AllocInfo> &state = FnAllocState[Fn];
1185 for (const_inst_iterator II=inst_begin (Fn), IE=inst_end (Fn); II!=IE; ++II) {
1186 const Instruction *I = *II;
1187 MachineCodeForInstruction &Instrs = MachineCodeForInstruction::get (I);
1188 std::cerr << "Instruction:\n" << " " << *I << "\n"
1189 << "MachineCodeForInstruction:\n";
1190 for (unsigned i = 0, n = Instrs.size (); i != n; ++i)
1191 std::cerr << " " << *Instrs[i] << "\n";
1192 std::cerr << "FnAllocState:\n";
1193 for (unsigned i = 0; i < state.size (); ++i) {
1194 AllocInfo &S = state[i];
1195 if (Insn == S.Instruction)
1196 std::cerr << " " << S << "\n";
1198 std::cerr << "----------\n";
1204 /// Finish the job of saveState(), by collapsing FnAllocState into an LLVM
1205 /// Constant and stuffing it inside the Module. (NOTE: Soon, there will be
1206 /// other, better ways of storing the saved state; this one is cumbersome and
1207 /// does not work well with the JIT.)
1209 bool PhyRegAlloc::doFinalization (Module &M) {
1210 if (!SaveRegAllocState)
1211 return false; // Nothing to do here, unless we're saving state.
1213 // If saving state into the module, just copy new elements to the
1215 if (!SaveStateToModule) {
1216 ExportedFnAllocState = FnAllocState;
1217 // FIXME: should ONLY copy new elements in FnAllocState
1221 // Convert FnAllocState to a single Constant array and add it
1223 ArrayType *AT = ArrayType::get (AllocInfo::getConstantType (), 0);
1224 std::vector<const Type *> TV;
1225 TV.push_back (Type::UIntTy);
1227 PointerType *PT = PointerType::get (StructType::get (TV));
1229 std::vector<Constant *> allstate;
1230 for (Module::iterator I = M.begin (), E = M.end (); I != E; ++I) {
1232 if (F->isExternal ()) continue;
1233 if (FnAllocState.find (F) == FnAllocState.end ()) {
1234 allstate.push_back (ConstantPointerNull::get (PT));
1236 std::vector<AllocInfo> &state = FnAllocState[F];
1238 // Convert state into an LLVM ConstantArray, and put it in a
1239 // ConstantStruct (named S) along with its size.
1240 std::vector<Constant *> stateConstants;
1241 for (unsigned i = 0, s = state.size (); i != s; ++i)
1242 stateConstants.push_back (state[i].toConstant ());
1243 unsigned Size = stateConstants.size ();
1244 ArrayType *AT = ArrayType::get (AllocInfo::getConstantType (), Size);
1245 std::vector<const Type *> TV;
1246 TV.push_back (Type::UIntTy);
1248 StructType *ST = StructType::get (TV);
1249 std::vector<Constant *> CV;
1250 CV.push_back (ConstantUInt::get (Type::UIntTy, Size));
1251 CV.push_back (ConstantArray::get (AT, stateConstants));
1252 Constant *S = ConstantStruct::get (ST, CV);
1254 GlobalVariable *GV =
1255 new GlobalVariable (ST, true,
1256 GlobalValue::InternalLinkage, S,
1257 F->getName () + ".regAllocState", &M);
1259 // Have: { uint, [Size x { uint, int, uint, int }] } *
1260 // Cast it to: { uint, [0 x { uint, int, uint, int }] } *
1261 Constant *CE = ConstantExpr::getCast (ConstantPointerRef::get (GV), PT);
1262 allstate.push_back (CE);
1266 unsigned Size = allstate.size ();
1267 // Final structure type is:
1268 // { uint, [Size x { uint, [0 x { uint, int, uint, int }] } *] }
1269 std::vector<const Type *> TV2;
1270 TV2.push_back (Type::UIntTy);
1271 ArrayType *AT2 = ArrayType::get (PT, Size);
1272 TV2.push_back (AT2);
1273 StructType *ST2 = StructType::get (TV2);
1274 std::vector<Constant *> CV2;
1275 CV2.push_back (ConstantUInt::get (Type::UIntTy, Size));
1276 CV2.push_back (ConstantArray::get (AT2, allstate));
1277 new GlobalVariable (ST2, true, GlobalValue::ExternalLinkage,
1278 ConstantStruct::get (ST2, CV2), "_llvm_regAllocState",
1280 return false; // No error.
1284 /// Allocate registers for the machine code previously generated for F using
1285 /// the graph-coloring algorithm.
1287 bool PhyRegAlloc::runOnFunction (Function &F) {
1289 std::cerr << "\n********* Function "<< F.getName () << " ***********\n";
1292 MF = &MachineFunction::get (Fn);
1293 LVI = &getAnalysis<FunctionLiveVarInfo> ();
1294 LRI = new LiveRangeInfo (Fn, TM, RegClassList);
1295 LoopDepthCalc = &getAnalysis<LoopInfo> ();
1297 // Create each RegClass for the target machine and add it to the
1298 // RegClassList. This must be done before calling constructLiveRanges().
1299 for (unsigned rc = 0; rc != NumOfRegClasses; ++rc)
1300 RegClassList.push_back (new RegClass (Fn, &TM.getRegInfo (),
1301 MRI.getMachineRegClass (rc)));
1303 LRI->constructLiveRanges(); // create LR info
1304 if (DEBUG_RA >= RA_DEBUG_LiveRanges)
1305 LRI->printLiveRanges();
1307 createIGNodeListsAndIGs(); // create IGNode list and IGs
1309 buildInterferenceGraphs(); // build IGs in all reg classes
1311 if (DEBUG_RA >= RA_DEBUG_LiveRanges) {
1312 // print all LRs in all reg classes
1313 for ( unsigned rc=0; rc < NumOfRegClasses ; rc++)
1314 RegClassList[rc]->printIGNodeList();
1316 // print IGs in all register classes
1317 for ( unsigned rc=0; rc < NumOfRegClasses ; rc++)
1318 RegClassList[rc]->printIG();
1321 LRI->coalesceLRs(); // coalesce all live ranges
1323 if (DEBUG_RA >= RA_DEBUG_LiveRanges) {
1324 // print all LRs in all reg classes
1325 for (unsigned rc=0; rc < NumOfRegClasses; rc++)
1326 RegClassList[rc]->printIGNodeList();
1328 // print IGs in all register classes
1329 for (unsigned rc=0; rc < NumOfRegClasses; rc++)
1330 RegClassList[rc]->printIG();
1333 // mark un-usable suggested color before graph coloring algorithm.
1334 // When this is done, the graph coloring algo will not reserve
1335 // suggested color unnecessarily - they can be used by another LR
1336 markUnusableSugColors();
1338 // color all register classes using the graph coloring algo
1339 for (unsigned rc=0; rc < NumOfRegClasses ; rc++)
1340 RegClassList[rc]->colorAllRegs();
1342 // After graph coloring, if some LRs did not receive a color (i.e, spilled)
1343 // a position for such spilled LRs
1344 allocateStackSpace4SpilledLRs();
1346 // Reset the temp. area on the stack before use by the first instruction.
1347 // This will also happen after updating each instruction.
1348 MF->getInfo()->popAllTempValues();
1350 // color incoming args - if the correct color was not received
1351 // insert code to copy to the correct register
1352 colorIncomingArgs();
1354 // Save register allocation state for this function in a Constant.
1355 if (SaveRegAllocState)
1357 if (DEBUG_RA) { // Check our work.
1358 verifySavedState ();
1361 // Now update the machine code with register names and add any additional
1362 // code inserted by the register allocator to the instruction stream.
1363 updateMachineCode();
1366 std::cerr << "\n**** Machine Code After Register Allocation:\n\n";
1370 // Tear down temporary data structures
1371 for (unsigned rc = 0; rc < NumOfRegClasses; ++rc)
1372 delete RegClassList[rc];
1373 RegClassList.clear ();
1374 AddedInstrMap.clear ();
1375 OperandsColoredMap.clear ();
1376 ScratchRegsUsed.clear ();
1377 AddedInstrAtEntry.clear ();
1380 if (DEBUG_RA) std::cerr << "\nRegister allocation complete!\n";
1381 return false; // Function was not modified
1384 } // End llvm namespace