1 #include "llvm/CodeGen/PhyRegAlloc.h"
3 cl::Enum<RegAllocDebugLevel_t> DEBUG_RA("dregalloc", cl::NoFlags,
4 "enable register allocation debugging information",
5 clEnumValN(RA_DEBUG_None , "n", "disable debug output"),
6 clEnumValN(RA_DEBUG_Normal , "y", "enable debug output"),
7 clEnumValN(RA_DEBUG_Verbose, "v", "enable extra debug output"), 0);
10 //----------------------------------------------------------------------------
11 // Constructor: Init local composite objects and create register classes.
12 //----------------------------------------------------------------------------
13 PhyRegAlloc::PhyRegAlloc(const Method *const M,
14 const TargetMachine& tm,
15 MethodLiveVarInfo *const Lvi)
17 Meth(M), TM(tm), LVI(Lvi), LRI(M, tm, RegClassList),
18 MRI( tm.getRegInfo() ),
19 NumOfRegClasses(MRI.getNumOfRegClasses()),
23 // **TODO: use an actual reserved color list
24 ReservedColorListType *RCL = new ReservedColorListType();
26 // create each RegisterClass and put in RegClassList
27 for( unsigned int rc=0; rc < NumOfRegClasses; rc++)
28 RegClassList.push_back( new RegClass(M, MRI.getMachineRegClass(rc), RCL) );
32 //----------------------------------------------------------------------------
33 // This method initally creates interference graphs (one in each reg class)
34 // and IGNodeList (one in each IG). The actual nodes will be pushed later.
35 //----------------------------------------------------------------------------
37 void PhyRegAlloc::createIGNodeListsAndIGs()
39 if(DEBUG_RA ) cout << "Creating LR lists ..." << endl;
42 LiveRangeMapType::const_iterator HMI = (LRI.getLiveRangeMap())->begin();
45 LiveRangeMapType::const_iterator HMIEnd = (LRI.getLiveRangeMap())->end();
47 for( ; HMI != HMIEnd ; ++HMI ) {
51 LiveRange *L = (*HMI).second; // get the LiveRange
55 cout << "\n*?!?Warning: Null liver range found for: ";
56 printValue( (*HMI).first) ; cout << endl;
60 // if the Value * is not null, and LR
61 // is not yet written to the IGNodeList
62 if( !(L->getUserIGNode()) ) {
64 RegClass *const RC = // RegClass of first value in the LR
65 //RegClassList [MRI.getRegClassIDOfValue(*(L->begin()))];
66 RegClassList[ L->getRegClass()->getID() ];
68 RC-> addLRToIG( L ); // add this LR to an IG
74 for( unsigned int rc=0; rc < NumOfRegClasses ; rc++)
75 RegClassList[ rc ]->createInterferenceGraph();
78 cout << "LRLists Created!" << endl;
83 //----------------------------------------------------------------------------
84 // This method will add all interferences at for a given instruction.
85 // Interence occurs only if the LR of Def (Inst or Arg) is of the same reg
86 // class as that of live var. The live var passed to this function is the
87 // LVset AFTER the instruction
88 //----------------------------------------------------------------------------
90 void PhyRegAlloc::addInterference(const Value *const Def,
91 const LiveVarSet *const LVSet,
92 const bool isCallInst) {
94 LiveVarSet::const_iterator LIt = LVSet->begin();
96 // get the live range of instruction
97 const LiveRange *const LROfDef = LRI.getLiveRangeForValue( Def );
99 IGNode *const IGNodeOfDef = LROfDef->getUserIGNode();
100 assert( IGNodeOfDef );
102 RegClass *const RCOfDef = LROfDef->getRegClass();
104 // for each live var in live variable set
105 for( ; LIt != LVSet->end(); ++LIt) {
108 cout << "< Def="; printValue(Def);
109 cout << ", Lvar="; printValue( *LIt); cout << "> ";
112 // get the live range corresponding to live var
113 LiveRange *const LROfVar = LRI.getLiveRangeForValue(*LIt );
115 // LROfVar can be null if it is a const since a const
116 // doesn't have a dominating def - see Assumptions above
119 if(LROfDef == LROfVar) // do not set interf for same LR
122 // if 2 reg classes are the same set interference
123 if( RCOfDef == LROfVar->getRegClass() ){
124 RCOfDef->setInterference( LROfDef, LROfVar);
128 //the live range of this var interferes with this call
130 LROfVar->addCallInterference( (const Instruction *const) Def );
131 // cout << "\n ++Added Call Interf to set:";
132 // LROfVar->printSet();
135 else if(DEBUG_RA > 1) {
136 // we will not have LRs for values not explicitly allocated in the
137 // instruction stream (e.g., constants)
138 cout << " warning: no live range for " ;
139 printValue( *LIt); cout << endl; }
145 //----------------------------------------------------------------------------
146 // This method will walk thru code and create interferences in the IG of
148 //----------------------------------------------------------------------------
150 void PhyRegAlloc::buildInterferenceGraphs()
153 if(DEBUG_RA) cout << "Creating interference graphs ..." << endl;
155 Method::const_iterator BBI = Meth->begin(); // random iterator for BBs
157 for( ; BBI != Meth->end(); ++BBI) { // traverse BBs in random order
159 // get the iterator for machine instructions
160 const MachineCodeForBasicBlock& MIVec = (*BBI)->getMachineInstrVec();
161 MachineCodeForBasicBlock::const_iterator
162 MInstIterator = MIVec.begin();
164 // iterate over all the machine instructions in BB
165 for( ; MInstIterator != MIVec.end(); ++MInstIterator) {
167 const MachineInstr *const MInst = *MInstIterator;
169 // get the LV set after the instruction
170 const LiveVarSet *const LVSetAI =
171 LVI->getLiveVarSetAfterMInst(MInst, *BBI);
173 const bool isCallInst = TM.getInstrInfo().isCall(MInst->getOpCode());
175 // if( isCallInst) cout << "\n%%% Found call Inst:\n";
177 // iterate over MI operands to find defs
178 for( MachineInstr::val_op_const_iterator OpI(MInst);!OpI.done(); ++OpI) {
181 // create a new LR iff this operand is a def
182 addInterference(*OpI, LVSetAI, isCallInst );
186 } // for all operands
189 // Also add interference for any implicit definitions in a machine
190 // instr (currently, only calls have this).
192 unsigned NumOfImpRefs = MInst->getNumImplicitRefs();
193 if( NumOfImpRefs > 0 ) {
194 for(unsigned z=0; z < NumOfImpRefs; z++)
195 if( MInst->implicitRefIsDefined(z) )
196 addInterference( MInst->getImplicitRef(z), LVSetAI, isCallInst );
199 } // for all machine instructions in BB
204 // go thru LLVM instructions in the basic block and record all CALL
205 // instructions and Return instructions in the CallInstrList
206 // This is done because since there are no reverse pointers in machine
207 // instructions to find the llvm instruction, when we encounter a call
208 // or a return whose args must be specailly colored (e.g., %o's for args)
209 BasicBlock::const_iterator InstIt = (*BBI)->begin();
211 for( ; InstIt != (*BBI)->end() ; ++ InstIt) {
212 unsigned OpCode = (*InstIt)->getOpcode();
214 if( OpCode == Instruction::Call )
215 CallInstrList.push_back( *InstIt );
217 else if( OpCode == Instruction::Ret )
218 RetInstrList.push_back( *InstIt );
224 } // for all BBs in method
227 // add interferences for method arguments. Since there are no explict
228 // defs in method for args, we have to add them manually
230 addInterferencesForArgs(); // add interference for method args
233 cout << "Interference graphs calculted!" << endl;
240 //----------------------------------------------------------------------------
241 // This method will add interferences for incoming arguments to a method.
242 //----------------------------------------------------------------------------
243 void PhyRegAlloc::addInterferencesForArgs()
245 // get the InSet of root BB
246 const LiveVarSet *const InSet = LVI->getInSetOfBB( Meth->front() );
248 // get the argument list
249 const Method::ArgumentListType& ArgList = Meth->getArgumentList();
251 // get an iterator to arg list
252 Method::ArgumentListType::const_iterator ArgIt = ArgList.begin();
255 for( ; ArgIt != ArgList.end() ; ++ArgIt) { // for each argument
256 addInterference( *ArgIt, InSet, false ); // add interferences between
257 // args and LVars at start
259 cout << " - %% adding interference for argument ";
260 printValue( (const Value *) *ArgIt); cout << endl;
267 //----------------------------------------------------------------------------
268 // This method inserts caller saving/restoring instructons before/after
269 // a call machine instruction.
270 //----------------------------------------------------------------------------
273 void PhyRegAlloc::insertCallerSavingCode(const MachineInstr *MInst,
274 const BasicBlock *BB )
276 assert( (TM.getInstrInfo()).isCall( MInst->getOpCode() ) );
278 int StackOff = 10; // ****TODO : Change
279 hash_set<unsigned> PushedRegSet;
281 // Now find the LR of the return value of the call
282 // The last *implicit operand* is the return value of a call
283 // Insert it to to he PushedRegSet since we must not save that register
284 // and restore it after the call.
285 // We do this because, we look at the LV set *after* the instruction
286 // to determine, which LRs must be saved across calls. The return value
287 // of the call is live in this set - but we must not save/restore it.
289 unsigned NumOfImpRefs = MInst->getNumImplicitRefs();
290 if( NumOfImpRefs > 0 ) {
292 if( MInst->implicitRefIsDefined(NumOfImpRefs-1) ) {
294 const Value *RetVal = MInst->getImplicitRef(NumOfImpRefs-1);
295 LiveRange *RetValLR = LRI.getLiveRangeForValue( RetVal );
296 assert( RetValLR && "No LR for RetValue of call");
299 MRI.getUnifiedRegNum((RetValLR->getRegClass())->getID(),
300 RetValLR->getColor() ) );
306 const LiveVarSet *LVSetAft = LVI->getLiveVarSetAfterMInst(MInst, BB);
308 LiveVarSet::const_iterator LIt = LVSetAft->begin();
310 // for each live var in live variable set after machine inst
311 for( ; LIt != LVSetAft->end(); ++LIt) {
313 // get the live range corresponding to live var
314 LiveRange *const LR = LRI.getLiveRangeForValue(*LIt );
316 // LROfVar can be null if it is a const since a const
317 // doesn't have a dominating def - see Assumptions above
320 if( LR->hasColor() ) {
322 unsigned RCID = (LR->getRegClass())->getID();
323 unsigned Color = LR->getColor();
325 if ( MRI.isRegVolatile(RCID, Color) ) {
327 // if the value is in both LV sets (i.e., live before and after
328 // the call machine instruction)
330 unsigned Reg = MRI.getUnifiedRegNum(RCID, Color);
332 if( PushedRegSet.find(Reg) == PushedRegSet.end() ) {
334 // if we haven't already pushed that register
336 unsigned RegType = MRI.getRegType( LR );
338 // Now get two instructions - to push on stack and pop from stack
339 // and add them to InstrnsBefore and InstrnsAfter of the
342 MachineInstr *AdIBef =
343 MRI.cpReg2MemMI(Reg, MRI.getFramePointer(), StackOff, RegType );
345 MachineInstr *AdIAft =
346 MRI.cpMem2RegMI(MRI.getFramePointer(), StackOff, Reg, RegType );
348 ((AddedInstrMap[MInst])->InstrnsBefore).push_front(AdIBef);
349 ((AddedInstrMap[MInst])->InstrnsAfter).push_back(AdIAft);
351 PushedRegSet.insert( Reg );
352 StackOff += 4; // ****TODO: Correct ??????
353 cout << "\n $$$ Inserted caller saving instr";
355 } // if not already pushed
357 } // if LR has a volatile color
361 } // if there is a LR for Var
363 } // for each value in the LV set after instruction
368 //----------------------------------------------------------------------------
369 // This method is called after register allocation is complete to set the
370 // allocated reisters in the machine code. This code will add register numbers
371 // to MachineOperands that contain a Value.
372 //----------------------------------------------------------------------------
374 void PhyRegAlloc::updateMachineCode()
377 Method::const_iterator BBI = Meth->begin(); // random iterator for BBs
379 for( ; BBI != Meth->end(); ++BBI) { // traverse BBs in random order
381 // get the iterator for machine instructions
382 MachineCodeForBasicBlock& MIVec = (*BBI)->getMachineInstrVec();
383 MachineCodeForBasicBlock::iterator MInstIterator = MIVec.begin();
385 // iterate over all the machine instructions in BB
386 for( ; MInstIterator != MIVec.end(); ++MInstIterator) {
388 MachineInstr *MInst = *MInstIterator;
390 // if this machine instr is call, insert caller saving code
392 if( (TM.getInstrInfo()).isCall( MInst->getOpCode()) )
393 insertCallerSavingCode(MInst, *BBI );
395 // If there are instructions to be added, *before* this machine
396 // instruction, add them now.
398 if( AddedInstrMap[ MInst ] ) {
400 deque<MachineInstr *> &IBef = (AddedInstrMap[MInst])->InstrnsBefore;
402 if( ! IBef.empty() ) {
404 deque<MachineInstr *>::iterator AdIt;
406 for( AdIt = IBef.begin(); AdIt != IBef.end() ; ++AdIt ) {
408 cout << " *$* PREPENDed instr opcode: ";
409 cout << TargetInstrDescriptors[(*AdIt)->getOpCode()].opCodeString;
412 MInstIterator = MIVec.insert( MInstIterator, *AdIt );
422 //for(MachineInstr::val_op_const_iterator OpI(MInst);!OpI.done();++OpI) {
424 for(unsigned OpNum=0; OpNum < MInst->getNumOperands(); ++OpNum) {
426 MachineOperand& Op = MInst->getOperand(OpNum);
428 if( Op.getOperandType() == MachineOperand::MO_VirtualRegister ||
429 Op.getOperandType() == MachineOperand::MO_CCRegister) {
431 const Value *const Val = Op.getVRegValue();
433 // delete this condition checking later (must assert if Val is null)
436 cout << "Warning: NULL Value found for operand" << endl;
439 assert( Val && "Value is NULL");
441 const LiveRange *const LR = LRI.getLiveRangeForValue(Val);
445 // nothing to worry if it's a const or a label
448 cout << "*NO LR for inst opcode: ";
449 cout << TargetInstrDescriptors[MInst->getOpCode()].opCodeString;
452 // if register is not allocated, mark register as invalid
453 if( Op.getAllocatedRegNum() == -1)
454 Op.setRegForValue( MRI.getInvalidRegNum());
457 if( ((Val->getType())->isLabelType()) ||
458 (Val->getValueType() == Value::ConstantVal) )
461 // The return address is not explicitly defined within a
462 // method. So, it is not colored by usual algorithm. In that case
465 //else if (TM.getInstrInfo().isCall(MInst->getOpCode()))
466 //Op.setRegForValue( MRI.getCallAddressReg() );
468 //TM.getInstrInfo().isReturn(MInst->getOpCode())
469 else if(TM.getInstrInfo().isReturn(MInst->getOpCode()) ) {
470 if (DEBUG_RA) cout << endl << "RETURN found" << endl;
471 Op.setRegForValue( MRI.getReturnAddressReg() );
475 if (Val->getValueType() == Value::InstructionVal)
477 cout << "!Warning: No LiveRange for: ";
478 printValue( Val); cout << " Type: " << Val->getValueType();
479 cout << " RegVal=" << Op.getAllocatedRegNum() << endl;
487 unsigned RCID = (LR->getRegClass())->getID();
489 Op.setRegForValue( MRI.getUnifiedRegNum(RCID, LR->getColor()) );
491 int RegNum = MRI.getUnifiedRegNum(RCID, LR->getColor());
495 } // for each operand
498 // If there are instructions to be added *after* this machine
499 // instruction, add them now
501 if( AddedInstrMap[ MInst ] ) {
503 deque<MachineInstr *> &IAft = (AddedInstrMap[MInst])->InstrnsAfter;
505 if( ! IAft.empty() ) {
507 deque<MachineInstr *>::iterator AdIt;
509 ++MInstIterator; // advance to the next instruction
511 for( AdIt = IAft.begin(); AdIt != IAft.end() ; ++AdIt ) {
513 cout << " *#* APPENDed instr opcode: ";
514 cout << TargetInstrDescriptors[(*AdIt)->getOpCode()].opCodeString;
517 MInstIterator = MIVec.insert( MInstIterator, *AdIt );
521 // MInsterator already points to the next instr. Since the
522 // for loop also increments it, decrement it to point to the
523 // instruction added last
530 } // for each machine instruction
537 //----------------------------------------------------------------------------
538 // This method prints the code with registers after register allocation is
540 //----------------------------------------------------------------------------
541 void PhyRegAlloc::printMachineCode()
544 cout << endl << ";************** Method ";
545 cout << Meth->getName() << " *****************" << endl;
547 Method::const_iterator BBI = Meth->begin(); // random iterator for BBs
549 for( ; BBI != Meth->end(); ++BBI) { // traverse BBs in random order
551 cout << endl ; printLabel( *BBI); cout << ": ";
553 // get the iterator for machine instructions
554 MachineCodeForBasicBlock& MIVec = (*BBI)->getMachineInstrVec();
555 MachineCodeForBasicBlock::iterator MInstIterator = MIVec.begin();
557 // iterate over all the machine instructions in BB
558 for( ; MInstIterator != MIVec.end(); ++MInstIterator) {
560 MachineInstr *const MInst = *MInstIterator;
563 cout << endl << "\t";
564 cout << TargetInstrDescriptors[MInst->getOpCode()].opCodeString;
567 //for(MachineInstr::val_op_const_iterator OpI(MInst);!OpI.done();++OpI) {
569 for(unsigned OpNum=0; OpNum < MInst->getNumOperands(); ++OpNum) {
571 MachineOperand& Op = MInst->getOperand(OpNum);
573 if( Op.getOperandType() == MachineOperand::MO_VirtualRegister ||
574 Op.getOperandType() == MachineOperand::MO_CCRegister ||
575 Op.getOperandType() == MachineOperand::MO_PCRelativeDisp ) {
577 const Value *const Val = Op.getVRegValue () ;
578 // ****this code is temporary till NULL Values are fixed
580 cout << "\t<*NULL*>";
584 // if a label or a constant
585 if( (Val->getValueType() == Value::BasicBlockVal) ) {
587 cout << "\t"; printLabel( Op.getVRegValue () );
590 // else it must be a register value
591 const int RegNum = Op.getAllocatedRegNum();
593 //if( RegNum != 1000)
595 cout << "\t" << "%" << MRI.getUnifiedRegName( RegNum );
596 // else cout << "\t<*NoReg*>";
601 else if(Op.getOperandType() == MachineOperand::MO_MachineRegister) {
602 cout << "\t" << "%" << MRI.getUnifiedRegName(Op.getMachineRegNum());
606 cout << "\t" << Op; // use dump field
611 unsigned NumOfImpRefs = MInst->getNumImplicitRefs();
612 if( NumOfImpRefs > 0 ) {
614 cout << "\tImplicit:";
616 for(unsigned z=0; z < NumOfImpRefs; z++) {
617 printValue( MInst->getImplicitRef(z) );
623 } // for all machine instructions
634 //----------------------------------------------------------------------------
636 //----------------------------------------------------------------------------
638 void PhyRegAlloc::colorCallRetArgs()
641 CallRetInstrListType &CallRetInstList = LRI.getCallRetInstrList();
642 CallRetInstrListType::const_iterator It = CallRetInstList.begin();
644 for( ; It != CallRetInstList.end(); ++It ) {
646 const MachineInstr *const CRMI = *It;
647 unsigned OpCode = CRMI->getOpCode();
649 // get the added instructions for this Call/Ret instruciton
650 AddedInstrns *AI = AddedInstrMap[ CRMI ];
652 AI = new AddedInstrns();
653 AddedInstrMap[ CRMI ] = AI;
656 if( (TM.getInstrInfo()).isCall( OpCode ) )
657 MRI.colorCallArgs( CRMI, LRI, AI );
659 else if ( (TM.getInstrInfo()).isReturn(OpCode) )
660 MRI.colorRetValue( CRMI, LRI, AI );
662 else assert( 0 && "Non Call/Ret instrn in CallRetInstrList\n" );
668 //----------------------------------------------------------------------------
670 //----------------------------------------------------------------------------
671 void PhyRegAlloc::colorIncomingArgs()
673 const BasicBlock *const FirstBB = Meth->front();
674 const MachineInstr *FirstMI = *((FirstBB->getMachineInstrVec()).begin());
675 assert( FirstMI && "No machine instruction in entry BB");
677 AddedInstrns *AI = AddedInstrMap[ FirstMI ];
679 AI = new AddedInstrns();
680 AddedInstrMap[ FirstMI ] = AI;
683 MRI.colorMethodArgs(Meth, LRI, AI );
687 //----------------------------------------------------------------------------
688 // Used to generate a label for a basic block
689 //----------------------------------------------------------------------------
690 void PhyRegAlloc::printLabel(const Value *const Val)
693 cout << Val->getName();
695 cout << "Label" << Val;
699 //----------------------------------------------------------------------------
700 // The entry pont to Register Allocation
701 //----------------------------------------------------------------------------
703 void PhyRegAlloc::allocateRegisters()
706 // make sure that we put all register classes into the RegClassList
707 // before we call constructLiveRanges (now done in the constructor of
708 // PhyRegAlloc class).
710 constructLiveRanges(); // create LR info
713 LRI.printLiveRanges();
715 createIGNodeListsAndIGs(); // create IGNode list and IGs
717 buildInterferenceGraphs(); // build IGs in all reg classes
721 // print all LRs in all reg classes
722 for( unsigned int rc=0; rc < NumOfRegClasses ; rc++)
723 RegClassList[ rc ]->printIGNodeList();
725 // print IGs in all register classes
726 for( unsigned int rc=0; rc < NumOfRegClasses ; rc++)
727 RegClassList[ rc ]->printIG();
730 LRI.coalesceLRs(); // coalesce all live ranges
733 // print all LRs in all reg classes
734 for( unsigned int rc=0; rc < NumOfRegClasses ; rc++)
735 RegClassList[ rc ]->printIGNodeList();
737 // print IGs in all register classes
738 for( unsigned int rc=0; rc < NumOfRegClasses ; rc++)
739 RegClassList[ rc ]->printIG();
742 // color all register classes
743 for( unsigned int rc=0; rc < NumOfRegClasses ; rc++)
744 RegClassList[ rc ]->colorAllRegs();
747 // color incoming args and call args
754 // PrintMachineInstructions(Meth);
755 printMachineCode(); // only for DEBUGGING