2 //***************************************************************************
7 // Register allocation for LLVM.
10 // 9/10/01 - Ruchira Sasanka - created.
11 //**************************************************************************/
13 #include "llvm/CodeGen/PhyRegAlloc.h"
14 #include "llvm/CodeGen/MachineInstr.h"
15 #include "llvm/Target/TargetMachine.h"
16 #include "llvm/Target/MachineFrameInfo.h"
19 // ***TODO: There are several places we add instructions. Validate the order
20 // of adding these instructions.
24 cl::Enum<RegAllocDebugLevel_t> DEBUG_RA("dregalloc", cl::NoFlags,
25 "enable register allocation debugging information",
26 clEnumValN(RA_DEBUG_None , "n", "disable debug output"),
27 clEnumValN(RA_DEBUG_Normal , "y", "enable debug output"),
28 clEnumValN(RA_DEBUG_Verbose, "v", "enable extra debug output"), 0);
31 //----------------------------------------------------------------------------
32 // Constructor: Init local composite objects and create register classes.
33 //----------------------------------------------------------------------------
34 PhyRegAlloc::PhyRegAlloc(Method *M,
35 const TargetMachine& tm,
36 MethodLiveVarInfo *const Lvi)
40 mcInfo(MachineCodeForMethod::get(M)),
41 LVI(Lvi), LRI(M, tm, RegClassList),
42 MRI( tm.getRegInfo() ),
43 NumOfRegClasses(MRI.getNumOfRegClasses()),
47 // **TODO: use an actual reserved color list
48 ReservedColorListType *RCL = new ReservedColorListType();
50 // create each RegisterClass and put in RegClassList
51 for( unsigned int rc=0; rc < NumOfRegClasses; rc++)
52 RegClassList.push_back( new RegClass(M, MRI.getMachineRegClass(rc), RCL) );
55 //----------------------------------------------------------------------------
56 // This method initally creates interference graphs (one in each reg class)
57 // and IGNodeList (one in each IG). The actual nodes will be pushed later.
58 //----------------------------------------------------------------------------
60 void PhyRegAlloc::createIGNodeListsAndIGs()
62 if(DEBUG_RA ) cout << "Creating LR lists ..." << endl;
65 LiveRangeMapType::const_iterator HMI = (LRI.getLiveRangeMap())->begin();
68 LiveRangeMapType::const_iterator HMIEnd = (LRI.getLiveRangeMap())->end();
70 for( ; HMI != HMIEnd ; ++HMI ) {
74 LiveRange *L = (*HMI).second; // get the LiveRange
78 cout << "\n*?!?Warning: Null liver range found for: ";
79 printValue( (*HMI).first) ; cout << endl;
83 // if the Value * is not null, and LR
84 // is not yet written to the IGNodeList
85 if( !(L->getUserIGNode()) ) {
87 RegClass *const RC = // RegClass of first value in the LR
88 //RegClassList [MRI.getRegClassIDOfValue(*(L->begin()))];
89 RegClassList[ L->getRegClass()->getID() ];
91 RC-> addLRToIG( L ); // add this LR to an IG
97 for( unsigned int rc=0; rc < NumOfRegClasses ; rc++)
98 RegClassList[ rc ]->createInterferenceGraph();
101 cout << "LRLists Created!" << endl;
106 //----------------------------------------------------------------------------
107 // This method will add all interferences at for a given instruction.
108 // Interence occurs only if the LR of Def (Inst or Arg) is of the same reg
109 // class as that of live var. The live var passed to this function is the
110 // LVset AFTER the instruction
111 //----------------------------------------------------------------------------
113 void PhyRegAlloc::addInterference(const Value *const Def,
114 const LiveVarSet *const LVSet,
115 const bool isCallInst) {
117 LiveVarSet::const_iterator LIt = LVSet->begin();
119 // get the live range of instruction
120 const LiveRange *const LROfDef = LRI.getLiveRangeForValue( Def );
122 IGNode *const IGNodeOfDef = LROfDef->getUserIGNode();
123 assert( IGNodeOfDef );
125 RegClass *const RCOfDef = LROfDef->getRegClass();
127 // for each live var in live variable set
128 for( ; LIt != LVSet->end(); ++LIt) {
131 cout << "< Def="; printValue(Def);
132 cout << ", Lvar="; printValue( *LIt); cout << "> ";
135 // get the live range corresponding to live var
136 LiveRange *const LROfVar = LRI.getLiveRangeForValue(*LIt );
138 // LROfVar can be null if it is a const since a const
139 // doesn't have a dominating def - see Assumptions above
142 if(LROfDef == LROfVar) // do not set interf for same LR
145 // if 2 reg classes are the same set interference
146 if( RCOfDef == LROfVar->getRegClass() ){
147 RCOfDef->setInterference( LROfDef, LROfVar);
151 else if(DEBUG_RA > 1) {
152 // we will not have LRs for values not explicitly allocated in the
153 // instruction stream (e.g., constants)
154 cout << " warning: no live range for " ;
155 printValue( *LIt); cout << endl; }
164 //----------------------------------------------------------------------------
165 // For a call instruction, this method sets the CallInterference flag in
166 // the LR of each variable live int the Live Variable Set live after the
167 // call instruction (except the return value of the call instruction - since
168 // the return value does not interfere with that call itself).
169 //----------------------------------------------------------------------------
171 void PhyRegAlloc::setCallInterferences(const MachineInstr *MInst,
172 const LiveVarSet *const LVSetAft )
174 // Now find the LR of the return value of the call
177 // We do this because, we look at the LV set *after* the instruction
178 // to determine, which LRs must be saved across calls. The return value
179 // of the call is live in this set - but it does not interfere with call
180 // (i.e., we can allocate a volatile register to the return value)
182 LiveRange *RetValLR = NULL;
184 const Value *RetVal = MRI.getCallInstRetVal( MInst );
187 RetValLR = LRI.getLiveRangeForValue( RetVal );
188 assert( RetValLR && "No LR for RetValue of call");
192 cout << "\n For call inst: " << *MInst;
194 LiveVarSet::const_iterator LIt = LVSetAft->begin();
196 // for each live var in live variable set after machine inst
197 for( ; LIt != LVSetAft->end(); ++LIt) {
199 // get the live range corresponding to live var
200 LiveRange *const LR = LRI.getLiveRangeForValue(*LIt );
202 if( LR && DEBUG_RA) {
203 cout << "\n\tLR Aft Call: ";
208 // LR can be null if it is a const since a const
209 // doesn't have a dominating def - see Assumptions above
210 if( LR && (LR != RetValLR) ) {
211 LR->setCallInterference();
213 cout << "\n ++Added call interf for LR: " ;
223 //----------------------------------------------------------------------------
224 // This method will walk thru code and create interferences in the IG of
226 //----------------------------------------------------------------------------
228 void PhyRegAlloc::buildInterferenceGraphs()
231 if(DEBUG_RA) cout << "Creating interference graphs ..." << endl;
233 Method::const_iterator BBI = Meth->begin(); // random iterator for BBs
235 for( ; BBI != Meth->end(); ++BBI) { // traverse BBs in random order
237 // get the iterator for machine instructions
238 const MachineCodeForBasicBlock& MIVec = (*BBI)->getMachineInstrVec();
239 MachineCodeForBasicBlock::const_iterator
240 MInstIterator = MIVec.begin();
242 // iterate over all the machine instructions in BB
243 for( ; MInstIterator != MIVec.end(); ++MInstIterator) {
245 const MachineInstr * MInst = *MInstIterator;
247 // get the LV set after the instruction
248 const LiveVarSet *const LVSetAI =
249 LVI->getLiveVarSetAfterMInst(MInst, *BBI);
251 const bool isCallInst = TM.getInstrInfo().isCall(MInst->getOpCode());
254 //cout << "\nFor call inst: " << *MInst;
256 // set the isCallInterference flag of each live range wich extends
257 // accross this call instruction. This information is used by graph
258 // coloring algo to avoid allocating volatile colors to live ranges
259 // that span across calls (since they have to be saved/restored)
260 setCallInterferences( MInst, LVSetAI);
264 // iterate over MI operands to find defs
265 for( MachineInstr::val_op_const_iterator OpI(MInst);!OpI.done(); ++OpI) {
268 // create a new LR iff this operand is a def
269 addInterference(*OpI, LVSetAI, isCallInst );
271 } // for all operands
274 // if there are multiple defs in this instruction e.g. in SETX
276 if( (TM.getInstrInfo()).isPseudoInstr( MInst->getOpCode()) )
277 addInterf4PseudoInstr(MInst);
280 // Also add interference for any implicit definitions in a machine
281 // instr (currently, only calls have this).
283 unsigned NumOfImpRefs = MInst->getNumImplicitRefs();
284 if( NumOfImpRefs > 0 ) {
285 for(unsigned z=0; z < NumOfImpRefs; z++)
286 if( MInst->implicitRefIsDefined(z) )
287 addInterference( MInst->getImplicitRef(z), LVSetAI, isCallInst );
291 // record phi instrns in PhiInstList
292 if( TM.getInstrInfo().isDummyPhiInstr(MInst->getOpCode()) )
293 PhiInstList.push_back( MInst );
296 } // for all machine instructions in BB
298 } // for all BBs in method
301 // add interferences for method arguments. Since there are no explict
302 // defs in method for args, we have to add them manually
304 addInterferencesForArgs(); // add interference for method args
307 cout << "Interference graphs calculted!" << endl;
311 //--------------------------------------------------------------------------
312 // Pseudo instructions will be exapnded to multiple instructions by the
313 // assembler. Consequently, all the opernds must get distinct registers
314 //--------------------------------------------------------------------------
316 void PhyRegAlloc::addInterf4PseudoInstr(const MachineInstr *MInst) {
318 bool setInterf = false;
320 // iterate over MI operands to find defs
321 for( MachineInstr::val_op_const_iterator It1(MInst);!It1.done(); ++It1) {
323 const LiveRange *const LROfOp1 = LRI.getLiveRangeForValue( *It1 );
325 if( !LROfOp1 && It1.isDef() )
326 assert( 0 && "No LR for Def in PSEUDO insruction");
328 //if( !LROfOp1 ) continue;
330 MachineInstr::val_op_const_iterator It2 = It1;
333 for( ; !It2.done(); ++It2) {
335 const LiveRange *const LROfOp2 = LRI.getLiveRangeForValue( *It2 );
339 RegClass *const RCOfOp1 = LROfOp1->getRegClass();
340 RegClass *const RCOfOp2 = LROfOp2->getRegClass();
342 if( RCOfOp1 == RCOfOp2 ){
343 RCOfOp1->setInterference( LROfOp1, LROfOp2 );
344 //cerr << "\nSet interfs for PSEUDO inst: " << *MInst;
351 } // for all other defs in machine instr
353 } // for all operands in an instruction
355 if( !setInterf && (MInst->getNumOperands() > 2) ) {
356 cerr << "\nInterf not set for any operand in pseudo instr:\n";
358 assert(0 && "Interf not set for pseudo instr with > 2 operands" );
368 //----------------------------------------------------------------------------
369 // This method will add interferences for incoming arguments to a method.
370 //----------------------------------------------------------------------------
371 void PhyRegAlloc::addInterferencesForArgs()
373 // get the InSet of root BB
374 const LiveVarSet *const InSet = LVI->getInSetOfBB( Meth->front() );
376 // get the argument list
377 const Method::ArgumentListType& ArgList = Meth->getArgumentList();
379 // get an iterator to arg list
380 Method::ArgumentListType::const_iterator ArgIt = ArgList.begin();
383 for( ; ArgIt != ArgList.end() ; ++ArgIt) { // for each argument
384 addInterference( *ArgIt, InSet, false ); // add interferences between
385 // args and LVars at start
387 cout << " - %% adding interference for argument ";
388 printValue( (const Value *) *ArgIt); cout << endl;
394 //----------------------------------------------------------------------------
395 // This method is called after register allocation is complete to set the
396 // allocated reisters in the machine code. This code will add register numbers
397 // to MachineOperands that contain a Value.
398 //----------------------------------------------------------------------------
400 void PhyRegAlloc::updateMachineCode()
403 Method::const_iterator BBI = Meth->begin(); // random iterator for BBs
405 for( ; BBI != Meth->end(); ++BBI) { // traverse BBs in random order
407 // get the iterator for machine instructions
408 MachineCodeForBasicBlock& MIVec = (*BBI)->getMachineInstrVec();
409 MachineCodeForBasicBlock::iterator MInstIterator = MIVec.begin();
411 // iterate over all the machine instructions in BB
412 for( ; MInstIterator != MIVec.end(); ++MInstIterator) {
414 MachineInstr *MInst = *MInstIterator;
416 // do not process Phis
417 if( (TM.getInstrInfo()).isPhi( MInst->getOpCode()) )
421 // if this machine instr is call, insert caller saving code
423 if( (TM.getInstrInfo()).isCall( MInst->getOpCode()) )
424 MRI.insertCallerSavingCode(MInst, *BBI, *this );
427 // reset the stack offset for temporary variables since we may
428 // need that to spill
429 mcInfo.popAllTempValues(TM);
431 //for(MachineInstr::val_op_const_iterator OpI(MInst);!OpI.done();++OpI) {
434 // Now replace set the registers for operands in the machine instruction
436 for(unsigned OpNum=0; OpNum < MInst->getNumOperands(); ++OpNum) {
438 MachineOperand& Op = MInst->getOperand(OpNum);
440 if( Op.getOperandType() == MachineOperand::MO_VirtualRegister ||
441 Op.getOperandType() == MachineOperand::MO_CCRegister) {
443 const Value *const Val = Op.getVRegValue();
445 // delete this condition checking later (must assert if Val is null)
448 cout << "Warning: NULL Value found for operand" << endl;
451 assert( Val && "Value is NULL");
453 LiveRange *const LR = LRI.getLiveRangeForValue(Val);
457 // nothing to worry if it's a const or a label
460 cout << "*NO LR for operand : " << Op ;
461 cout << " [reg:" << Op.getAllocatedRegNum() << "]";
462 cout << " in inst:\t" << *MInst << endl;
465 // if register is not allocated, mark register as invalid
466 if( Op.getAllocatedRegNum() == -1)
467 Op.setRegForValue( MRI.getInvalidRegNum());
473 unsigned RCID = (LR->getRegClass())->getID();
475 if( LR->hasColor() ) {
476 Op.setRegForValue( MRI.getUnifiedRegNum(RCID, LR->getColor()) );
480 // LR did NOT receive a color (register). Now, insert spill code
481 // for spilled opeands in this machine instruction
483 //assert(0 && "LR must be spilled");
484 insertCode4SpilledLR(LR, MInst, *BBI, OpNum );
489 } // for each operand
492 // If there are instructions to be added, *before* this machine
493 // instruction, add them now.
495 if( AddedInstrMap[ MInst ] ) {
497 deque<MachineInstr *> &IBef = (AddedInstrMap[MInst])->InstrnsBefore;
499 if( ! IBef.empty() ) {
501 deque<MachineInstr *>::iterator AdIt;
503 for( AdIt = IBef.begin(); AdIt != IBef.end() ; ++AdIt ) {
506 cerr << "For inst " << *MInst;
507 cerr << " PREPENDed instr: " << **AdIt << endl;
510 MInstIterator = MIVec.insert( MInstIterator, *AdIt );
518 // If there are instructions to be added *after* this machine
519 // instruction, add them now
521 if( AddedInstrMap[ MInst ] &&
522 ! (AddedInstrMap[ MInst ]->InstrnsAfter).empty() ) {
524 // if there are delay slots for this instruction, the instructions
525 // added after it must really go after the delayed instruction(s)
526 // So, we move the InstrAfter of the current instruction to the
527 // corresponding delayed instruction
530 if((delay=TM.getInstrInfo().getNumDelaySlots(MInst->getOpCode())) >0){
531 move2DelayedInstr(MInst, *(MInstIterator+delay) );
533 if(DEBUG_RA) cout<< "\nMoved an added instr after the delay slot";
539 // Here we can add the "instructions after" to the current
540 // instruction since there are no delay slots for this instruction
542 deque<MachineInstr *> &IAft = (AddedInstrMap[MInst])->InstrnsAfter;
544 if( ! IAft.empty() ) {
546 deque<MachineInstr *>::iterator AdIt;
548 ++MInstIterator; // advance to the next instruction
550 for( AdIt = IAft.begin(); AdIt != IAft.end() ; ++AdIt ) {
553 cerr << "For inst " << *MInst;
554 cerr << " APPENDed instr: " << **AdIt << endl;
557 MInstIterator = MIVec.insert( MInstIterator, *AdIt );
561 // MInsterator already points to the next instr. Since the
562 // for loop also increments it, decrement it to point to the
563 // instruction added last
572 } // for each machine instruction
578 //----------------------------------------------------------------------------
579 // This method inserts spill code for AN operand whose LR was spilled.
580 // This method may be called several times for a single machine instruction
581 // if it contains many spilled operands. Each time it is called, it finds
582 // a register which is not live at that instruction and also which is not
583 // used by other spilled operands of the same instruction. Then it uses
584 // this register temporarily to accomodate the spilled value.
585 //----------------------------------------------------------------------------
586 void PhyRegAlloc::insertCode4SpilledLR(const LiveRange *LR,
588 const BasicBlock *BB,
589 const unsigned OpNum) {
591 MachineOperand& Op = MInst->getOperand(OpNum);
592 bool isDef = MInst->operandIsDefined(OpNum);
593 unsigned RegType = MRI.getRegType( LR );
594 int SpillOff = LR->getSpillOffFromFP();
595 RegClass *RC = LR->getRegClass();
596 const LiveVarSet *LVSetBef = LVI->getLiveVarSetBeforeMInst(MInst, BB);
598 /**** NOTE: THIS SHOULD USE THE RIGHT SIZE FOR THE REG BEING PUSHED ****/
600 mcInfo.pushTempValue(TM, 8 /* TM.findOptimalStorageSize(LR->getType()) */);
602 MachineInstr *MIBef=NULL, *AdIMid=NULL, *MIAft=NULL;
605 TmpReg = getUsableRegAtMI(RC, RegType, MInst,LVSetBef, MIBef, MIAft);
606 TmpReg = MRI.getUnifiedRegNum( RC->getID(), TmpReg );
609 // get the added instructions for this instruciton
610 AddedInstrns *AI = AddedInstrMap[ MInst ];
612 AI = new AddedInstrns();
613 AddedInstrMap[ MInst ] = AI;
620 // for a USE, we have to load the value of LR from stack to a TmpReg
621 // and use the TmpReg as one operand of instruction
623 // actual loading instruction
624 AdIMid = MRI.cpMem2RegMI(MRI.getFramePointer(), SpillOff, TmpReg, RegType);
627 (AI->InstrnsBefore).push_back(MIBef);
629 (AI->InstrnsBefore).push_back(AdIMid);
632 (AI->InstrnsAfter).push_front(MIAft);
636 else { // if this is a Def
638 // for a DEF, we have to store the value produced by this instruction
639 // on the stack position allocated for this LR
641 // actual storing instruction
642 AdIMid = MRI.cpReg2MemMI(TmpReg, MRI.getFramePointer(), SpillOff, RegType);
645 (AI->InstrnsBefore).push_back(MIBef);
647 (AI->InstrnsAfter).push_front(AdIMid);
650 (AI->InstrnsAfter).push_front(MIAft);
654 cerr << "\nFor Inst " << *MInst;
655 cerr << " - SPILLED LR: "; LR->printSet();
656 cerr << "\n - Added Instructions:";
657 if( MIBef ) cerr << *MIBef;
659 if( MIAft ) cerr << *MIAft;
661 Op.setRegForValue( TmpReg ); // set the opearnd
671 //----------------------------------------------------------------------------
672 // We can use the following method to get a temporary register to be used
673 // BEFORE any given machine instruction. If there is a register available,
674 // this method will simply return that register and set MIBef = MIAft = NULL.
675 // Otherwise, it will return a register and MIAft and MIBef will contain
676 // two instructions used to free up this returned register.
677 // Returned register number is the UNIFIED register number
678 //----------------------------------------------------------------------------
680 int PhyRegAlloc::getUsableRegAtMI(RegClass *RC,
682 const MachineInstr *MInst,
683 const LiveVarSet *LVSetBef,
685 MachineInstr *MIAft) {
687 int Reg = getUnusedRegAtMI(RC, MInst, LVSetBef);
688 Reg = MRI.getUnifiedRegNum(RC->getID(), Reg);
691 // we found an unused register, so we can simply use it
692 MIBef = MIAft = NULL;
695 // we couldn't find an unused register. Generate code to free up a reg by
696 // saving it on stack and restoring after the instruction
698 /**** NOTE: THIS SHOULD USE THE RIGHT SIZE FOR THE REG BEING PUSHED ****/
699 int TmpOff = mcInfo.pushTempValue(TM, /*size*/ 8);
701 Reg = getRegNotUsedByThisInst(RC, MInst);
702 MIBef = MRI.cpReg2MemMI(Reg, MRI.getFramePointer(), TmpOff, RegType );
703 MIAft = MRI.cpMem2RegMI(MRI.getFramePointer(), TmpOff, Reg, RegType );
709 //----------------------------------------------------------------------------
710 // This method is called to get a new unused register that can be used to
711 // accomodate a spilled value.
712 // This method may be called several times for a single machine instruction
713 // if it contains many spilled operands. Each time it is called, it finds
714 // a register which is not live at that instruction and also which is not
715 // used by other spilled operands of the same instruction.
716 // Return register number is relative to the register class. NOT
718 //----------------------------------------------------------------------------
719 int PhyRegAlloc::getUnusedRegAtMI(RegClass *RC,
720 const MachineInstr *MInst,
721 const LiveVarSet *LVSetBef) {
723 unsigned NumAvailRegs = RC->getNumOfAvailRegs();
725 bool *IsColorUsedArr = RC->getIsColorUsedArr();
727 for(unsigned i=0; i < NumAvailRegs; i++)
728 IsColorUsedArr[i] = false;
730 LiveVarSet::const_iterator LIt = LVSetBef->begin();
732 // for each live var in live variable set after machine inst
733 for( ; LIt != LVSetBef->end(); ++LIt) {
735 // get the live range corresponding to live var
736 LiveRange *const LRofLV = LRI.getLiveRangeForValue(*LIt );
738 // LR can be null if it is a const since a const
739 // doesn't have a dominating def - see Assumptions above
741 if( LRofLV->hasColor() )
742 IsColorUsedArr[ LRofLV->getColor() ] = true;
745 // It is possible that one operand of this MInst was already spilled
746 // and it received some register temporarily. If that's the case,
747 // it is recorded in machine operand. We must skip such registers.
749 setRegsUsedByThisInst(RC, MInst);
751 unsigned c; // find first unused color
752 for( c=0; c < NumAvailRegs; c++)
753 if( ! IsColorUsedArr[ c ] ) break;
765 //----------------------------------------------------------------------------
766 // This method modifies the IsColorUsedArr of the register class passed to it.
767 // It sets the bits corresponding to the registers used by this machine
768 // instructions. Both explicit and implicit operands are set.
769 //----------------------------------------------------------------------------
770 void PhyRegAlloc::setRegsUsedByThisInst(RegClass *RC,
771 const MachineInstr *MInst ) {
773 bool *IsColorUsedArr = RC->getIsColorUsedArr();
775 for(unsigned OpNum=0; OpNum < MInst->getNumOperands(); ++OpNum) {
777 const MachineOperand& Op = MInst->getOperand(OpNum);
779 if( Op.getOperandType() == MachineOperand::MO_VirtualRegister ||
780 Op.getOperandType() == MachineOperand::MO_CCRegister ) {
782 const Value *const Val = Op.getVRegValue();
785 if( MRI.getRegClassIDOfValue( Val )== RC->getID() ) {
787 if( (Reg=Op.getAllocatedRegNum()) != -1) {
788 IsColorUsedArr[ Reg ] = true;
791 // it is possilbe that this operand still is not marked with
792 // a register but it has a LR and that received a color
794 LiveRange *LROfVal = LRI.getLiveRangeForValue(Val);
796 if( LROfVal->hasColor() )
797 IsColorUsedArr[ LROfVal->getColor() ] = true;
800 } // if reg classes are the same
802 else if (Op.getOperandType() == MachineOperand::MO_MachineRegister) {
803 IsColorUsedArr[ Op.getMachineRegNum() ] = true;
807 // If there are implicit references, mark them as well
809 for(unsigned z=0; z < MInst->getNumImplicitRefs(); z++) {
811 LiveRange *const LRofImpRef =
812 LRI.getLiveRangeForValue( MInst->getImplicitRef(z) );
815 if( LRofImpRef->hasColor() )
816 IsColorUsedArr[ LRofImpRef->getColor() ] = true;
825 //----------------------------------------------------------------------------
826 // Get any other register in a register class, other than what is used
827 // by operands of a machine instruction.
828 //----------------------------------------------------------------------------
829 int PhyRegAlloc::getRegNotUsedByThisInst(RegClass *RC,
830 const MachineInstr *MInst) {
832 bool *IsColorUsedArr = RC->getIsColorUsedArr();
833 unsigned NumAvailRegs = RC->getNumOfAvailRegs();
836 for(unsigned i=0; i < NumAvailRegs ; i++)
837 IsColorUsedArr[i] = false;
839 setRegsUsedByThisInst(RC, MInst);
841 unsigned c; // find first unused color
842 for( c=0; c < RC->getNumOfAvailRegs(); c++)
843 if( ! IsColorUsedArr[ c ] ) break;
848 assert( 0 && "FATAL: No free register could be found in reg class!!");
856 //----------------------------------------------------------------------------
857 // If there are delay slots for an instruction, the instructions
858 // added after it must really go after the delayed instruction(s).
859 // So, we move the InstrAfter of that instruction to the
860 // corresponding delayed instruction using the following method.
862 //----------------------------------------------------------------------------
863 void PhyRegAlloc:: move2DelayedInstr(const MachineInstr *OrigMI,
864 const MachineInstr *DelayedMI) {
867 // "added after" instructions of the original instr
868 deque<MachineInstr *> &OrigAft = (AddedInstrMap[OrigMI])->InstrnsAfter;
870 // "added instructions" of the delayed instr
871 AddedInstrns *DelayAdI = AddedInstrMap[DelayedMI];
873 if(! DelayAdI ) { // create a new "added after" if necessary
874 DelayAdI = new AddedInstrns();
875 AddedInstrMap[DelayedMI] = DelayAdI;
878 // "added after" instructions of the delayed instr
879 deque<MachineInstr *> &DelayedAft = DelayAdI->InstrnsAfter;
881 // go thru all the "added after instructions" of the original instruction
882 // and append them to the "addded after instructions" of the delayed
885 deque<MachineInstr *>::iterator OrigAdIt;
887 for( OrigAdIt = OrigAft.begin(); OrigAdIt != OrigAft.end() ; ++OrigAdIt ) {
888 DelayedAft.push_back( *OrigAdIt );
891 // empty the "added after instructions" of the original instruction
896 //----------------------------------------------------------------------------
897 // This method prints the code with registers after register allocation is
899 //----------------------------------------------------------------------------
900 void PhyRegAlloc::printMachineCode()
903 cout << endl << ";************** Method ";
904 cout << Meth->getName() << " *****************" << endl;
906 Method::const_iterator BBI = Meth->begin(); // random iterator for BBs
908 for( ; BBI != Meth->end(); ++BBI) { // traverse BBs in random order
910 cout << endl ; printLabel( *BBI); cout << ": ";
912 // get the iterator for machine instructions
913 MachineCodeForBasicBlock& MIVec = (*BBI)->getMachineInstrVec();
914 MachineCodeForBasicBlock::iterator MInstIterator = MIVec.begin();
916 // iterate over all the machine instructions in BB
917 for( ; MInstIterator != MIVec.end(); ++MInstIterator) {
919 MachineInstr *const MInst = *MInstIterator;
922 cout << endl << "\t";
923 cout << TargetInstrDescriptors[MInst->getOpCode()].opCodeString;
926 //for(MachineInstr::val_op_const_iterator OpI(MInst);!OpI.done();++OpI) {
928 for(unsigned OpNum=0; OpNum < MInst->getNumOperands(); ++OpNum) {
930 MachineOperand& Op = MInst->getOperand(OpNum);
932 if( Op.getOperandType() == MachineOperand::MO_VirtualRegister ||
933 Op.getOperandType() == MachineOperand::MO_CCRegister /*||
934 Op.getOperandType() == MachineOperand::MO_PCRelativeDisp*/ ) {
936 const Value *const Val = Op.getVRegValue () ;
937 // ****this code is temporary till NULL Values are fixed
939 cout << "\t<*NULL*>";
943 // if a label or a constant
944 if( (Val->getValueType() == Value::BasicBlockVal) ) {
946 cout << "\t"; printLabel( Op.getVRegValue () );
949 // else it must be a register value
950 const int RegNum = Op.getAllocatedRegNum();
952 cout << "\t" << "%" << MRI.getUnifiedRegName( RegNum );
956 else if(Op.getOperandType() == MachineOperand::MO_MachineRegister) {
957 cout << "\t" << "%" << MRI.getUnifiedRegName(Op.getMachineRegNum());
961 cout << "\t" << Op; // use dump field
966 unsigned NumOfImpRefs = MInst->getNumImplicitRefs();
967 if( NumOfImpRefs > 0 ) {
969 cout << "\tImplicit:";
971 for(unsigned z=0; z < NumOfImpRefs; z++) {
972 printValue( MInst->getImplicitRef(z) );
978 } // for all machine instructions
989 //----------------------------------------------------------------------------
991 //----------------------------------------------------------------------------
993 void PhyRegAlloc::colorCallRetArgs()
996 CallRetInstrListType &CallRetInstList = LRI.getCallRetInstrList();
997 CallRetInstrListType::const_iterator It = CallRetInstList.begin();
999 for( ; It != CallRetInstList.end(); ++It ) {
1001 const MachineInstr *const CRMI = *It;
1002 unsigned OpCode = CRMI->getOpCode();
1004 // get the added instructions for this Call/Ret instruciton
1005 AddedInstrns *AI = AddedInstrMap[ CRMI ];
1007 AI = new AddedInstrns();
1008 AddedInstrMap[ CRMI ] = AI;
1011 // Tmp stack poistions are needed by some calls that have spilled args
1012 // So reset it before we call each such method
1013 mcInfo.popAllTempValues(TM);
1015 if( (TM.getInstrInfo()).isCall( OpCode ) )
1016 MRI.colorCallArgs( CRMI, LRI, AI, *this );
1018 else if ( (TM.getInstrInfo()).isReturn(OpCode) )
1019 MRI.colorRetValue( CRMI, LRI, AI );
1021 else assert( 0 && "Non Call/Ret instrn in CallRetInstrList\n" );
1029 //----------------------------------------------------------------------------
1031 //----------------------------------------------------------------------------
1032 void PhyRegAlloc::colorIncomingArgs()
1034 const BasicBlock *const FirstBB = Meth->front();
1035 const MachineInstr *FirstMI = *((FirstBB->getMachineInstrVec()).begin());
1036 assert( FirstMI && "No machine instruction in entry BB");
1038 AddedInstrns *AI = AddedInstrMap[ FirstMI ];
1040 AI = new AddedInstrns();
1041 AddedInstrMap[ FirstMI ] = AI;
1044 MRI.colorMethodArgs(Meth, LRI, AI );
1048 //----------------------------------------------------------------------------
1049 // Used to generate a label for a basic block
1050 //----------------------------------------------------------------------------
1051 void PhyRegAlloc::printLabel(const Value *const Val)
1053 if( Val->hasName() )
1054 cout << Val->getName();
1056 cout << "Label" << Val;
1060 //----------------------------------------------------------------------------
1061 // This method calls setSugColorUsable method of each live range. This
1062 // will determine whether the suggested color of LR is really usable.
1063 // A suggested color is not usable when the suggested color is volatile
1064 // AND when there are call interferences
1065 //----------------------------------------------------------------------------
1067 void PhyRegAlloc::markUnusableSugColors()
1069 if(DEBUG_RA ) cout << "\nmarking unusable suggested colors ..." << endl;
1071 // hash map iterator
1072 LiveRangeMapType::const_iterator HMI = (LRI.getLiveRangeMap())->begin();
1073 LiveRangeMapType::const_iterator HMIEnd = (LRI.getLiveRangeMap())->end();
1075 for( ; HMI != HMIEnd ; ++HMI ) {
1077 if( (*HMI).first ) {
1079 LiveRange *L = (*HMI).second; // get the LiveRange
1082 if( L->hasSuggestedColor() ) {
1084 int RCID = (L->getRegClass())->getID();
1085 if( MRI.isRegVolatile( RCID, L->getSuggestedColor()) &&
1086 L->isCallInterference() )
1087 L->setSuggestedColorUsable( false );
1089 L->setSuggestedColorUsable( true );
1091 } // if L->hasSuggestedColor()
1093 } // for all LR's in hash map
1098 //----------------------------------------------------------------------------
1099 // The following method will set the stack offsets of the live ranges that
1100 // are decided to be spillled. This must be called just after coloring the
1101 // LRs using the graph coloring algo. For each live range that is spilled,
1102 // this method allocate a new spill position on the stack.
1103 //----------------------------------------------------------------------------
1105 void PhyRegAlloc::allocateStackSpace4SpilledLRs()
1107 if(DEBUG_RA ) cout << "\nsetting LR stack offsets ..." << endl;
1109 // hash map iterator
1110 LiveRangeMapType::const_iterator HMI = (LRI.getLiveRangeMap())->begin();
1111 LiveRangeMapType::const_iterator HMIEnd = (LRI.getLiveRangeMap())->end();
1113 for( ; HMI != HMIEnd ; ++HMI ) {
1114 if( (*HMI).first ) {
1115 LiveRange *L = (*HMI).second; // get the LiveRange
1117 if( ! L->hasColor() )
1118 /**** NOTE: THIS SHOULD USE THE RIGHT SIZE FOR THE REG BEING PUSHED ****/
1119 L->setSpillOffFromFP(mcInfo.allocateSpilledValue(TM, Type::LongTy /*L->getType()*/ ));
1121 } // for all LR's in hash map
1126 //----------------------------------------------------------------------------
1127 // The entry pont to Register Allocation
1128 //----------------------------------------------------------------------------
1130 void PhyRegAlloc::allocateRegisters()
1133 // make sure that we put all register classes into the RegClassList
1134 // before we call constructLiveRanges (now done in the constructor of
1135 // PhyRegAlloc class).
1137 constructLiveRanges(); // create LR info
1140 LRI.printLiveRanges();
1142 createIGNodeListsAndIGs(); // create IGNode list and IGs
1144 buildInterferenceGraphs(); // build IGs in all reg classes
1148 // print all LRs in all reg classes
1149 for( unsigned int rc=0; rc < NumOfRegClasses ; rc++)
1150 RegClassList[ rc ]->printIGNodeList();
1152 // print IGs in all register classes
1153 for( unsigned int rc=0; rc < NumOfRegClasses ; rc++)
1154 RegClassList[ rc ]->printIG();
1157 LRI.coalesceLRs(); // coalesce all live ranges
1159 // coalscing could not get rid of all phi's, add phi elimination
1161 // insertPhiEleminateInstrns();
1164 // print all LRs in all reg classes
1165 for( unsigned int rc=0; rc < NumOfRegClasses ; rc++)
1166 RegClassList[ rc ]->printIGNodeList();
1168 // print IGs in all register classes
1169 for( unsigned int rc=0; rc < NumOfRegClasses ; rc++)
1170 RegClassList[ rc ]->printIG();
1174 // mark un-usable suggested color before graph coloring algorithm.
1175 // When this is done, the graph coloring algo will not reserve
1176 // suggested color unnecessarily - they can be used by another LR
1177 markUnusableSugColors();
1179 // color all register classes using the graph coloring algo
1180 for( unsigned int rc=0; rc < NumOfRegClasses ; rc++)
1181 RegClassList[ rc ]->colorAllRegs();
1183 // Atter grpah coloring, if some LRs did not receive a color (i.e, spilled)
1184 // a poistion for such spilled LRs
1185 allocateStackSpace4SpilledLRs();
1187 // color incoming args and call args
1188 colorIncomingArgs();
1192 updateMachineCode();
1194 MachineCodeForMethod::get(Meth).dump();
1195 printMachineCode(); // only for DEBUGGING