1 //===- Sparc.td - Target Description for Sparc V9 Target --------*- C++ -*-===//
3 //===----------------------------------------------------------------------===//
5 #include "../Target.td"
7 #include "SparcV9_Reg.td"
9 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
13 class InstV9 : Instruction { // Sparc instruction baseline
19 set Inst{31-30} = op; // Top two bits are the 'op' field
21 // Bit attributes specific to Sparc instructions
22 bit isPasi = 0; // Does this instruction affect an alternate addr space?
23 bit isDeprecated = 0; // Is this instruction deprecated?
24 bit isPrivileged = 0; // Is this a privileged instruction?
27 #include "SparcV9_F2.td"
28 #include "SparcV9_F3.td"
29 #include "SparcV9_F4.td"
31 //===----------------------------------------------------------------------===//
32 // Instruction list...
35 // Section A.2: Add - p137
36 def ADDr : F3_1<2, 0b000000, "add">; // add r, r, r
37 def ADDi : F3_2<2, 0b000000, "add">; // add r, i, r
38 def ADDccr : F3_1<2, 0b010000, "addcc">; // addcc r, r, r
39 def ADDcci : F3_2<2, 0b010000, "addcc">; // addcc r, i, r
40 def ADDCr : F3_1<2, 0b001000, "addC">; // addC r, r, r
41 def ADDCi : F3_2<2, 0b001000, "addC">; // addC r, i, r
42 def ADDCccr : F3_1<2, 0b011000, "addCcc">; // addCcc r, r, r
43 def ADDCcci : F3_2<2, 0b011000, "addCcc">; // addCcc r, i, r
45 // Section A.3: Branch on Integer Register with Prediction - p162
47 def BRZ : F2_4<0b001, "brz">; // Branch on rs1 == 0
48 def BRLEZ : F2_4<0b010, "brlez">; // Branch on rs1 <= 0
49 def BRLZ : F2_4<0b011, "brlz">; // Branch on rs1 < 0
50 def BRNZ : F2_4<0b101, "brnz">; // Branch on rs1 != 0
51 def BRGZ : F2_4<0b110, "brgz">; // Branch on rs1 > 0
52 def BRGEZ : F2_4<0b111, "brgez">; // Branch on rs1 >= 0
56 set isDeprecated = 1 in {
58 def FBA : F2_2<0b1000, "fba">; // Branch always
59 def FBN : F2_2<0b0000, "fbn">; // Branch never
60 def FBU : F2_2<0b0111, "fbu">; // Branch on unordered
61 def FBG : F2_2<0b0110, "fbg">; // Branch >
62 def FBUG : F2_2<0b0101, "fbug">; // Branch on unordered or >
63 def FBL : F2_2<0b0100, "fbl">; // Branch <
64 def FBUL : F2_2<0b0011, "fbul">; // Branch on unordered or <
65 def FBLG : F2_2<0b0010, "fblg">; // Branch < or >
66 def FBNE : F2_2<0b0001, "fbne">; // Branch !=
67 def FBE : F2_2<0b1001, "fbe">; // Branch ==
68 def FBUE : F2_2<0b1010, "fbue">; // Branch on unordered or ==
69 def FBGE : F2_2<0b1011, "fbge">; // Branch > or ==
70 def FBUGE : F2_2<0b1100, "fbuge">; // Branch unord or > or ==
71 def FBLE : F2_2<0b1101, "fble">; // Branch < or ==
72 def FBULE : F2_2<0b1110, "fbule">; // Branch unord or < or ==
73 def FBO : F2_2<0b1111, "fbo">; // Branch on ordered
78 // Not used in the Sparc backend
81 def FBPA : F2_3<0b1000, "fbpa">; // Branch always
82 def FBPN : F2_3<0b0000, "fbpn">; // Branch never
83 def FBPU : F2_3<0b0111, "fbpu">; // Branch on unordered
84 def FBPG : F2_3<0b0110, "fbpg">; // Branch >
85 def FBPUG : F2_3<0b0101, "fbpug">; // Branch on unordered or >
86 def FBPL : F2_3<0b0100, "fbpl">; // Branch <
87 def FBPUL : F2_3<0b0011, "fbpul">; // Branch on unordered or <
88 def FBPLG : F2_3<0b0010, "fbplg">; // Branch < or >
89 def FBPNE : F2_3<0b0001, "fbpne">; // Branch !=
90 def FBPE : F2_3<0b1001, "fbpe">; // Branch ==
91 def FBPUE : F2_3<0b1010, "fbpue">; // Branch on unordered or ==
92 def FBPGE : F2_3<0b1011, "fbpge">; // Branch > or ==
93 def FBPUGE : F2_3<0b1100, "fbpuge">; // Branch unord or > or ==
94 def FBPLE : F2_3<0b1101, "fbple">; // Branch < or ==
95 def FBPULE : F2_3<0b1110, "fbpule">; // Branch unord or < or ==
96 def FBPO : F2_3<0b1111, "fbpo">; // Branch on ordered
100 // Section A.6: Branch on Integer condition codes (Bicc) - p146
101 set isDeprecated = 1 in {
103 def BA : F2_2<0b1000, "ba">; // Branch always
104 def BN : F2_2<0b0000, "bn">; // Branch never
105 def BNE : F2_2<0b1001, "bne">; // Branch !=
106 def BE : F2_2<0b0001, "be">; // Branch ==
107 def BG : F2_2<0b1010, "bg">; // Branch >
108 def BLE : F2_2<0b0010, "ble">; // Branch <=
109 def BGE : F2_2<0b1011, "bge">; // Branch >=
110 def BL : F2_2<0b0011, "bl">; // Branch <
111 def BGU : F2_2<0b1100, "bgu">; // Branch unsigned >
112 def BLEU : F2_2<0b0100, "bleu">; // Branch unsigned <=
113 def BCC : F2_2<0b1101, "bcc">; // Branch unsigned >=
114 def BCS : F2_2<0b0101, "bcs">; // Branch unsigned <=
115 def BPOS : F2_2<0b1110, "bpos">; // Branch on positive
116 def BNEG : F2_2<0b0110, "bneg">; // Branch on negative
117 def BVC : F2_2<0b1111, "bvc">; // Branch on overflow clear
118 def BVS : F2_2<0b0111, "bvs">; // Branch on overflow set
122 // Section A.7: Branch on integer condition codes with prediction - p148
123 // Not used in the Sparc backend
126 def BPA : F2_3<0b1000, "bpa">; // Branch always
127 def BPN : F2_3<0b0000, "bpn">; // Branch never
128 def BPNE : F2_3<0b1001, "bpne">; // Branch !=
129 def BPE : F2_3<0b0001, "bpe">; // Branch ==
130 def BPG : F2_3<0b1010, "bpg">; // Branch >
131 def BPLE : F2_3<0b0010, "bple">; // Branch <=
132 def BPGE : F2_3<0b1011, "bpge">; // Branch >=
133 def BPL : F2_3<0b0011, "bpl">; // Branch <
134 def BPGU : F2_3<0b1100, "bpgu">; // Branch unsigned >
135 def BPLEU : F2_3<0b0100, "bpleu">; // Branch unsigned <=
136 def BPCC : F2_3<0b1101, "bpcc">; // Branch unsigned >=
137 def BPCS : F2_3<0b0101, "bpcs">; // Branch unsigned <=
138 def BPPOS : F2_3<0b1110, "bppos">; // Branch on positive
139 def BPNEG : F2_3<0b0110, "bpneg">; // Branch on negative
140 def BPVC : F2_3<0b1111, "bpvc">; // Branch on overflow clear
141 def BPVS : F2_3<0b0111, "bpvs">; // Branch on overflow set
145 // Section A.8: CALL - p151, the only Format #1 instruction
149 set Inst{29-0} = disp;
154 // Section A.9: Compare and Swap - p176
155 // CASA/CASXA: are for alternate address spaces! Ignore them
158 // Section A.10: Divide (64-bit / 32-bit) - p178
159 // Not used in the Sparc backend
161 set isDeprecated = 1 in {
162 def UDIVr : F3_1<2, 0b001110, "udiv">; // udiv r, r, r
163 def UDIVi : F3_2<2, 0b001110, "udiv">; // udiv r, r, i
164 def SDIVr : F3_1<2, 0b001111, "sdiv">; // sdiv r, r, r
165 def SDIVi : F3_2<2, 0b001111, "sdiv">; // sdiv r, r, i
166 def UDIVCCr : F3_1<2, 0b011110, "udivcc">; // udivcc r, r, r
167 def UDIVCCi : F3_2<2, 0b011110, "udivcc">; // udivcc r, r, i
168 def SDIVCCr : F3_1<2, 0b011111, "sdivcc">; // sdivcc r, r, r
169 def SDIVCCi : F3_2<2, 0b011111, "sdivcc">; // sdivcc r, r, i
173 // Section A.11: DONE and RETRY - p181
174 // Not used in the Sparc backend
176 set isPrivileged = 1 in {
177 def DONE : F3_18<0, "done">; // done
178 def RETRY : F3_18<1, "retry">; // retry
182 // Section A.12: Floating-Point Add and Subtract - p182
183 def FADDS : F3_16<2, 0b110100, 0x41, "fadds">; // fadds f, f, f
184 def FADDD : F3_16<2, 0b110100, 0x42, "faddd">; // faddd f, f, f
185 def FADDQ : F3_16<2, 0b110100, 0x43, "faddq">; // faddq f, f, f
186 def FSUBS : F3_16<2, 0b110100, 0x45, "fsubs">; // fsubs f, f, f
187 def FSUBD : F3_16<2, 0b110100, 0x46, "fsubd">; // fsubd f, f, f
188 def FSUBQ : F3_16<2, 0b110100, 0x47, "fsubq">; // fsubq f, f, f
190 // Section A.13: Floating-point compare - p159
191 def FCMPS : F3_15<2, 0b110101, 0b010100001, "fcmps">; // fcmps %fcc, r1, r2
192 def FCMPD : F3_15<2, 0b110101, 0b010100010, "fcmpd">; // fcmpd %fcc, r1, r2
193 def FCMPQ : F3_15<2, 0b110101, 0b010100011, "fcmpq">; // fcmpq %fcc, r1, r2
194 // Currently unused in the Sparc backend
196 def FCMPES : F3_15<2, 0b110101, 0b010100101, "fcmpes">; // fcmpes %fcc, r1, r2
197 def FCMPED : F3_15<2, 0b110101, 0b010100110, "fcmped">; // fcmped %fcc, r1, r2
198 def FCMPEQ : F3_15<2, 0b110101, 0b010100111, "fcmpeq">; // fcmpeq %fcc, r1, r2
201 // Section A.14: Convert floating-point to integer - p161
202 def FSTOX : F3_14<2, 0b110100, 0b010000001, "fstox">; // fstox rs2, rd
203 def FDTOX : F3_14<2, 0b110100, 0b010000010, "fstox">; // fstox rs2, rd
204 def FQTOX : F3_14<2, 0b110100, 0b010000011, "fstox">; // fstox rs2, rd
205 def FSTOI : F3_14<2, 0b110100, 0b011010001, "fstoi">; // fstoi rs2, rd
206 def FDTOI : F3_14<2, 0b110100, 0b011010010, "fdtoi">; // fdtoi rs2, rd
207 def FQTOI : F3_14<2, 0b110100, 0b011010011, "fqtoi">; // fqtoi rs2, rd
209 // Section A.15: Convert between floating-point formats - p162
210 def FSTOD : F3_14<2, 0b110100, 0b011001001, "fstod">; // fstod rs2, rd
211 def FSTOQ : F3_14<2, 0b110100, 0b011001101, "fstoq">; // fstoq rs2, rd
212 def FDTOS : F3_14<2, 0b110100, 0b011000110, "fstos">; // fstos rs2, rd
213 def FDTOQ : F3_14<2, 0b110100, 0b011001110, "fdtoq">; // fdtoq rs2, rd
214 def FQTOS : F3_14<2, 0b110100, 0b011000111, "fqtos">; // fqtos rs2, rd
215 def FQTOD : F3_14<2, 0b110100, 0b011001011, "fqtod">; // fqtod rs2, rd
217 // Section A.16: Convert integer to floating-point - p163
218 def FXTOS : F3_14<2, 0b110100, 0b010000100, "fxtos">; // fxtos rs2, rd
219 def FXTOD : F3_14<2, 0b110100, 0b010001000, "fxtod">; // fxtod rs2, rd
220 def FXTOQ : F3_14<2, 0b110100, 0b010001100, "fxtoq">; // fxtoq rs2, rd
221 def FITOS : F3_14<2, 0b110100, 0b011000100, "fitos">; // fitos rs2, rd
222 def FITOD : F3_14<2, 0b110100, 0b011001000, "fitod">; // fitod rs2, rd
223 def FITOQ : F3_14<2, 0b110100, 0b011001100, "fitoq">; // fitoq rs2, rd
225 // Section A.17: Floating-Point Move - p164
226 def FMOVS : F3_14<2, 0b110100, 0b000000001, "fmovs">; // fmovs r, r
227 def FMOVD : F3_14<2, 0b110100, 0b000000010, "fmovs">; // fmovd r, r
228 //def FMOVQ : F3_14<2, 0b110100, 0b000000011, "fmovs">; // fmovq r, r
229 def FNEGS : F3_14<2, 0b110100, 0b000000101, "fnegs">; // fnegs r, r
230 def FNEGD : F3_14<2, 0b110100, 0b000000110, "fnegs">; // fnegs r, r
231 //def FNEGQ : F3_14<2, 0b110100, 0b000000111, "fnegs">; // fnegs r, r
232 def FABSS : F3_14<2, 0b110100, 0b000001001, "fabss">; // fabss r, r
233 def FABSD : F3_14<2, 0b110100, 0b000001010, "fabss">; // fabss r, r
234 //def FABSQ : F3_14<2, 0b110100, 0b000001011, "fabss">; // fabss r, r
236 // Section A.18: Floating-Point Multiply and Divide - p165
237 def FMULS : F3_16<2, 0b110100, 0b001001001, "fmuls">; // fmuls r, r, r
238 def FMULD : F3_16<2, 0b110100, 0b001001010, "fmuld">; // fmuld r, r, r
239 def FMULQ : F3_16<2, 0b110100, 0b001001011, "fmulq">; // fmulq r, r, r
240 def FSMULD : F3_16<2, 0b110100, 0b001101001, "fsmuld">; // fsmuls r, r, r
241 def FDMULQ : F3_16<2, 0b110100, 0b001101110, "fdmulq">; // fdmuls r, r, r
242 def FDIVS : F3_16<2, 0b110100, 0b001001101, "fdivs">; // fdivs r, r, r
243 def FDIVD : F3_16<2, 0b110100, 0b001001110, "fdivs">; // fdivd r, r, r
244 def FDIVQ : F3_16<2, 0b110100, 0b001001111, "fdivs">; // fdivq r, r, r
246 // Section A.19: Floating-Point Square Root - p166
247 def FSQRTS : F3_14<2, 0b110100, 0b000101001, "fsqrts">; // fsqrts r, r
248 def FSQRTD : F3_14<2, 0b110100, 0b000101010, "fsqrts">; // fsqrts r, r
249 def FSQRTQ : F3_14<2, 0b110100, 0b000101011, "fsqrts">; // fsqrts r, r
251 // FIXME: A.20: Flush Instruction Memory - p167
252 // FIXME: A.21: Flush Register Windows - p169
254 // A.22: Illegal instruction Trap - p170
255 // Not currently used
257 // A.23: Implementation-Dependent Instructions - p171
258 // Not currently used
260 // Section A.24: Jump and Link - p172
261 // Mimicking the Sparc's instr def...
262 def JMPLCALLr : F3_1<2, 0b111000, "jmpl">; // jmpl [r+r], r
263 def JMPLCALLi : F3_2<2, 0b111000, "jmpl">; // jmpl [r+i], r
264 def JMPLRETr : F3_1<2, 0b111000, "jmpl">; // jmpl [r+r], r
265 def JMPLRETi : F3_2<2, 0b111000, "jmpl">; // jmpl [r+i], r
267 // Section A.25: Load Floating-Point - p173
268 def LDFr : F3_1<3, 0b100000, "ld">; // ld [r+r], r
269 def LDFi : F3_2<3, 0b100000, "ld">; // ld [r+i], r
270 def LDDFr : F3_1<3, 0b100011, "ldd">; // ldd [r+r], r
271 def LDDFi : F3_2<3, 0b100011, "ldd">; // ldd [r+i], r
272 def LDQFr : F3_1<3, 0b100010, "ldq">; // ldq [r+r], r
273 def LDQFi : F3_2<3, 0b100010, "ldq">; // ldq [r+i], r
274 set isDeprecated = 1 in {
276 def LDFSRr : F3_1<3, 0b100001, "ld">; // ld [r+r], r
277 def LDFSRi : F3_2<3, 0b100001, "ld">; // ld [r+i], r
281 def LDXFSRr : F3_1<3, 0b100001, "ldx">; // ldx [r+r], r
282 def LDXFSRi : F3_2<3, 0b100001, "ldx">; // ldx [r+i], r
285 // Section A.27: Load Integer - p178
286 def LDSBr : F3_1<3, 0b001001, "ldsb">; // ldsb [r+r], r
287 def LDSBi : F3_2<3, 0b001001, "ldsb">; // ldsb [r+i], r
288 def LDSHr : F3_1<3, 0b001010, "ldsh">; // ldsh [r+r], r
289 def LDSHi : F3_2<3, 0b001010, "ldsh">; // ldsh [r+i], r
290 def LDSWr : F3_1<3, 0b001000, "ldsw">; // ldsh [r+r], r
291 def LDSWi : F3_2<3, 0b001000, "ldsw">; // ldsh [r+i], r
292 def LDUBr : F3_1<3, 0b000001, "ldub">; // ldub [r+r], r
293 def LDUBi : F3_2<3, 0b000001, "ldub">; // ldub [r+i], r
294 def LDUHr : F3_1<3, 0b000010, "lduh">; // lduh [r+r], r
295 def LDUHi : F3_2<3, 0b000010, "lduh">; // lduh [r+i], r
297 def LDUWr : F3_1<3, 0b000000, "lduw">; // lduw [r+r], r
298 def LDUWi : F3_2<3, 0b000000, "lduw">; // lduw [r+i], r
299 // LDD should no longer be used, LDX should be used instead
300 def LDXr : F3_1<3, 0b001011, "ldx">; // ldx [r+r], r
301 def LDXi : F3_2<3, 0b001011, "ldx">; // ldx [r+i], r
303 set isDeprecated = 1 in {
304 def LDDr : F3_1<3, 0b000011, "ldd">; // ldd [r+r], r
305 def LDDi : F3_2<3, 0b000011, "ldd">; // ldd [r+i], r
309 // Section A.31: Logical operations
310 def ANDr : F3_1<2, 0b000001, "and">; // and r, r, r
311 def ANDi : F3_2<2, 0b000001, "and">; // and r, r, i
312 def ANDccr : F3_1<2, 0b010001, "andcc">; // andcc r, r, r
313 def ANDcci : F3_2<2, 0b010001, "andcc">; // andcc r, r, i
314 def ANDNr : F3_1<2, 0b000101, "andn">; // andn r, r, r
315 def ANDNi : F3_2<2, 0b000101, "andn">; // andn r, r, i
316 def ANDNccr : F3_1<2, 0b010101, "andncc">; // andncc r, r, r
317 def ANDNcci : F3_2<2, 0b010101, "andncc">; // andncc r, r, i
319 def ORr : F3_1<2, 0b000010, "or">; // or r, r, r
320 def ORi : F3_2<2, 0b000010, "or">; // or r, r, i
321 def ORccr : F3_1<2, 0b010010, "orcc">; // orcc r, r, r
322 def ORcci : F3_2<2, 0b010010, "orcc">; // orcc r, r, i
323 def ORNr : F3_1<2, 0b000110, "orn">; // orn r, r, r
324 def ORNi : F3_2<2, 0b000110, "orn">; // orn r, r, i
325 def ORNccr : F3_1<2, 0b010110, "orncc">; // orncc r, r, r
326 def ORNcci : F3_2<2, 0b010110, "orncc">; // orncc r, r, i
328 def XORr : F3_1<2, 0b000011, "xor">; // xor r, r, r
329 def XORi : F3_2<2, 0b000011, "xor">; // xor r, r, i
330 def XORccr : F3_1<2, 0b010011, "xorcc">; // xorcc r, r, r
331 def XORcci : F3_2<2, 0b010011, "xorcc">; // xorcc r, r, i
332 def XNORr : F3_1<2, 0b000111, "xnor">; // xnor r, r, r
333 def XNORi : F3_2<2, 0b000111, "xnor">; // xnor r, r, i
334 def XNORccr : F3_1<2, 0b010111, "xnorcc">; // xnorcc r, r, r
335 def XNORcci : F3_2<2, 0b010111, "xnorcc">; // xnorcc r, r, i
337 // Section A.32: Memory Barrier - p186
338 // Not currently used in the Sparc backend
340 // Section A.33: Move Floating-Point Register on Condition (FMOVcc)
342 // For integer condition codes
343 def FMOVA : F4_7<2, 0b110101, 0b1000, "fmova">; // fmova r, r
344 def FMOVN : F4_7<2, 0b110101, 0b0000, "fmovn">; // fmovn r, r
345 def FMOVNE : F4_7<2, 0b110101, 0b1001, "fmovne">; // fmovne r, r
346 def FMOVE : F4_7<2, 0b110101, 0b0000, "fmove">; // fmove r, r
347 def FMOVG : F4_7<2, 0b110101, 0b1010, "fmovg">; // fmovg r, r
348 def FMOVLE : F4_7<2, 0b110101, 0b0000, "fmovle">; // fmovle r, r
349 def FMOVGE : F4_7<2, 0b110101, 0b1011, "fmovge">; // fmovge r, r
350 def FMOVL : F4_7<2, 0b110101, 0b0011, "fmovl">; // fmovl r, r
351 def FMOVGU : F4_7<2, 0b110101, 0b1100, "fmovgu">; // fmovgu r, r
352 def FMOVLEU : F4_7<2, 0b110101, 0b0100, "fmovleu">; // fmovleu r, r
353 def FMOVCC : F4_7<2, 0b110101, 0b1101, "fmovcc">; // fmovcc r, r
354 def FMOVCS : F4_7<2, 0b110101, 0b0101, "fmovcs">; // fmovcs r, r
355 def FMOVPOS : F4_7<2, 0b110101, 0b1110, "fmovpos">; // fmovpos r, r
356 def FMOVNEG : F4_7<2, 0b110101, 0b0110, "fmovneg">; // fmovneg r, r
357 def FMOVVC : F4_7<2, 0b110101, 0b1111, "fmovvc">; // fmovvc r, r
358 def FMOVVS : F4_7<2, 0b110101, 0b0111, "fmovvs">; // fmovvs r, r
360 // For floating-point condition codes
361 def FMOVFA : F4_7<2, 0b110101, 0b0100, "fmovfa">; // fmovfa r, r
362 def FMOVFN : F4_7<2, 0b110101, 0b0000, "fmovfn">; // fmovfa r, r
363 def FMOVFU : F4_7<2, 0b110101, 0b0111, "fmovfu">; // fmovfu r, r
364 def FMOVFG : F4_7<2, 0b110101, 0b0110, "fmovfg">; // fmovfg r, r
365 def FMOVFUG : F4_7<2, 0b110101, 0b0101, "fmovfug">; // fmovfug r, r
366 def FMOVFL : F4_7<2, 0b110101, 0b0100, "fmovfl">; // fmovfl r, r
367 def FMOVFUL : F4_7<2, 0b110101, 0b0011, "fmovful">; // fmovful r, r
368 def FMOVFLG : F4_7<2, 0b110101, 0b0010, "fmovflg">; // fmovflg r, r
369 def FMOVFNE : F4_7<2, 0b110101, 0b0001, "fmovfne">; // fmovfne r, r
370 def FMOVFE : F4_7<2, 0b110101, 0b1001, "fmovfe">; // fmovfe r, r
371 def FMOVFUE : F4_7<2, 0b110101, 0b1010, "fmovfue">; // fmovfue r, r
372 def FMOVGE : F4_7<2, 0b110101, 0b1011, "fmovge">; // fmovge r, r
373 def FMOVFUGE : F4_7<2, 0b110101, 0b1100, "fmovfuge">; // fmovfuge r, r
374 def FMOVFLE : F4_7<2, 0b110101, 0b1101, "fmovfle">; // fmovfle r, r
375 def FMOVFULE : F4_7<2, 0b110101, 0b1110, "fmovfule">; // fmovfule r, r
376 def FMOVFO : F4_7<2, 0b110101, 0b1111, "fmovfo">; // fmovfo r, r
379 // Section A.34: Move FP Register on Integer Register condition (FMOVr) - p192
380 def FMOVRSZ : F4_6<2, 0b110101, 0b001, 0b00101, "fmovrsz">; //fmovsrz r,r,rd
381 def FMOVRSLEZ : F4_6<2, 0b110101, 0b010, 0b00101, "fmovrslez">;//fmovsrz r,r,rd
382 def FMOVRSLZ : F4_6<2, 0b110101, 0b011, 0b00101, "fmovrslz">; //fmovsrz r,r,rd
383 def FMOVRSNZ : F4_6<2, 0b110101, 0b101, 0b00101, "fmovrsne">; //fmovsrz r,r,rd
384 def FMOVRSGZ : F4_6<2, 0b110101, 0b110, 0b00101, "fmovrsgz">; //fmovsrz r,r,rd
385 def FMOVRSGEZ : F4_6<2, 0b110101, 0b111, 0b00101, "fmovrsgez">;//fmovsrz r,r,rd
387 def FMOVRDZ : F4_6<2, 0b110101, 0b001, 0b00110, "fmovrdz">; //fmovsrz r,r,rd
388 def FMOVRDLEZ : F4_6<2, 0b110101, 0b010, 0b00110, "fmovrdlez">;//fmovsrz r,r,rd
389 def FMOVRDLZ : F4_6<2, 0b110101, 0b011, 0b00110, "fmovrdlz">; //fmovsrz r,r,rd
390 def FMOVRDNZ : F4_6<2, 0b110101, 0b101, 0b00110, "fmovrdne">; //fmovsrz r,r,rd
391 def FMOVRDGZ : F4_6<2, 0b110101, 0b110, 0b00110, "fmovrdgz">; //fmovsrz r,r,rd
392 def FMOVRDGEZ : F4_6<2, 0b110101, 0b111, 0b00110, "fmovrdgez">;//fmovsrz r,r,rd
394 def FMOVRQZ : F4_6<2, 0b110101, 0b001, 0b00111, "fmovrqz">; //fmovsrz r,r,rd
395 def FMOVRQLEZ : F4_6<2, 0b110101, 0b010, 0b00111, "fmovrqlez">;//fmovsrz r,r,rd
396 def FMOVRQLZ : F4_6<2, 0b110101, 0b011, 0b00111, "fmovrqlz">; //fmovsrz r,r,rd
397 def FMOVRQNZ : F4_6<2, 0b110101, 0b101, 0b00111, "fmovrqne">; //fmovsrz r,r,rd
398 def FMOVRQGZ : F4_6<2, 0b110101, 0b110, 0b00111, "fmovrqgz">; //fmovsrz r,r,rd
399 def FMOVRQGEZ : F4_6<2, 0b110101, 0b111, 0b00111, "fmovrqgez">;//fmovsrz r,r,rd
402 // Section A.35: Move Integer Register on Condition (MOVcc) - p194
403 // For integer condition codes
404 def MOVAr : F4_3<2, 0b101100, 0b1000, "mova">; // mova i/xcc, rs2, rd
405 def MOVAi : F4_4<2, 0b101100, 0b1000, "mova">; // mova i/xcc, rs2, rd
406 def MOVNr : F4_3<2, 0b101100, 0b0000, "movn">; // mova i/xcc, rs2, rd
407 def MOVNi : F4_4<2, 0b101100, 0b0000, "movn">; // mova i/xcc, rs2, rd
408 def MOVNEr : F4_3<2, 0b101100, 0b1001, "movne">; // mova i/xcc, rs2, rd
409 def MOVNEi : F4_4<2, 0b101100, 0b1001, "movne">; // mova i/xcc, rs2, rd
410 def MOVEr : F4_3<2, 0b101100, 0b0001, "move">; // mova i/xcc, rs2, rd
411 def MOVEi : F4_4<2, 0b101100, 0b0001, "move">; // mova i/xcc, rs2, rd
412 def MOVGr : F4_3<2, 0b101100, 0b1010, "movg">; // mova i/xcc, rs2, rd
413 def MOVGi : F4_4<2, 0b101100, 0b1010, "movg">; // mova i/xcc, rs2, rd
414 def MOVLEr : F4_3<2, 0b101100, 0b0010, "movle">; // mova i/xcc, rs2, rd
415 def MOVLEi : F4_4<2, 0b101100, 0b0010, "movle">; // mova i/xcc, rs2, rd
416 def MOVGEr : F4_3<2, 0b101100, 0b1011, "movge">; // mova i/xcc, rs2, rd
417 def MOVGEi : F4_4<2, 0b101100, 0b1011, "movge">; // mova i/xcc, rs2, rd
418 def MOVLr : F4_3<2, 0b101100, 0b0011, "movl">; // mova i/xcc, rs2, rd
419 def MOVLi : F4_4<2, 0b101100, 0b0011, "movl">; // mova i/xcc, rs2, rd
420 def MOVGUr : F4_3<2, 0b101100, 0b1100, "movgu">; // mova i/xcc, rs2, rd
421 def MOVGUi : F4_4<2, 0b101100, 0b1100, "movgu">; // mova i/xcc, rs2, rd
422 def MOVLEUr : F4_3<2, 0b101100, 0b0100, "movleu">; // mova i/xcc, rs2, rd
423 def MOVLEUi : F4_4<2, 0b101100, 0b0100, "movleu">; // mova i/xcc, rs2, rd
424 def MOVCCr : F4_3<2, 0b101100, 0b1101, "movcc">; // mova i/xcc, rs2, rd
425 def MOVCCi : F4_4<2, 0b101100, 0b1101, "movcc">; // mova i/xcc, rs2, rd
426 def MOVCSr : F4_3<2, 0b101100, 0b0101, "movcs">; // mova i/xcc, rs2, rd
427 def MOVCSi : F4_4<2, 0b101100, 0b0101, "movcs">; // mova i/xcc, rs2, rd
428 def MOVPOSr : F4_3<2, 0b101100, 0b1110, "movpos">; // mova i/xcc, rs2, rd
429 def MOVPOSi : F4_4<2, 0b101100, 0b1110, "movpos">; // mova i/xcc, rs2, rd
430 def MOVNEGr : F4_3<2, 0b101100, 0b0110, "movneg">; // mova i/xcc, rs2, rd
431 def MOVNEGi : F4_4<2, 0b101100, 0b0110, "movneg">; // mova i/xcc, rs2, rd
432 def MOVVCr : F4_3<2, 0b101100, 0b1111, "movvc">; // mova i/xcc, rs2, rd
433 def MOVVCi : F4_4<2, 0b101100, 0b1111, "movvc">; // mova i/xcc, rs2, rd
434 def MOVVSr : F4_3<2, 0b101100, 0b0111, "movvs">; // mova i/xcc, rs2, rd
435 def MOVVSi : F4_4<2, 0b101100, 0b0111, "movvs">; // mova i/xcc, rs2, rd
437 // For floating-point condition codes
438 def MOVFAr : F4_3<2, 0b101100, 0b1000, "movfa">; // mova i/xcc, rs2, rd
439 def MOVFAi : F4_4<2, 0b101100, 0b1000, "movfa">; // mova i/xcc, rs2, rd
440 def MOVFNr : F4_3<2, 0b101100, 0b0000, "movfn">; // mova i/xcc, rs2, rd
441 def MOVFNi : F4_4<2, 0b101100, 0b0000, "movfn">; // mova i/xcc, rs2, rd
442 def MOVFUr : F4_3<2, 0b101100, 0b0111, "movfu">; // mova i/xcc, rs2, rd
443 def MOVFUi : F4_4<2, 0b101100, 0b0111, "movfu">; // mova i/xcc, rs2, rd
444 def MOVFGr : F4_3<2, 0b101100, 0b0110, "movfg">; // mova i/xcc, rs2, rd
445 def MOVFGi : F4_4<2, 0b101100, 0b0110, "movfg">; // mova i/xcc, rs2, rd
446 def MOVFUGr : F4_3<2, 0b101100, 0b0101, "movfug">; // mova i/xcc, rs2, rd
447 def MOVFUGi : F4_4<2, 0b101100, 0b0101, "movfug">; // mova i/xcc, rs2, rd
448 def MOVFLr : F4_3<2, 0b101100, 0b0100, "movfl">; // mova i/xcc, rs2, rd
449 def MOVFLi : F4_4<2, 0b101100, 0b0100, "movfl">; // mova i/xcc, rs2, rd
450 def MOVFULr : F4_3<2, 0b101100, 0b0011, "movful">; // mova i/xcc, rs2, rd
451 def MOVFULi : F4_4<2, 0b101100, 0b0011, "movful">; // mova i/xcc, rs2, rd
452 def MOVFLGr : F4_3<2, 0b101100, 0b0010, "movflg">; // mova i/xcc, rs2, rd
453 def MOVFLGi : F4_4<2, 0b101100, 0b0010, "movflg">; // mova i/xcc, rs2, rd
454 def MOVFNEr : F4_3<2, 0b101100, 0b0001, "movfne">; // mova i/xcc, rs2, rd
455 def MOVFNEi : F4_4<2, 0b101100, 0b0001, "movfne">; // mova i/xcc, rs2, rd
456 def MOVFEr : F4_3<2, 0b101100, 0b1001, "movfe">; // mova i/xcc, rs2, rd
457 def MOVFEi : F4_4<2, 0b101100, 0b1001, "movfe">; // mova i/xcc, rs2, rd
458 def MOVFUEr : F4_3<2, 0b101100, 0b1010, "movfue">; // mova i/xcc, rs2, rd
459 def MOVFUEi : F4_4<2, 0b101100, 0b1010, "movfue">; // mova i/xcc, rs2, rd
460 def MOVFGEr : F4_3<2, 0b101100, 0b1011, "movfge">; // mova i/xcc, rs2, rd
461 def MOVFGEi : F4_4<2, 0b101100, 0b1011, "movfge">; // mova i/xcc, rs2, rd
462 def MOVFUGEr : F4_3<2, 0b101100, 0b1100, "movfuge">; // mova i/xcc, rs2, rd
463 def MOVFUGEi : F4_4<2, 0b101100, 0b1100, "movfuge">; // mova i/xcc, rs2, rd
464 def MOVFLEr : F4_3<2, 0b101100, 0b1101, "movfle">; // mova i/xcc, rs2, rd
465 def MOVFLEi : F4_4<2, 0b101100, 0b1101, "movfle">; // mova i/xcc, rs2, rd
466 def MOVFULEr : F4_3<2, 0b101100, 0b1110, "movfule">; // mova i/xcc, rs2, rd
467 def MOVFULEi : F4_4<2, 0b101100, 0b1110, "movfule">; // mova i/xcc, rs2, rd
468 def MOVFOr : F4_3<2, 0b101100, 0b1111, "movfo">; // mova i/xcc, rs2, rd
469 def MOVFOi : F4_4<2, 0b101100, 0b1111, "movfo">; // mova i/xcc, rs2, rd
471 // Section A.36: Move Integer Register on Register Condition (MOVR)
472 def MOVRZr : F3_5<2, 0b101111, 0b001, "movrz">; // movrz rs1, rs2, rd
473 def MOVRZi : F3_6<2, 0b101111, 0b001, "movrz">; // movrz rs1, imm, rd
474 def MOVRLEZr : F3_5<2, 0b101111, 0b010, "movrlez">; // movrz rs1, rs2, rd
475 def MOVRLEZi : F3_6<2, 0b101111, 0b010, "movrlez">; // movrz rs1, imm, rd
476 def MOVRLZr : F3_5<2, 0b101111, 0b011, "movrlz">; // movrz rs1, rs2, rd
477 def MOVRLZi : F3_6<2, 0b101111, 0b011, "movrlz">; // movrz rs1, imm, rd
478 def MOVRNZr : F3_5<2, 0b101111, 0b101, "movrnz">; // movrz rs1, rs2, rd
479 def MOVRNZi : F3_6<2, 0b101111, 0b101, "movrnz">; // movrz rs1, imm, rd
480 def MOVRGZr : F3_5<2, 0b101111, 0b110, "movrgz">; // movrz rs1, rs2, rd
481 def MOVRGZi : F3_6<2, 0b101111, 0b110, "movrgz">; // movrz rs1, imm, rd
482 def MOVRGEZr : F3_5<2, 0b101111, 0b111, "movrgez">; // movrz rs1, rs2, rd
483 def MOVRGEZi : F3_6<2, 0b101111, 0b111, "movrgez">; // movrz rs1, imm, rd
485 // Section A.37: Multiply and Divide (64-bit) - p199
486 def MULXr : F3_1<2, 0b001001, "mulx">; // mulx r, r, r
487 def SDIVXr : F3_1<2, 0b101101, "sdivx">; // mulx r, r, r
488 def UDIVXr : F3_1<2, 0b001101, "udivx">; // mulx r, r, r
489 def MULXi : F3_2<2, 0b001001, "mulx">; // mulx r, i, r
490 def SDIVXi : F3_2<2, 0b101101, "sdivx">; // mulx r, i, r
491 def UDIVXi : F3_2<2, 0b001101, "udivx">; // mulx r, i, r
493 // Section A.38: Multiply (32-bit) - p200
494 // Not used in the Sparc backend
496 set Inst{13} = 0 in {
497 def UMULr : F3_1<2, 0b001010, "umul">; // umul r, r, r
498 def SMULr : F3_1<2, 0b001011, "smul">; // smul r, r, r
499 def UMULCCr : F3_1<2, 0b011010, "umulcc">; // mulcc r, r, r
500 def SMULCCr : F3_1<2, 0b011011, "smulcc">; // smulcc r, r, r
502 set Inst{13} = 1 in {
503 def UMULi : F3_1<2, 0b001010, "umul">; // umul r, i, r
504 def SMULi : F3_1<2, 0b001011, "smul">; // smul r, i, r
505 def UMULCCi : F3_1<2, 0b011010, "umulcc">; // umulcc r, i, r
506 def SMULCCi : F3_1<2, 0b011011, "smulcc">; // smulcc r, i, r
510 // Section A.39: Multiply Step - p202
511 // Not currently used in the Sparc backend
513 // Section A.40: No operation - p204
514 // NOP is really a pseudo-instruction (special case of SETHI)
518 def NOP : F2_1<"nop">; // nop
523 // Section A.41: Population Count - p205
524 // Not currently used in the Sparc backend
526 // Section A.42: Prefetch Data - p206
527 // Not currently used in the Sparc backend
529 // Section A.43: Read Privileged Register - p211
530 // Not currently used in the Sparc backend
532 // Section A.44: Read State Register
533 // The only instr from this section currently used is RDCCR
535 def RDCCR : F3_17<2, 0b101000, "rd">; // rd %ccr, r
538 // Section A.45: RETURN - p216
539 set isReturn = 1 in {
540 def RETURNr : F3_3<2, 0b111001, "return">; // return
541 def RETURNi : F3_4<2, 0b111001, "return">; // return
544 // Section A.46: SAVE and RESTORE - p217
545 def SAVEr : F3_1<2, 0b111100, "save">; // save r, r, r
546 def SAVEi : F3_2<2, 0b111100, "save">; // save r, i, r
547 def RESTOREr : F3_1<2, 0b111101, "restore">; // restore r, r, r
548 def RESTOREi : F3_2<2, 0b111101, "restore">; // restore r, i, r
550 // Section A.47: SAVED and RESTORED - p219
551 // Not currently used in Sparc backend
553 // Section A.48: SETHI - p220
555 def SETHI : F2_1<"sethi">; // sethi
558 // Section A.49: Shift - p221
559 // Not currently used in the Sparc backend
561 uses 5 least significant bits of rs2
563 def SLLr5 : F3_11<2, 0b100101, "sll">; // sll r, r, r
564 def SRLr5 : F3_11<2, 0b100110, "srl">; // srl r, r, r
565 def SRAr5 : F3_11<2, 0b100111, "sra">; // sra r, r, r
566 def SLLXr5 : F3_11<2, 0b100101, "sllx">; // sllx r, r, r
567 def SRLXr5 : F3_11<2, 0b100110, "srlx">; // srlx r, r, r
568 def SRAXr5 : F3_11<2, 0b100111, "srax">; // srax r, r, r
572 // uses 6 least significant bits of rs2
574 def SLLr6 : F3_11<2, 0b100101, "sll">; // sll r, r, r
575 def SRLr6 : F3_11<2, 0b100110, "srl">; // srl r, r, r
576 def SRAr6 : F3_11<2, 0b100111, "sra">; // sra r, r, r
577 def SLLXr6 : F3_11<2, 0b100101, "sllx">; // sllx r, r, r
578 def SRLXr6 : F3_11<2, 0b100110, "srlx">; // srlx r, r, r
579 def SRAXr6 : F3_11<2, 0b100111, "srax">; // srax r, r, r
582 // Not currently used in the Sparc backend
584 def SLLi5 : F3_12<2, 0b100101, "sll">; // sll r, shcnt32, r
585 def SRLi5 : F3_12<2, 0b100110, "srl">; // srl r, shcnt32, r
586 def SRAi5 : F3_12<2, 0b100111, "sra">; // sra r, shcnt32, r
587 def SLLXi5 : F3_12<2, 0b100101, "sllx">; // sllx r, shcnt32, r
588 def SRLXi5 : F3_12<2, 0b100110, "srlx">; // srlx r, shcnt32, r
589 def SRAXi5 : F3_12<2, 0b100111, "srax">; // srax r, shcnt32, r
592 def SLLi6 : F3_13<2, 0b100101, "sll">; // sll r, shcnt64, r
593 def SRLi6 : F3_13<2, 0b100110, "srl">; // srl r, shcnt64, r
594 def SRAi6 : F3_13<2, 0b100111, "sra">; // sra r, shcnt64, r
595 def SLLXi6 : F3_13<2, 0b100101, "sllx">; // sllx r, shcnt64, r
596 def SRLXi6 : F3_13<2, 0b100110, "srlx">; // srlx r, shcnt64, r
597 def SRAXi6 : F3_13<2, 0b100111, "srax">; // srax r, shcnt64, r
599 // Section A.50: Sofware-Initiated Reset - p223
600 // Not currently used in the Sparc backend
602 // Section A.51: Store Barrier - p224
603 // Not currently used in the Sparc backend
605 // Section A.52: Store Floating-point -p225
606 def STFr : F3_1rd<3, 0b100100, "st">; // st r, [r+r]
607 def STFi : F3_2rd<3, 0b100100, "st">; // st r, [r+i]
608 def STDFr : F3_1rd<3, 0b100111, "std">; // std r, [r+r]
609 def STDFi : F3_2rd<3, 0b100111, "std">; // std r, [r+i]
611 // Not currently used in the Sparc backend
613 def STQFr : F3_1rd<3, 0b100110, "stq">; // stq r, [r+r]
614 def STQFi : F3_2rd<3, 0b100110, "stq">; // stq r, [r+i]
617 set isDeprecated = 1 in {
618 def STFSRr : F3_1<3, 0b100101, "st">; // st r, [r+r]
619 def STFSRi : F3_2<3, 0b100101, "st">; // st r, [r+i]
621 def STXFSRr : F3_1<3, 0b100101, "stq">; // stx r, [r+r]
622 def STXFSRi : F3_2<3, 0b100101, "stq">; // stx r, [r+i]
624 // Section A.53: Store Floating-Point into Alternate Space - p227
625 // Not currently used in the Sparc backend
627 // Section A.54: Store Integer - p229
628 def STBr : F3_1<3, 0b000101, "stb">; // stb r, [r+r]
629 def STBi : F3_2<3, 0b000101, "stb">; // stb r, [r+i]
630 def STHr : F3_1<3, 0b000110, "stb">; // stb r, [r+r]
631 def STHi : F3_2<3, 0b000110, "stb">; // stb r, [r+i]
632 def STWr : F3_1<3, 0b000100, "stb">; // stb r, [r+r]
633 def STWi : F3_2<3, 0b000100, "stb">; // stb r, [r+i]
634 def STXr : F3_1<3, 0b001110, "stb">; // stb r, [r+r]
635 def STXi : F3_2<3, 0b001110, "stb">; // stb r, [r+i]
637 // Section A.55: Store Integer into Alternate Space - p231
638 // Not currently used in the Sparc backend
640 // Section A.56: Subtract - p233
641 def SUBr : F3_1<2, 0b000100, "sub">; // sub r, r, r
642 def SUBi : F3_1<2, 0b000100, "sub">; // sub r, i, r
643 def SUBccr : F3_1<2, 0b010100, "subcc">; // subcc r, r, r
644 def SUBcci : F3_1<2, 0b010100, "subcc">; // subcc r, i, r
645 def SUBCr : F3_1<2, 0b001100, "subc">; // subc r, r, r
646 def SUBCi : F3_1<2, 0b001100, "subc">; // subc r, i, r
647 def SUBCccr : F3_1<2, 0b011100, "subccc">; // subccc r, r, r
648 def SUBCcci : F3_1<2, 0b011100, "subccc">; // subccc r, i, r