1 //===- Sparc.td - Target Description for Sparc V9 Target --------*- C++ -*-===//
3 //===----------------------------------------------------------------------===//
5 //===----------------------------------------------------------------------===//
6 // Target-Independent interface
7 //===----------------------------------------------------------------------===//
10 string Namespace = "";
15 string Name; // The opcode string for this instruction
16 string Namespace = "";
18 list<Register> Uses = []; // Default to using no non-operand registers
19 list<Register> Defs = []; // Default to modifying no non-operand registers
21 // These bits capture information about the high-level semantics of the
23 bit isReturn = 0; // Is this instruction a return instruction?
24 bit isBranch = 0; // Is this instruction a branch instruction?
25 bit isCall = 0; // Is this instruction a call instruction?
29 //===----------------------------------------------------------------------===//
30 // Declarations that describe the Sparc register file
31 //===----------------------------------------------------------------------===//
33 class V9Reg : Register { set Namespace = "SparcV9"; }
35 // Ri - One of the 32 64 bit integer registers
36 class Ri<bits<5> num> : V9Reg { set Size = 64; field bits<5> Num = num; }
38 def G0 : Ri< 0>; def G1 : Ri< 1>; def G2 : Ri< 2>; def G3 : Ri< 3>;
39 def G4 : Ri< 4>; def G5 : Ri< 5>; def G6 : Ri< 6>; def G7 : Ri< 7>;
40 def O0 : Ri< 8>; def O1 : Ri< 9>; def O2 : Ri<10>; def O3 : Ri<11>;
41 def O4 : Ri<12>; def O5 : Ri<13>; def O6 : Ri<14>; def O7 : Ri<15>;
42 def L0 : Ri<16>; def L1 : Ri<17>; def L2 : Ri<18>; def L3 : Ri<19>;
43 def L4 : Ri<20>; def L5 : Ri<21>; def L6 : Ri<22>; def L7 : Ri<23>;
44 def I0 : Ri<24>; def I1 : Ri<25>; def I2 : Ri<26>; def I3 : Ri<27>;
45 def I4 : Ri<28>; def I5 : Ri<29>; def I6 : Ri<30>; def I7 : Ri<31>;
46 // Floating-point registers?
50 //===----------------------------------------------------------------------===//
51 // This is temporary testing stuff.....
52 //===----------------------------------------------------------------------===//
54 class InstV9 : Instruction { // Sparc instruction baseline
57 set Namespace = "SparcV9";
60 set Inst{31-30} = op; // Top two bits are the 'op' field
62 // Bit attributes specific to Sparc instructions
63 bit isPasi = 0; // Does this instruction affect an alternate addr space?
64 bit isDeprecated = 0; // Is this instruction deprecated?
65 bit isPrivileged = 0; // Is this a privileged instruction?
69 //===----------------------------------------------------------------------===//
72 class F2 : InstV9 { // Format 2 instructions
75 set Inst{24-22} = op2;
78 // Format 2.1 instructions
79 class F2_1<string name> : F2 {
88 class F2_br : F2 { // Format 2 Branch instruction
89 bit annul; // All branches have an annul bit
91 set isBranch = 1; // All instances are branch instructions
94 class F2_2<bits<4> cond, string name> : F2_br { // Format 2.2 instructions
98 set Inst{28-25} = cond;
99 set Inst{21-0} = disp;
102 class F2_3<bits<4> cond, string name> : F2_br { // Format 2.3 instructions
108 set Inst{28-25} = cond;
109 set Inst{21-20} = cc;
110 set Inst{19} = predict;
111 set Inst{18-0} = disp;
114 class F2_4<bits<3> rcond, string name> : F2_br { // Format 2.4 instructions
115 // Variables exposed by the instruction...
122 set Inst{27-25} = rcond;
123 // Inst{24-22} = op2 field
124 set Inst{21-20} = disp{15-14};
125 set Inst{19} = predict;
126 set Inst{18-14} = rs1;
127 set Inst{13-0 } = disp{13-0};
131 //===----------------------------------------------------------------------===//
135 // F3 - Common superclass of all F3 instructions. All instructions have an op3
139 set op{1} = 1; // Op = 2 or 3
140 set Inst{24-19} = op3;
143 // F3_rs1 - Common superclass of instructions that use rs1
146 set Inst{18-14} = rs1;
149 // F3_rs1rd - Common superclass of instructions that use rs1 & rd...
150 class F3_rs1rd : F3 {
151 // Added rs1 here manually to have rd appear before rs1
152 // Formerly inherited directly from F3_rs1
155 set Inst{29-25} = rd;
156 set Inst{18-14} = rs1;
159 // F3_rs1rdrs2 - Common superclass of instructions with rs1, rd, & rs2 fields
160 class F3_rs1rdrs2 : F3_rs1rd {
165 // Specific F3 classes...
168 class F3_1<bits<2> opVal, bits<6> op3val, string name> : F3_rs1rdrs2 {
172 set Inst{13} = 0; // i field = 0
173 //set Inst{12-5} = dontcare;
176 class F3_2<bits<2> opVal, bits<6> op3val, string name> : F3_rs1rd {
182 set Inst{13} = 1; // i field = 1
183 set Inst{12-0} = simm;
186 class F3_3<bits<2> opVal, bits<6> op3val, string name> : F3_rs1 {
191 //set Inst{29-25} = dontcare;
193 //set Inst{12-5} = dontcare;
197 class F3_4<bits<2> opVal, bits<6> op3Val, string name> : F3_rs1 {
202 //set Inst{29-25} = dontcare;
204 set Inst{12-0} = simm;
207 class F3_11<bits<2> opVal, bits<6> op3Val, string name> : F3_rs1rdrs2 {
212 set Inst{13} = 0; // i field = 0
214 //set Inst{11-5} = dontcare;
217 class F3_12<bits<2> opVal, bits<6> op3Val, string name> : F3 {
221 set Inst{13} = 1; // i field = 1
222 set Inst{12} = 0; // x field = 0
223 //set Inst{11-5} = dontcare;
224 set Inst{4-0} = shcnt;
227 class F3_13<bits<2> opVal, bits<6> op3Val, string name> : F3 {
231 set Inst{13} = 1; // i field = 1
232 set Inst{12} = 1; // x field = 1
233 //set Inst{11-6} = dontcare;
234 set Inst{5-0} = shcnt;
237 class F3_14<bits<2> opVal, bits<6> op3val,
238 bits<9> opfval, string name> : F3_rs1rdrs2 {
242 //set Inst{18-14} = dontcare;
243 set Inst{13-5} = opfval;
246 class F3_16<bits<2> opVal, bits<6> op3val,
247 bits<9> opfval, string name> : F3_rs1rdrs2 {
251 set Inst{13-5} = opfval;
254 class F3_18<bits<5> fcn, string name> : F3 {
258 set Inst{29-25} = fcn;
259 //set Inst{18-0 } = dontcare;
262 //===----------------------------------------------------------------------===//
263 // Instruction list...
267 def ADDr : F3_1<2, 0b000000, "add">; // add r, r, r
268 def ADDi : F3_2<2, 0b000000, "add">; // add r, r, i
269 def ADDccr : F3_1<2, 0b010000, "addcc">; // addcc r, r, r
270 def ADDcci : F3_2<2, 0b010000, "addcc">; // addcc r, r, i
271 def ADDCr : F3_1<2, 0b001000, "addC">; // addC r, r, r
272 def ADDCi : F3_2<2, 0b001000, "addC">; // addC r, r, i
273 def ADDCccr : F3_1<2, 0b011000, "addCcc">; // addCcc r, r, r
274 def ADDCcci : F3_2<2, 0b011000, "addCcc">; // addCcc r, r, i
278 def BRZ : F2_4<0b001, "brz">; // Branch on rs1 == 0
279 def BRLEZ : F2_4<0b010, "brlez">; // Branch on rs1 <= 0
280 def BRLZ : F2_4<0b011, "brlz">; // Branch on rs1 < 0
281 def BRNZ : F2_4<0b101, "brnz">; // Branch on rs1 != 0
282 def BRGZ : F2_4<0b110, "brgz">; // Branch on rs1 > 0
283 def BRGEZ : F2_4<0b111, "brgez">; // Branch on rs1 >= 0
287 set isDeprecated = 1 in {
289 def FBA : F2_2<0b1000, "fba">; // Branch always
290 def FBN : F2_2<0b0000, "fbn">; // Branch never
291 def FBU : F2_2<0b0111, "fbu">; // Branch on unordered
292 def FBG : F2_2<0b0110, "fbg">; // Branch >
293 def FBUG : F2_2<0b0101, "fbug">; // Branch on unordered or >
294 def FBL : F2_2<0b0100, "fbl">; // Branch <
295 def FBUL : F2_2<0b0011, "fbul">; // Branch on unordered or <
296 def FBLG : F2_2<0b0010, "fblg">; // Branch < or >
297 def FBNE : F2_2<0b0001, "fbne">; // Branch !=
298 def FBE : F2_2<0b1001, "fbe">; // Branch ==
299 def FBUE : F2_2<0b1010, "fbue">; // Branch on unordered or ==
300 def FBGE : F2_2<0b1011, "fbge">; // Branch > or ==
301 def FBUGE : F2_2<0b1100, "fbuge">; // Branch unord or > or ==
302 def FBLE : F2_2<0b1101, "fble">; // Branch < or ==
303 def FBULE : F2_2<0b1110, "fbule">; // Branch unord or < or ==
304 def FBO : F2_2<0b1111, "fbo">; // Branch on ordered
309 //set op2 = 0b101 in {
310 //def FBPA : F2_3<0b1000, "fbpa">; // Branch always
311 //def FBPN : F2_3<0b0000, "fbpn">; // Branch never
312 //def FBPU : F2_3<0b0111, "fbpu">; // Branch on unordered
313 //def FBPG : F2_3<0b0110, "fbpg">; // Branch >
314 //def FBPUG : F2_3<0b0101, "fbpug">; // Branch on unordered or >
315 //def FBPL : F2_3<0b0100, "fbpl">; // Branch <
316 //def FBPUL : F2_3<0b0011, "fbpul">; // Branch on unordered or <
317 //def FBPLG : F2_3<0b0010, "fbplg">; // Branch < or >
318 //def FBPNE : F2_3<0b0001, "fbpne">; // Branch !=
319 //def FBPE : F2_3<0b1001, "fbpe">; // Branch ==
320 //def FBPUE : F2_3<0b1010, "fbpue">; // Branch on unordered or ==
321 //def FBPGE : F2_3<0b1011, "fbpge">; // Branch > or ==
322 //def FBPUGE : F2_3<0b1100, "fbpuge">; // Branch unord or > or ==
323 //def FBPLE : F2_3<0b1101, "fbple">; // Branch < or ==
324 //def FBPULE : F2_3<0b1110, "fbpule">; // Branch unord or < or ==
325 //def FBPO : F2_3<0b1111, "fbpo">; // Branch on ordered
328 // Section A.6: p170: Bicc
329 set isDeprecated = 1 in {
331 def BA : F2_2<0b1000, "ba">; // Branch always
332 def BN : F2_2<0b0000, "bn">; // Branch never
333 def BNE : F2_2<0b1001, "bne">; // Branch !=
334 def BE : F2_2<0b0001, "be">; // Branch ==
335 def BG : F2_2<0b1010, "bg">; // Branch >
336 def BLE : F2_2<0b0010, "ble">; // Branch <=
337 def BGE : F2_2<0b1011, "bge">; // Branch >=
338 def BL : F2_2<0b0011, "bl">; // Branch <
339 def BGU : F2_2<0b1100, "bgu">; // Branch unsigned >
340 def BLEU : F2_2<0b0100, "bleu">; // Branch unsigned <=
341 def BCC : F2_2<0b1101, "bcc">; // Branch unsigned >=
342 def BCS : F2_2<0b0101, "bcs">; // Branch unsigned <=
343 def BPOS : F2_2<0b1110, "bpos">; // Branch on positive
344 def BNEG : F2_2<0b0110, "bneg">; // Branch on negative
345 def BVC : F2_2<0b1111, "bvc">; // Branch on overflow clear
346 def BVS : F2_2<0b0111, "bvs">; // Branch on overflow set
351 //set op2 = 0b001 in {
352 // def BPA : F2_3<0b1000, "bpa">; // Branch always
353 // def BPN : F2_3<0b0000, "bpn">; // Branch never
354 // def BPNE : F2_3<0b1001, "bpne">; // Branch !=
355 // def BPE : F2_3<0b0001, "bpe">; // Branch ==
356 // def BPG : F2_3<0b1010, "bpg">; // Branch >
357 // def BPLE : F2_3<0b0010, "bple">; // Branch <=
358 // def BPGE : F2_3<0b1011, "bpge">; // Branch >=
359 // def BPL : F2_3<0b0011, "bpl">; // Branch <
360 // def BPGU : F2_3<0b1100, "bpgu">; // Branch unsigned >
361 // def BPLEU : F2_3<0b0100, "bpleu">; // Branch unsigned <=
362 // def BPCC : F2_3<0b1101, "bpcc">; // Branch unsigned >=
363 // def BPCS : F2_3<0b0101, "bpcs">; // Branch unsigned <=
364 // def BPPOS : F2_3<0b1110, "bppos">; // Branch on positive
365 // def BPNEG : F2_3<0b0110, "bpneg">; // Branch on negative
366 // def BPVC : F2_3<0b1111, "bpvc">; // Branch on overflow clear
367 // def BPVS : F2_3<0b0111, "bpvs">; // Branch on overflow set
370 // Section A.8: p175 - CALL - the only Format #1 instruction
374 set Inst{29-0} = disp;
379 // Section A.9: Compare and Swap - p176
380 // CASA/CASXA: are for alternate address spaces! Ignore them
383 // Section A.10: Divide (64-bit / 32-bit) - p178
384 // Not used in the Sparc backend
385 //set isDeprecated = 1 in {
386 //def UDIVr : F3_1<2, 0b001110, "udiv">; // udiv r, r, r
387 //def UDIVi : F3_2<2, 0b001110, "udiv">; // udiv r, r, i
388 //def SDIVr : F3_1<2, 0b001111, "sdiv">; // sdiv r, r, r
389 //def SDIVi : F3_2<2, 0b001111, "sdiv">; // sdiv r, r, i
390 //def UDIVCCr : F3_1<2, 0b011110, "udivcc">; // udivcc r, r, r
391 //def UDIVCCi : F3_2<2, 0b011110, "udivcc">; // udivcc r, r, i
392 //def SDIVCCr : F3_1<2, 0b011111, "sdivcc">; // sdivcc r, r, r
393 //def SDIVCCi : F3_2<2, 0b011111, "sdivcc">; // sdivcc r, r, i
396 // Section A.11: DONE and RETRY - p181
397 //set isPrivileged = 1 in {
398 //def DONE : F3_18<0, "done">; // done
399 //def RETRY : F3_18<1, "retry">; // retry
402 // Section A.12: Floating-Point Add and Subtract - p182
403 def FADDS : F3_16<2, 0b110100, 0x41, "fadds">; // fadds f, f, f
404 def FADDD : F3_16<2, 0b110100, 0x42, "faddd">; // faddd f, f, f
405 def FADDQ : F3_16<2, 0b110100, 0x43, "faddq">; // faddq f, f, f
406 def FSUBS : F3_16<2, 0b110100, 0x45, "fsubs">; // fsubs f, f, f
407 def FSUBD : F3_16<2, 0b110100, 0x46, "fsubd">; // fsubd f, f, f
408 def FSUBQ : F3_16<2, 0b110100, 0x47, "fsubq">; // fsubq f, f, f
410 // Section A.17: Floating-Point Move - p164
411 def FMOVS : F3_14<2, 0b110100, 0b000000001, "fmovs">; // fmovs r, r
412 def FMOVD : F3_14<2, 0b110100, 0b000000010, "fmovs">; // fmovd r, r
413 //def FMOVQ : F3_14<2, 0b110100, 0b000000011, "fmovs">; // fmovq r, r
414 def FNEGS : F3_14<2, 0b110100, 0b000000101, "fnegs">; // fnegs r, r
415 def FNEGD : F3_14<2, 0b110100, 0b000000110, "fnegs">; // fnegs r, r
416 //def FNEGQ : F3_14<2, 0b110100, 0b000000111, "fnegs">; // fnegs r, r
417 def FABSS : F3_14<2, 0b110100, 0b000001001, "fabss">; // fabss r, r
418 def FABSD : F3_14<2, 0b110100, 0b000001010, "fabss">; // fabss r, r
419 //def FABSQ : F3_14<2, 0b110100, 0b000001011, "fabss">; // fabss r, r
421 // Section A.18: Floating-Point Multiply and Divide - p165
422 def FMULS : F3_16<2, 0b110100, 0b001001001, "fmuls">; // fmuls r, r, r
423 def FMULD : F3_16<2, 0b110100, 0b001001010, "fmuld">; // fmuld r, r, r
424 def FMULQ : F3_16<2, 0b110100, 0b001001011, "fmulq">; // fmulq r, r, r
425 def FSMULD : F3_16<2, 0b110100, 0b001101001, "fsmuld">; // fsmuls r, r, r
426 def FDMULQ : F3_16<2, 0b110100, 0b001101110, "fdmulq">; // fdmuls r, r, r
427 def FDIVS : F3_16<2, 0b110100, 0b001001101, "fdivs">; // fdivs r, r, r
428 def FDIVD : F3_16<2, 0b110100, 0b001001110, "fdivs">; // fdivd r, r, r
429 def FDIVQ : F3_16<2, 0b110100, 0b001001111, "fdivs">; // fdivq r, r, r
431 // Section A.19: Floating-Point Square Root - p166
432 def FSQRTS : F3_14<2, 0b110100, 0b000101001, "fsqrts">; // fsqrts r, r
433 def FSQRTD : F3_14<2, 0b110100, 0b000101010, "fsqrts">; // fsqrts r, r
434 def FSQRTQ : F3_14<2, 0b110100, 0b000101011, "fsqrts">; // fsqrts r, r
436 // Section A.24: Jump and Link
437 // Mimicking the Sparc's instr def...
438 def JMPLCALLr : F3_1<2, 0b111000, "jmpl">; // jmpl [r+r], r
439 def JMPLCALLi : F3_1<2, 0b111000, "jmpl">; // jmpl [r+i], r
440 def JMPLRETr : F3_1<2, 0b111000, "jmpl">; // jmpl [r+r], r
441 def JMPLRETi : F3_1<2, 0b111000, "jmpl">; // jmpl [r+i], r
443 // FIXME: FCMPS, FCMPD, FCMPQ !!!
444 // FIXME: FMULS, FMULD, FMULQ, ...
446 // Section A.25: Load Floating-Point - p173
447 def LDFr : F3_1<3, 0b100000, "ld">; // ld [r+r], r
448 def LDFi : F3_2<3, 0b100000, "ld">; // ld [r+i], r
449 def LDDFr : F3_1<3, 0b100011, "ldd">; // ldd [r+r], r
450 def LDDFi : F3_2<3, 0b100011, "ldd">; // ldd [r+i], r
451 def LDQFr : F3_1<3, 0b100010, "ldq">; // ldq [r+r], r
452 def LDQFi : F3_2<3, 0b100010, "ldq">; // ldq [r+i], r
453 set isDeprecated = 1 in {
455 def LDFSRr : F3_1<3, 0b100001, "ld">; // ld [r+r], r
456 def LDFSRi : F3_2<3, 0b100001, "ld">; // ld [r+i], r
460 def LDXFSRr : F3_1<3, 0b100001, "ldx">; // ldx [r+r], r
461 def LDXFSRi : F3_2<3, 0b100001, "ldx">; // ldx [r+i], r
464 // Section A.27: Load Integer - p178
465 def LDSBr : F3_1<3, 0b001001, "ldsb">; // ldsb [r+r], r
466 def LDSBi : F3_2<3, 0b001001, "ldsb">; // ldsb [r+i], r
467 def LDSHr : F3_1<3, 0b001010, "ldsh">; // ldsh [r+r], r
468 def LDSHi : F3_2<3, 0b001010, "ldsh">; // ldsh [r+i], r
469 def LDSWr : F3_1<3, 0b001000, "ldsw">; // ldsh [r+r], r
470 def LDSWi : F3_2<3, 0b001000, "ldsw">; // ldsh [r+i], r
471 def LDUBr : F3_1<3, 0b000001, "ldub">; // ldub [r+r], r
472 def LDUBi : F3_2<3, 0b000001, "ldub">; // ldub [r+i], r
473 def LDUHr : F3_1<3, 0b000010, "lduh">; // lduh [r+r], r
474 def LDUHi : F3_2<3, 0b000010, "lduh">; // lduh [r+i], r
476 def LDUWr : F3_1<3, 0b000000, "lduw">; // lduw [r+r], r
477 def LDUWi : F3_2<3, 0b000000, "lduw">; // lduw [r+i], r
478 // LDD should no longer be used, LDX should be used instead
479 def LDXr : F3_1<3, 0b001011, "ldx">; // ldx [r+r], r
480 def LDXi : F3_2<3, 0b001011, "ldx">; // ldx [r+i], r
481 //set isDeprecated = 1 in {
482 // def LDDr : F3_1<3, 0b000011, "ldd">; // ldd [r+r], r
483 // def LDDi : F3_2<3, 0b000011, "ldd">; // ldd [r+i], r
486 // Section A.31: Logical operations
487 def ANDr : F3_1<2, 0b000001, "and">; // and r, r, r
488 def ANDi : F3_2<2, 0b000001, "and">; // and r, r, i
489 def ANDccr : F3_1<2, 0b010001, "andcc">; // andcc r, r, r
490 def ANDcci : F3_2<2, 0b010001, "andcc">; // andcc r, r, i
491 def ANDNr : F3_1<2, 0b000101, "andn">; // andn r, r, r
492 def ANDNi : F3_2<2, 0b000101, "andn">; // andn r, r, i
493 def ANDNccr : F3_1<2, 0b010101, "andncc">; // andncc r, r, r
494 def ANDNcci : F3_2<2, 0b010101, "andncc">; // andncc r, r, i
496 def ORr : F3_1<2, 0b000010, "or">; // or r, r, r
497 def ORi : F3_2<2, 0b000010, "or">; // or r, r, i
498 def ORccr : F3_1<2, 0b010010, "orcc">; // orcc r, r, r
499 def ORcci : F3_2<2, 0b010010, "orcc">; // orcc r, r, i
500 def ORNr : F3_1<2, 0b000110, "orn">; // orn r, r, r
501 def ORNi : F3_2<2, 0b000110, "orn">; // orn r, r, i
502 def ORNccr : F3_1<2, 0b010110, "orncc">; // orncc r, r, r
503 def ORNcci : F3_2<2, 0b010110, "orncc">; // orncc r, r, i
505 def XORr : F3_1<2, 0b000011, "xor">; // xor r, r, r
506 def XORi : F3_2<2, 0b000011, "xor">; // xor r, r, i
507 def XORccr : F3_1<2, 0b010011, "xorcc">; // xorcc r, r, r
508 def XORcci : F3_2<2, 0b010011, "xorcc">; // xorcc r, r, i
509 def XNORr : F3_1<2, 0b000111, "xnor">; // xnor r, r, r
510 def XNORi : F3_2<2, 0b000111, "xnor">; // xnor r, r, i
511 def XNORccr : F3_1<2, 0b010111, "xnorcc">; // xnorcc r, r, r
512 def XNORcci : F3_2<2, 0b010111, "xnorcc">; // xnorcc r, r, i
515 // Section A.33: Move Floating-Point Register on Condition (FMOVcc)
516 // For integer condition codes
517 def FMOVA : F4_7<2, 0b110101, 0b1000, "fmova">; // fmova r, r
518 def FMOVN : F4_7<2, 0b110101, 0b0000, "fmovn">; // fmovn r, r
519 def FMOVNE : F4_7<2, 0b110101, 0b1001, "fmovne">; // fmovne r, r
520 def FMOVE : F4_7<2, 0b110101, 0b0000, "fmove">; // fmove r, r
521 def FMOVG : F4_7<2, 0b110101, 0b1010, "fmovg">; // fmovg r, r
522 def FMOVLE : F4_7<2, 0b110101, 0b0000, "fmovle">; // fmovle r, r
523 def FMOVGE : F4_7<2, 0b110101, 0b1011, "fmovge">; // fmovge r, r
524 def FMOVL : F4_7<2, 0b110101, 0b0011, "fmovl">; // fmovl r, r
525 def FMOVGU : F4_7<2, 0b110101, 0b1100, "fmovgu">; // fmovgu r, r
526 def FMOVLEU : F4_7<2, 0b110101, 0b0100, "fmovleu">; // fmovleu r, r
527 def FMOVCC : F4_7<2, 0b110101, 0b1101, "fmovcc">; // fmovcc r, r
528 def FMOVCS : F4_7<2, 0b110101, 0b0101, "fmovcs">; // fmovcs r, r
529 def FMOVPOS : F4_7<2, 0b110101, 0b1110, "fmovpos">; // fmovpos r, r
530 def FMOVNEG : F4_7<2, 0b110101, 0b0110, "fmovneg">; // fmovneg r, r
531 def FMOVVC : F4_7<2, 0b110101, 0b1111, "fmovvc">; // fmovvc r, r
532 def FMOVVS : F4_7<2, 0b110101, 0b0111, "fmovvs">; // fmovvs r, r
534 // For floating-point condition codes
535 def FMOVFA : F4_7<2, 0b110101, 0b0100, "fmovfa">; // fmovfa r, r
536 def FMOVFN : F4_7<2, 0b110101, 0b0000, "fmovfn">; // fmovfa r, r
537 def FMOVFU : F4_7<2, 0b110101, 0b0111, "fmovfu">; // fmovfu r, r
538 def FMOVFG : F4_7<2, 0b110101, 0b0110, "fmovfg">; // fmovfg r, r
539 def FMOVFUG : F4_7<2, 0b110101, 0b0101, "fmovfug">; // fmovfug r, r
540 def FMOVFL : F4_7<2, 0b110101, 0b0100, "fmovfl">; // fmovfl r, r
541 def FMOVFUL : F4_7<2, 0b110101, 0b0011, "fmovful">; // fmovful r, r
542 def FMOVFLG : F4_7<2, 0b110101, 0b0010, "fmovflg">; // fmovflg r, r
543 def FMOVFNE : F4_7<2, 0b110101, 0b0001, "fmovfne">; // fmovfne r, r
544 def FMOVFE : F4_7<2, 0b110101, 0b1001, "fmovfe">; // fmovfe r, r
545 def FMOVFUE : F4_7<2, 0b110101, 0b1010, "fmovfue">; // fmovfue r, r
546 def FMOVGE : F4_7<2, 0b110101, 0b1011, "fmovge">; // fmovge r, r
547 def FMOVFUGE : F4_7<2, 0b110101, 0b1100, "fmovfuge">; // fmovfuge r, r
548 def FMOVFLE : F4_7<2, 0b110101, 0b1101, "fmovfle">; // fmovfle r, r
549 def FMOVFULE : F4_7<2, 0b110101, 0b1110, "fmovfule">; // fmovfule r, r
550 def FMOVFO : F4_7<2, 0b110101, 0b1111, "fmovfo">; // fmovfo r, r
553 // Section A.37: Multiply and Divide (64-bit) - p199
554 def MULXr : F3_1<2, 0b001001, "mulx">; // mulx r, r, r
555 def SDIVXr : F3_1<2, 0b101101, "sdivx">; // mulx r, r, r
556 def UDIVXr : F3_1<2, 0b001101, "udivx">; // mulx r, r, r
557 def MULXi : F3_2<2, 0b001001, "mulx">; // mulx r, i, r
558 def SDIVXi : F3_2<2, 0b101101, "sdivx">; // mulx r, i, r
559 def UDIVXi : F3_2<2, 0b001101, "udivx">; // mulx r, i, r
561 // Section A.38: Multiply (32-bit) - p200
562 // Not used in the Sparc backend?
563 //set Inst{13} = 0 in {
564 // def UMULr : F3_1<2, 0b001010, "umul">; // umul r, r, r
565 // def SMULr : F3_1<2, 0b001011, "smul">; // smul r, r, r
566 // def UMULCCr : F3_1<2, 0b011010, "umulcc">; // mulcc r, r, r
567 // def SMULCCr : F3_1<2, 0b011011, "smulcc">; // smulcc r, r, r
569 //set Inst{13} = 1 in {
570 // def UMULi : F3_1<2, 0b001010, "umul">; // umul r, i, r
571 // def SMULi : F3_1<2, 0b001011, "smul">; // smul r, i, r
572 // def UMULCCi : F3_1<2, 0b011010, "umulcc">; // umulcc r, i, r
573 // def SMULCCi : F3_1<2, 0b011011, "smulcc">; // smulcc r, i, r
576 // Section A.40: No operation - p204
577 // NOP is really a pseudo-instruction (special case of SETHI)
581 def NOP : F2_1<"nop">; // nop
586 // Section A.45: RETURN - p216
587 set isReturn = 1 in {
588 def RETURNr : F3_3<2, 0b111001, "return">; // return
589 def RETURNi : F3_4<2, 0b111001, "return">; // return
592 // Section A.46: SAVE and RESTORE - p217
593 def SAVEr : F3_1<2, 0b111100, "save">; // save r, r, r
594 def SAVEi : F3_2<2, 0b111100, "save">; // save r, i, r
595 def RESTOREr : F3_1<2, 0b111101, "restore">; // restore r, r, r
596 def RESTOREi : F3_2<2, 0b111101, "restore">; // restore r, i, r
598 // Section A.47: SAVED and RESTORED - p219
599 // FIXME: add these instrs
601 // Section A.48: SETHI - p220
603 def SETHI : F2_1<"sethi">; // sethi
606 // Section A.49: Shift - p221
607 // uses 5 least significant bits of rs2
609 // def SLLr5 : F3_11<2, 0b100101, "sll">; // sll r, r, r
610 // def SRLr5 : F3_11<2, 0b100110, "srl">; // srl r, r, r
611 // def SRAr5 : F3_11<2, 0b100111, "sra">; // sra r, r, r
612 // def SLLXr5 : F3_11<2, 0b100101, "sllx">; // sllx r, r, r
613 // def SRLXr5 : F3_11<2, 0b100110, "srlx">; // srlx r, r, r
614 // def SRAXr5 : F3_11<2, 0b100111, "srax">; // srax r, r, r
616 // uses 6 least significant bits of rs2
618 // def SLLr6 : F3_11<2, 0b100101, "sll">; // sll r, r, r
619 // def SRLr6 : F3_11<2, 0b100110, "srl">; // srl r, r, r
620 // def SRAr6 : F3_11<2, 0b100111, "sra">; // sra r, r, r
621 def SLLXr6 : F3_11<2, 0b100101, "sllx">; // sllx r, r, r
622 def SRLXr6 : F3_11<2, 0b100110, "srlx">; // srlx r, r, r
623 def SRAXr6 : F3_11<2, 0b100111, "srax">; // srax r, r, r
626 //def SLLi5 : F3_12<2, 0b100101, "sll">; // sll r, shcnt32, r
627 //def SRLi5 : F3_12<2, 0b100110, "srl">; // srl r, shcnt32, r
628 //def SRAi5 : F3_12<2, 0b100111, "sra">; // sra r, shcnt32, r
629 //def SLLXi5 : F3_12<2, 0b100101, "sllx">; // sllx r, shcnt32, r
630 //def SRLXi5 : F3_12<2, 0b100110, "srlx">; // srlx r, shcnt32, r
631 //def SRAXi5 : F3_12<2, 0b100111, "srax">; // srax r, shcnt32, r
633 //def SLLi6 : F3_13<2, 0b100101, "sll">; // sll r, shcnt64, r
634 //def SRLi6 : F3_13<2, 0b100110, "srl">; // srl r, shcnt64, r
635 //def SRAi6 : F3_13<2, 0b100111, "sra">; // sra r, shcnt64, r
636 def SLLXi6 : F3_13<2, 0b100101, "sllx">; // sllx r, shcnt64, r
637 def SRLXi6 : F3_13<2, 0b100110, "srlx">; // srlx r, shcnt64, r
638 def SRAXi6 : F3_13<2, 0b100111, "srax">; // srax r, shcnt64, r
640 // Section A.52: Store Floating-point -p225
641 def STFr : F3_1<3, 0b100100, "st">; // st r, [r+r]
642 def STFi : F3_2<3, 0b100100, "st">; // st r, [r+i]
643 def STDFr : F3_1<3, 0b100111, "std">; // std r, [r+r]
644 def STDFi : F3_2<3, 0b100111, "std">; // std r, [r+i]
645 // Not currently used in the Sparc backend
646 //def STQFr : F3_1<3, 0b100110, "stq">; // stq r, [r+r]
647 //def STQFi : F3_2<3, 0b100110, "stq">; // stq r, [r+i]
648 set isDeprecated = 1 in {
649 def STFSRr : F3_1<3, 0b100101, "st">; // st r, [r+r]
650 def STFSRi : F3_2<3, 0b100101, "st">; // st r, [r+i]
652 def STXFSRr : F3_1<3, 0b100101, "stq">; // stx r, [r+r]
653 def STXFSRi : F3_2<3, 0b100101, "stq">; // stx r, [r+i]
655 // Section A.54: Store Integer - p229
656 def STBr : F3_1<3, 0b000101, "stb">; // stb r, [r+r]
657 def STBi : F3_2<3, 0b000101, "stb">; // stb r, [r+i]
658 def STHr : F3_1<3, 0b000110, "stb">; // stb r, [r+r]
659 def STHi : F3_2<3, 0b000110, "stb">; // stb r, [r+i]
660 def STWr : F3_1<3, 0b000100, "stb">; // stb r, [r+r]
661 def STWi : F3_2<3, 0b000100, "stb">; // stb r, [r+i]
662 def STXr : F3_1<3, 0b001110, "stb">; // stb r, [r+r]
663 def STXi : F3_2<3, 0b001110, "stb">; // stb r, [r+i]
665 // Floating point store...
667 // Section A.56: Subtract - p233
668 def SUBr : F3_1<2, 0b000100, "sub">; // sub r, r, r
669 def SUBi : F3_1<2, 0b000100, "sub">; // sub r, i, r
670 def SUBccr : F3_1<2, 0b010100, "subcc">; // subcc r, r, r
671 def SUBcci : F3_1<2, 0b010100, "subcc">; // subcc r, i, r
672 def SUBCr : F3_1<2, 0b001100, "subc">; // subc r, r, r
673 def SUBCi : F3_1<2, 0b001100, "subc">; // subc r, i, r
674 def SUBCccr : F3_1<2, 0b011100, "subccc">; // subccc r, r, r
675 def SUBCcci : F3_1<2, 0b011100, "subccc">; // subccc r, i, r