1 //===- SparcV9.td - Target Description for SparcV9 Target -----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // TableGen target description file for the SparcV9. This is currently used
11 // primarily to generate part of the SparcV9CodeEmitter automatically.
13 //===----------------------------------------------------------------------===//
15 include "../Target.td"
17 include "SparcV9_Reg.td"
19 //===----------------------------------------------------------------------===//
21 //===----------------------------------------------------------------------===//
23 class InstV9 : Instruction { // SparcV9 instruction baseline
29 let Inst{31-30} = op; // Top two bits are the 'op' field
31 // Bit attributes specific to SparcV9 instructions
32 bit isPasi = 0; // Does this instruction affect an alternate addr space?
33 bit isDeprecated = 0; // Is this instruction deprecated?
34 bit isPrivileged = 0; // Is this a privileged instruction?
37 include "SparcV9_F2.td"
38 include "SparcV9_F3.td"
39 include "SparcV9_F4.td"
41 //===----------------------------------------------------------------------===//
42 // Instruction list...
45 // Section A.2: Add - p137
46 def ADDr : F3_1<2, 0b000000, "add">; // add rs1, rs2, rd
47 def ADDi : F3_2<2, 0b000000, "add">; // add rs1, imm, rd
48 def ADDccr : F3_1<2, 0b010000, "addcc">; // addcc rs1, rs2, rd
49 def ADDcci : F3_2<2, 0b010000, "addcc">; // addcc rs1, imm, rd
50 def ADDCr : F3_1<2, 0b001000, "addC">; // addC rs1, rs2, rd
51 def ADDCi : F3_2<2, 0b001000, "addC">; // addC rs1, imm, rd
52 def ADDCccr : F3_1<2, 0b011000, "addCcc">; // addCcc rs1, rs2, rd
53 def ADDCcci : F3_2<2, 0b011000, "addCcc">; // addCcc rs1, imm, rd
55 // Section A.3: Branch on Integer Register with Prediction - p138
57 def BRZ : F2_4<0b001, "brz">; // Branch on rs1 == 0
58 def BRLEZ : F2_4<0b010, "brlez">; // Branch on rs1 <= 0
59 def BRLZ : F2_4<0b011, "brlz">; // Branch on rs1 < 0
60 def BRNZ : F2_4<0b101, "brnz">; // Branch on rs1 != 0
61 def BRGZ : F2_4<0b110, "brgz">; // Branch on rs1 > 0
62 def BRGEZ : F2_4<0b111, "brgez">; // Branch on rs1 >= 0
65 // Section A.4: Branch on Floating-Point Condition Codes (FBfcc) p140
66 // The following deprecated instructions don't seem to play nice on SparcV9
68 let isDeprecated = 1 in {
70 def FBA : F2_2<0b1000, "fba">; // Branch always
71 def FBN : F2_2<0b0000, "fbn">; // Branch never
72 def FBU : F2_2<0b0111, "fbu">; // Branch on unordered
73 def FBG : F2_2<0b0110, "fbg">; // Branch >
74 def FBUG : F2_2<0b0101, "fbug">; // Branch on unordered or >
75 def FBL : F2_2<0b0100, "fbl">; // Branch <
76 def FBUL : F2_2<0b0011, "fbul">; // Branch on unordered or <
77 def FBLG : F2_2<0b0010, "fblg">; // Branch < or >
78 def FBNE : F2_2<0b0001, "fbne">; // Branch !=
79 def FBE : F2_2<0b1001, "fbe">; // Branch ==
80 def FBUE : F2_2<0b1010, "fbue">; // Branch on unordered or ==
81 def FBGE : F2_2<0b1011, "fbge">; // Branch > or ==
82 def FBUGE : F2_2<0b1100, "fbuge">; // Branch unord or > or ==
83 def FBLE : F2_2<0b1101, "fble">; // Branch < or ==
84 def FBULE : F2_2<0b1110, "fbule">; // Branch unord or < or ==
85 def FBO : F2_2<0b1111, "fbo">; // Branch on ordered
90 // We now make these same opcodes represent the FBPfcc instructions
92 def FBA : F2_3<0b1000, "fba">; // Branch always
93 def FBN : F2_3<0b0000, "fbn">; // Branch never
94 def FBU : F2_3<0b0111, "fbu">; // Branch on unordered
95 def FBG : F2_3<0b0110, "fbg">; // Branch >
96 def FBUG : F2_3<0b0101, "fbug">; // Branch on unordered or >
97 def FBL : F2_3<0b0100, "fbl">; // Branch <
98 def FBUL : F2_3<0b0011, "fbul">; // Branch on unordered or <
99 def FBLG : F2_3<0b0010, "fblg">; // Branch < or >
100 def FBNE : F2_3<0b0001, "fbne">; // Branch !=
101 def FBE : F2_3<0b1001, "fbe">; // Branch ==
102 def FBUE : F2_3<0b1010, "fbue">; // Branch on unordered or ==
103 def FBGE : F2_3<0b1011, "fbge">; // Branch > or ==
104 def FBUGE : F2_3<0b1100, "fbuge">; // Branch unord or > or ==
105 def FBLE : F2_3<0b1101, "fble">; // Branch < or ==
106 def FBULE : F2_3<0b1110, "fbule">; // Branch unord or < or ==
107 def FBO : F2_3<0b1111, "fbo">; // Branch on ordered
110 // Section A.5: Branch on FP condition codes with prediction - p143
111 // Not used in the SparcV9 backend (directly)
114 def FBPA : F2_3<0b1000, "fba">; // Branch always
115 def FBPN : F2_3<0b0000, "fbn">; // Branch never
116 def FBPU : F2_3<0b0111, "fbu">; // Branch on unordered
117 def FBPG : F2_3<0b0110, "fbg">; // Branch >
118 def FBPUG : F2_3<0b0101, "fbug">; // Branch on unordered or >
119 def FBPL : F2_3<0b0100, "fbl">; // Branch <
120 def FBPUL : F2_3<0b0011, "fbul">; // Branch on unordered or <
121 def FBPLG : F2_3<0b0010, "fblg">; // Branch < or >
122 def FBPNE : F2_3<0b0001, "fbne">; // Branch !=
123 def FBPE : F2_3<0b1001, "fbe">; // Branch ==
124 def FBPUE : F2_3<0b1010, "fbue">; // Branch on unordered or ==
125 def FBPGE : F2_3<0b1011, "fbge">; // Branch > or ==
126 def FBPUGE : F2_3<0b1100, "fbuge">; // Branch unord or > or ==
127 def FBPLE : F2_3<0b1101, "fble">; // Branch < or ==
128 def FBPULE : F2_3<0b1110, "fbule">; // Branch unord or < or ==
129 def FBPO : F2_3<0b1111, "fbo">; // Branch on ordered
133 // Section A.6: Branch on Integer condition codes (Bicc) - p146
135 let isDeprecated = 1 in {
137 def BA : F2_2<0b1000, "ba">; // Branch always
138 def BN : F2_2<0b0000, "bn">; // Branch never
139 def BNE : F2_2<0b1001, "bne">; // Branch !=
140 def BE : F2_2<0b0001, "be">; // Branch ==
141 def BG : F2_2<0b1010, "bg">; // Branch >
142 def BLE : F2_2<0b0010, "ble">; // Branch <=
143 def BGE : F2_2<0b1011, "bge">; // Branch >=
144 def BL : F2_2<0b0011, "bl">; // Branch <
145 def BGU : F2_2<0b1100, "bgu">; // Branch unsigned >
146 def BLEU : F2_2<0b0100, "bleu">; // Branch unsigned <=
147 def BCC : F2_2<0b1101, "bcc">; // Branch unsigned >=
148 def BCS : F2_2<0b0101, "bcs">; // Branch unsigned <=
149 def BPOS : F2_2<0b1110, "bpos">; // Branch on positive
150 def BNEG : F2_2<0b0110, "bneg">; // Branch on negative
151 def BVC : F2_2<0b1111, "bvc">; // Branch on overflow clear
152 def BVS : F2_2<0b0111, "bvs">; // Branch on overflow set
157 // Using the format of A.7 instructions...
159 let cc = 0 in { // BA and BN don't read condition codes
160 def BA : F2_3<0b1000, "ba">; // Branch always
161 def BN : F2_3<0b0000, "bn">; // Branch never
163 def BNE : F2_3<0b1001, "bne">; // Branch !=
164 def BE : F2_3<0b0001, "be">; // Branch ==
165 def BG : F2_3<0b1010, "bg">; // Branch >
166 def BLE : F2_3<0b0010, "ble">; // Branch <=
167 def BGE : F2_3<0b1011, "bge">; // Branch >=
168 def BL : F2_3<0b0011, "bl">; // Branch <
169 def BGU : F2_3<0b1100, "bgu">; // Branch unsigned >
170 def BLEU : F2_3<0b0100, "bleu">; // Branch unsigned <=
171 def BCC : F2_3<0b1101, "bcc">; // Branch unsigned >=
172 def BCS : F2_3<0b0101, "bcs">; // Branch unsigned <=
173 def BPOS : F2_3<0b1110, "bpos">; // Branch on positive
174 def BNEG : F2_3<0b0110, "bneg">; // Branch on negative
175 def BVC : F2_3<0b1111, "bvc">; // Branch on overflow clear
176 def BVS : F2_3<0b0111, "bvs">; // Branch on overflow set
179 // Section A.7: Branch on integer condition codes with prediction - p148
180 // Not used in the SparcV9 backend
183 def BPA : F2_3<0b1000, "bpa">; // Branch always
184 def BPN : F2_3<0b0000, "bpn">; // Branch never
185 def BPNE : F2_3<0b1001, "bpne">; // Branch !=
186 def BPE : F2_3<0b0001, "bpe">; // Branch ==
187 def BPG : F2_3<0b1010, "bpg">; // Branch >
188 def BPLE : F2_3<0b0010, "bple">; // Branch <=
189 def BPGE : F2_3<0b1011, "bpge">; // Branch >=
190 def BPL : F2_3<0b0011, "bpl">; // Branch <
191 def BPGU : F2_3<0b1100, "bpgu">; // Branch unsigned >
192 def BPLEU : F2_3<0b0100, "bpleu">; // Branch unsigned <=
193 def BPCC : F2_3<0b1101, "bpcc">; // Branch unsigned >=
194 def BPCS : F2_3<0b0101, "bpcs">; // Branch unsigned <=
195 def BPPOS : F2_3<0b1110, "bppos">; // Branch on positive
196 def BPNEG : F2_3<0b0110, "bpneg">; // Branch on negative
197 def BPVC : F2_3<0b1111, "bpvc">; // Branch on overflow clear
198 def BPVS : F2_3<0b0111, "bpvs">; // Branch on overflow set
202 // Section A.8: CALL - p151, the only Format #1 instruction
206 let Inst{29-0} = disp;
211 // Section A.9: Compare and Swap - p176
212 // CASA/CASXA: are for alternate address spaces! Ignore them
215 // Section A.10: Divide (64-bit / 32-bit) - p178
216 // Not used in the SparcV9 backend
218 let isDeprecated = 1 in {
219 def UDIVr : F3_1<2, 0b001110, "udiv">; // udiv r, r, r
220 def UDIVi : F3_2<2, 0b001110, "udiv">; // udiv r, r, i
221 def SDIVr : F3_1<2, 0b001111, "sdiv">; // sdiv r, r, r
222 def SDIVi : F3_2<2, 0b001111, "sdiv">; // sdiv r, r, i
223 def UDIVCCr : F3_1<2, 0b011110, "udivcc">; // udivcc r, r, r
224 def UDIVCCi : F3_2<2, 0b011110, "udivcc">; // udivcc r, r, i
225 def SDIVCCr : F3_1<2, 0b011111, "sdivcc">; // sdivcc r, r, r
226 def SDIVCCi : F3_2<2, 0b011111, "sdivcc">; // sdivcc r, r, i
230 // Section A.11: DONE and RETRY - p181
231 // Not used in the SparcV9 backend
233 let isPrivileged = 1 in {
234 def DONE : F3_18<0, "done">; // done
235 def RETRY : F3_18<1, "retry">; // retry
239 // Section A.12: Floating-Point Add and Subtract - p156
240 def FADDS : F3_16<2, 0b110100, 0x41, "fadds">; // fadds frs1, frs2, frd
241 def FADDD : F3_16<2, 0b110100, 0x42, "faddd">; // faddd frs1, frs2, frd
242 def FADDQ : F3_16<2, 0b110100, 0x43, "faddq">; // faddq frs1, frs2, frd
243 def FSUBS : F3_16<2, 0b110100, 0x45, "fsubs">; // fsubs frs1, frs2, frd
244 def FSUBD : F3_16<2, 0b110100, 0x46, "fsubd">; // fsubd frs1, frs2, frd
245 def FSUBQ : F3_16<2, 0b110100, 0x47, "fsubq">; // fsubq frs1, frs2, frd
247 // Section A.13: Floating-point compare - p159
248 def FCMPS : F3_15<2, 0b110101, 0b001010001, "fcmps">; // fcmps %fcc, r1, r2
249 def FCMPD : F3_15<2, 0b110101, 0b001010010, "fcmpd">; // fcmpd %fcc, r1, r2
250 def FCMPQ : F3_15<2, 0b110101, 0b001010011, "fcmpq">; // fcmpq %fcc, r1, r2
251 // Currently unused in the SparcV9 backend
253 def FCMPES : F3_15<2, 0b110101, 0b001010101, "fcmpes">; // fcmpes %fcc, r1, r2
254 def FCMPED : F3_15<2, 0b110101, 0b001010110, "fcmped">; // fcmped %fcc, r1, r2
255 def FCMPEQ : F3_15<2, 0b110101, 0b001010111, "fcmpeq">; // fcmpeq %fcc, r1, r2
258 // Section A.14: Convert floating-point to integer - p161
259 def FSTOX : F3_14<2, 0b110100, 0b010000001, "fstox">; // fstox rs2, rd
260 def FDTOX : F3_14<2, 0b110100, 0b010000010, "fstox">; // fstox rs2, rd
261 def FQTOX : F3_14<2, 0b110100, 0b010000011, "fstox">; // fstox rs2, rd
262 def FSTOI : F3_14<2, 0b110100, 0b011010001, "fstoi">; // fstoi rs2, rd
263 def FDTOI : F3_14<2, 0b110100, 0b011010010, "fdtoi">; // fdtoi rs2, rd
264 def FQTOI : F3_14<2, 0b110100, 0b011010011, "fqtoi">; // fqtoi rs2, rd
266 // Section A.15: Convert between floating-point formats - p162
267 def FSTOD : F3_14<2, 0b110100, 0b011001001, "fstod">; // fstod rs2, rd
268 def FSTOQ : F3_14<2, 0b110100, 0b011001101, "fstoq">; // fstoq rs2, rd
269 def FDTOS : F3_14<2, 0b110100, 0b011000110, "fstos">; // fstos rs2, rd
270 def FDTOQ : F3_14<2, 0b110100, 0b011001110, "fdtoq">; // fdtoq rs2, rd
271 def FQTOS : F3_14<2, 0b110100, 0b011000111, "fqtos">; // fqtos rs2, rd
272 def FQTOD : F3_14<2, 0b110100, 0b011001011, "fqtod">; // fqtod rs2, rd
274 // Section A.16: Convert integer to floating-point - p163
275 def FXTOS : F3_14<2, 0b110100, 0b010000100, "fxtos">; // fxtos rs2, rd
276 def FXTOD : F3_14<2, 0b110100, 0b010001000, "fxtod">; // fxtod rs2, rd
277 def FXTOQ : F3_14<2, 0b110100, 0b010001100, "fxtoq">; // fxtoq rs2, rd
278 def FITOS : F3_14<2, 0b110100, 0b011000100, "fitos">; // fitos rs2, rd
279 def FITOD : F3_14<2, 0b110100, 0b011001000, "fitod">; // fitod rs2, rd
280 def FITOQ : F3_14<2, 0b110100, 0b011001100, "fitoq">; // fitoq rs2, rd
282 // Section A.17: Floating-Point Move - p164
283 def FMOVS : F3_14<2, 0b110100, 0b000000001, "fmovs">; // fmovs r, r
284 def FMOVD : F3_14<2, 0b110100, 0b000000010, "fmovs">; // fmovd r, r
285 //def FMOVQ : F3_14<2, 0b110100, 0b000000011, "fmovs">; // fmovq r, r
286 def FNEGS : F3_14<2, 0b110100, 0b000000101, "fnegs">; // fnegs r, r
287 def FNEGD : F3_14<2, 0b110100, 0b000000110, "fnegs">; // fnegs r, r
288 //def FNEGQ : F3_14<2, 0b110100, 0b000000111, "fnegs">; // fnegs r, r
289 def FABSS : F3_14<2, 0b110100, 0b000001001, "fabss">; // fabss r, r
290 def FABSD : F3_14<2, 0b110100, 0b000001010, "fabss">; // fabss r, r
291 //def FABSQ : F3_14<2, 0b110100, 0b000001011, "fabss">; // fabss r, r
293 // Section A.18: Floating-Point Multiply and Divide - p165
294 def FMULS : F3_16<2, 0b110100, 0b001001001, "fmuls">; // fmuls r, r, r
295 def FMULD : F3_16<2, 0b110100, 0b001001010, "fmuld">; // fmuld r, r, r
296 def FMULQ : F3_16<2, 0b110100, 0b001001011, "fmulq">; // fmulq r, r, r
297 def FSMULD : F3_16<2, 0b110100, 0b001101001, "fsmuld">; // fsmuls r, r, r
298 def FDMULQ : F3_16<2, 0b110100, 0b001101110, "fdmulq">; // fdmuls r, r, r
299 def FDIVS : F3_16<2, 0b110100, 0b001001101, "fdivs">; // fdivs r, r, r
300 def FDIVD : F3_16<2, 0b110100, 0b001001110, "fdivs">; // fdivd r, r, r
301 def FDIVQ : F3_16<2, 0b110100, 0b001001111, "fdivs">; // fdivq r, r, r
303 // Section A.19: Floating-Point Square Root - p166
304 def FSQRTS : F3_14<2, 0b110100, 0b000101001, "fsqrts">; // fsqrts r, r
305 def FSQRTD : F3_14<2, 0b110100, 0b000101010, "fsqrts">; // fsqrts r, r
306 def FSQRTQ : F3_14<2, 0b110100, 0b000101011, "fsqrts">; // fsqrts r, r
308 // A.20: Flush Instruction Memory - p167
309 // Not currently used
311 // A.21: Flush Register Windows - p169
312 // Not currently used
314 // A.22: Illegal instruction Trap - p170
315 // Not currently used
317 // A.23: Implementation-Dependent Instructions - p171
318 // Not currently used
320 // Section A.24: Jump and Link - p172
321 // Mimicking the SparcV9's instr def...
322 def JMPLCALLr : F3_1<2, 0b111000, "jmpl">; // jmpl [rs1+rs2], rd
323 def JMPLCALLi : F3_2<2, 0b111000, "jmpl">; // jmpl [rs1+imm], rd
324 def JMPLRETr : F3_1<2, 0b111000, "jmpl">; // jmpl [rs1+rs2], rd
325 def JMPLRETi : F3_2<2, 0b111000, "jmpl">; // jmpl [rs1+imm], rd
327 // Section A.25: Load Floating-Point - p173
328 def LDFr : F3_1<3, 0b100000, "ld">; // ld [rs1+rs2], rd
329 def LDFi : F3_2<3, 0b100000, "ld">; // ld [rs1+imm], rd
330 def LDDFr : F3_1<3, 0b100011, "ldd">; // ldd [rs1+rs2], rd
331 def LDDFi : F3_2<3, 0b100011, "ldd">; // ldd [rs1+imm], rd
332 def LDQFr : F3_1<3, 0b100010, "ldq">; // ldq [rs1+rs2], rd
333 def LDQFi : F3_2<3, 0b100010, "ldq">; // ldq [rs1+imm], rd
334 let isDeprecated = 1 in {
336 def LDFSRr : F3_1<3, 0b100001, "ld">; // ld [rs1+rs2], rd
337 def LDFSRi : F3_2<3, 0b100001, "ld">; // ld [rs1+imm], rd
341 def LDXFSRr : F3_1<3, 0b100001, "ldx">; // ldx [rs1+rs2], rd
342 def LDXFSRi : F3_2<3, 0b100001, "ldx">; // ldx [rs1+imm], rd
345 // Section A.27: Load Integer - p178
346 def LDSBr : F3_1<3, 0b001001, "ldsb">; // ldsb [rs1+rs2], rd
347 def LDSBi : F3_2<3, 0b001001, "ldsb">; // ldsb [rs1+imm], rd
348 def LDSHr : F3_1<3, 0b001010, "ldsh">; // ldsh [rs1+rs2], rd
349 def LDSHi : F3_2<3, 0b001010, "ldsh">; // ldsh [rs1+imm], rd
350 def LDSWr : F3_1<3, 0b001000, "ldsw">; // ldsh [rs1+rs2], rd
351 def LDSWi : F3_2<3, 0b001000, "ldsw">; // ldsh [rs1+imm], rd
352 def LDUBr : F3_1<3, 0b000001, "ldub">; // ldub [rs1+rs2], rd
353 def LDUBi : F3_2<3, 0b000001, "ldub">; // ldub [rs1+imm], rd
354 def LDUHr : F3_1<3, 0b000010, "lduh">; // lduh [rs1+rs2], rd
355 def LDUHi : F3_2<3, 0b000010, "lduh">; // lduh [rs1+imm], rd
357 def LDUWr : F3_1<3, 0b000000, "lduw">; // lduw [rs1+rs2], rd
358 def LDUWi : F3_2<3, 0b000000, "lduw">; // lduw [rs1+imm], rd
359 def LDXr : F3_1<3, 0b001011, "ldx">; // ldx [rs1+rs2], rd
360 def LDXi : F3_2<3, 0b001011, "ldx">; // ldx [rs1+imm], rd
362 let isDeprecated = 1 in {
363 def LDDr : F3_1<3, 0b000011, "ldd">; // ldd [rs1+rs2], rd
364 def LDDi : F3_2<3, 0b000011, "ldd">; // ldd [rs1+imm], rd
368 // Section A.31: Logical operations
369 def ANDr : F3_1<2, 0b000001, "and">; // and rs1, rs2, rd
370 def ANDi : F3_2<2, 0b000001, "and">; // and rs1, imm, rd
371 def ANDccr : F3_1<2, 0b010001, "andcc">; // andcc rs1, rs2, rd
372 def ANDcci : F3_2<2, 0b010001, "andcc">; // andcc rs1, imm, rd
373 def ANDNr : F3_1<2, 0b000101, "andn">; // andn rs1, rs2, rd
374 def ANDNi : F3_2<2, 0b000101, "andn">; // andn rs1, imm, rd
375 def ANDNccr : F3_1<2, 0b010101, "andncc">; // andncc rs1, rs2, rd
376 def ANDNcci : F3_2<2, 0b010101, "andncc">; // andncc rs1, imm, rd
378 def ORr : F3_1<2, 0b000010, "or">; // or rs1, rs2, rd
379 def ORi : F3_2<2, 0b000010, "or">; // or rs1, imm, rd
380 def ORccr : F3_1<2, 0b010010, "orcc">; // orcc rs1, rs2, rd
381 def ORcci : F3_2<2, 0b010010, "orcc">; // orcc rs1, imm, rd
382 def ORNr : F3_1<2, 0b000110, "orn">; // orn rs1, rs2, rd
383 def ORNi : F3_2<2, 0b000110, "orn">; // orn rs1, imm, rd
384 def ORNccr : F3_1<2, 0b010110, "orncc">; // orncc rs1, rs2, rd
385 def ORNcci : F3_2<2, 0b010110, "orncc">; // orncc rs1, imm, rd
387 def XORr : F3_1<2, 0b000011, "xor">; // xor rs1, rs2, rd
388 def XORi : F3_2<2, 0b000011, "xor">; // xor rs1, imm, rd
389 def XORccr : F3_1<2, 0b010011, "xorcc">; // xorcc rs1, rs2, rd
390 def XORcci : F3_2<2, 0b010011, "xorcc">; // xorcc rs1, imm, rd
391 def XNORr : F3_1<2, 0b000111, "xnor">; // xnor rs1, rs2, rd
392 def XNORi : F3_2<2, 0b000111, "xnor">; // xnor rs1, imm, rd
393 def XNORccr : F3_1<2, 0b010111, "xnorcc">; // xnorcc rs1, rs2, rd
394 def XNORcci : F3_2<2, 0b010111, "xnorcc">; // xnorcc rs1, imm, rd
396 // Section A.32: Memory Barrier - p186
397 // Not currently used in the SparcV9 backend
399 // Section A.33: Move Floating-Point Register on Condition (FMOVcc)
400 // ======================= Single Floating Point ======================
401 // For integer condition codes
402 def FMOVSA : F4_7<2, 0b110101, 0b1000, 0b000001, "fmovsa">; // fmovsa cc, r, r
403 def FMOVSN : F4_7<2, 0b110101, 0b0000, 0b000001, "fmovsn">; // fmovsn cc, r, r
404 def FMOVSNE : F4_7<2, 0b110101, 0b1001, 0b000001, "fmovsne">; // fmovsne cc, r, r
405 def FMOVSE : F4_7<2, 0b110101, 0b0000, 0b000001, "fmovse">; // fmovse cc, r, r
406 def FMOVSG : F4_7<2, 0b110101, 0b1010, 0b000001, "fmovsg">; // fmovsg cc, r, r
407 def FMOVSLE : F4_7<2, 0b110101, 0b0000, 0b000001, "fmovsle">; // fmovsle cc, r, r
408 def FMOVSGE : F4_7<2, 0b110101, 0b1011, 0b000001, "fmovsge">; // fmovsge cc, r, r
409 def FMOVSL : F4_7<2, 0b110101, 0b0011, 0b000001, "fmovsl">; // fmovsl cc, r, r
410 def FMOVSGU : F4_7<2, 0b110101, 0b1100, 0b000001, "fmovsgu">; // fmovsgu cc, r, r
411 def FMOVSLEU : F4_7<2, 0b110101, 0b0100, 0b000001, "fmovsleu">; // fmovsleu cc, r, r
412 def FMOVSCC : F4_7<2, 0b110101, 0b1101, 0b000001, "fmovscc">; // fmovscc cc, r, r
413 def FMOVSCS : F4_7<2, 0b110101, 0b0101, 0b000001, "fmovscs">; // fmovscs cc, r, r
414 def FMOVSPOS : F4_7<2, 0b110101, 0b1110, 0b000001, "fmovspos">; // fmovspos cc, r, r
415 def FMOVSNEG : F4_7<2, 0b110101, 0b0110, 0b000001, "fmovsneg">; // fmovsneg cc, r, r
416 def FMOVSVC : F4_7<2, 0b110101, 0b1111, 0b000001, "fmovsvc">; // fmovsvc cc, r, r
417 def FMOVSVS : F4_7<2, 0b110101, 0b0111, 0b000001, "fmovsvs">; // fmovsvs cc, r, r
419 // For floating-point condition codes
420 def FMOVSFA : F4_7<2, 0b110101, 0b0100, 0b000001, "fmovsfa">; // fmovsfa cc,r,r
421 def FMOVSFN : F4_7<2, 0b110101, 0b0000, 0b000001, "fmovsfn">; // fmovsfa cc,r,r
422 def FMOVSFU : F4_7<2, 0b110101, 0b0111, 0b000001, "fmovsfu">; // fmovsfu cc,r,r
423 def FMOVSFG : F4_7<2, 0b110101, 0b0110, 0b000001, "fmovsfg">; // fmovsfg cc,r,r
424 def FMOVSFUG : F4_7<2, 0b110101, 0b0101, 0b000001, "fmovsfug">; // fmovsfug cc,r,r
425 def FMOVSFL : F4_7<2, 0b110101, 0b0100, 0b000001, "fmovsfl">; // fmovsfl cc,r,r
426 def FMOVSFUL : F4_7<2, 0b110101, 0b0011, 0b000001, "fmovsful">; // fmovsful cc,r,r
427 def FMOVSFLG : F4_7<2, 0b110101, 0b0010, 0b000001, "fmovsflg">; // fmovsflg cc,r,r
428 def FMOVSFNE : F4_7<2, 0b110101, 0b0001, 0b000001, "fmovsfne">; // fmovsfne cc,r,r
429 def FMOVSFE : F4_7<2, 0b110101, 0b1001, 0b000001, "fmovsfe">; // fmovsfe cc,r,r
430 def FMOVSFUE : F4_7<2, 0b110101, 0b1010, 0b000001, "fmovsfue">; // fmovsfue cc,r,r
431 def FMOVSFGE : F4_7<2, 0b110101, 0b1011, 0b000001, "fmovsge">; // fmovsge cc,r,r
432 def FMOVSFUGE : F4_7<2, 0b110101, 0b1100, 0b000001, "fmovsfuge">;// fmovsfuge cc,r,r
433 def FMOVSFLE : F4_7<2, 0b110101, 0b1101, 0b000001, "fmovsfle">; // fmovsfle cc,r,r
434 def FMOVSFULE : F4_7<2, 0b110101, 0b1110, 0b000001, "fmovsfule">;// fmovsfule cc,r,r
435 def FMOVSFO : F4_7<2, 0b110101, 0b1111, 0b000001, "fmovsfo">; // fmovsfo cc,r,r
437 // ======================= Double Floating Point ======================
438 // For integer condition codes
439 def FMOVDA : F4_7<2, 0b110101, 0b1000, 0b000010, "fmovda">; // fmovda cc, r, r
440 def FMOVDN : F4_7<2, 0b110101, 0b0000, 0b000010, "fmovdn">; // fmovdn cc, r, r
441 def FMOVDNE : F4_7<2, 0b110101, 0b1001, 0b000010, "fmovdne">; // fmovdne cc, r, r
442 def FMOVDE : F4_7<2, 0b110101, 0b0000, 0b000010, "fmovde">; // fmovde cc, r, r
443 def FMOVDG : F4_7<2, 0b110101, 0b1010, 0b000010, "fmovdg">; // fmovdg cc, r, r
444 def FMOVDLE : F4_7<2, 0b110101, 0b0000, 0b000010, "fmovdle">; // fmovdle cc, r, r
445 def FMOVDGE : F4_7<2, 0b110101, 0b1011, 0b000010, "fmovdge">; // fmovdge cc, r, r
446 def FMOVDL : F4_7<2, 0b110101, 0b0011, 0b000010, "fmovdl">; // fmovdl cc, r, r
447 def FMOVDGU : F4_7<2, 0b110101, 0b1100, 0b000010, "fmovdgu">; // fmovdgu cc, r, r
448 def FMOVDLEU : F4_7<2, 0b110101, 0b0100, 0b000010, "fmovdleu">; // fmovdleu cc, r, r
449 def FMOVDCC : F4_7<2, 0b110101, 0b1101, 0b000010, "fmovdcc">; // fmovdcc cc, r, r
450 def FMOVDCS : F4_7<2, 0b110101, 0b0101, 0b000010, "fmovdcs">; // fmovdcs cc, r, r
451 def FMOVDPOS : F4_7<2, 0b110101, 0b1110, 0b000010, "fmovdpos">; // fmovdpos cc, r, r
452 def FMOVDNEG : F4_7<2, 0b110101, 0b0110, 0b000010, "fmovdneg">; // fmovdneg cc, r, r
453 def FMOVDVC : F4_7<2, 0b110101, 0b1111, 0b000010, "fmovdvc">; // fmovdvc cc, r, r
454 def FMOVDVS : F4_7<2, 0b110101, 0b0111, 0b000010, "fmovdvs">; // fmovdvs cc, r, r
456 // For floating-point condition codes
457 def FMOVDFA : F4_7<2, 0b110101, 0b0100, 0b000010, "fmovdfa">; // fmovdfa cc,r,r
458 def FMOVDFN : F4_7<2, 0b110101, 0b0000, 0b000010, "fmovdfn">; // fmovdfa cc,r,r
459 def FMOVDFU : F4_7<2, 0b110101, 0b0111, 0b000010, "fmovdfu">; // fmovdfu cc,r,r
460 def FMOVDFG : F4_7<2, 0b110101, 0b0110, 0b000010, "fmovdfg">; // fmovdfg cc,r,r
461 def FMOVDFUG : F4_7<2, 0b110101, 0b0101, 0b000010, "fmovdfug">; // fmovdfug cc,r,r
462 def FMOVDFL : F4_7<2, 0b110101, 0b0100, 0b000010, "fmovdfl">; // fmovdfl cc,r,r
463 def FMOVDFUL : F4_7<2, 0b110101, 0b0011, 0b000010, "fmovdful">; // fmovdful cc,r,r
464 def FMOVDFLG : F4_7<2, 0b110101, 0b0010, 0b000010, "fmovdflg">; // fmovdflg cc,r,r
465 def FMOVDFNE : F4_7<2, 0b110101, 0b0001, 0b000010, "fmovdfne">; // fmovdfne cc,r,r
466 def FMOVDFE : F4_7<2, 0b110101, 0b1001, 0b000010, "fmovdfe">; // fmovdfe cc,r,r
467 def FMOVDFUE : F4_7<2, 0b110101, 0b1010, 0b000010, "fmovdfue">; // fmovdfue cc,r,r
468 def FMOVDFGE : F4_7<2, 0b110101, 0b1011, 0b000010, "fmovdge">; // fmovdge cc,r,r
469 def FMOVDFUGE : F4_7<2, 0b110101, 0b1100, 0b000010, "fmovdfuge">;// fmovdfuge cc,r,r
470 def FMOVDFLE : F4_7<2, 0b110101, 0b1101, 0b000010, "fmovdfle">; // fmovdfle cc,r,r
471 def FMOVDFULE : F4_7<2, 0b110101, 0b1110, 0b000010, "fmovdfule">;// fmovdfule cc,r,r
472 def FMOVDFO : F4_7<2, 0b110101, 0b1111, 0b000010, "fmovdfo">; // fmovdfo cc,r,r
474 // ======================= Quad Floating Point ======================
475 // For integer condition codes
476 def FMOVQA : F4_7<2, 0b110101, 0b1000, 0b000011, "fmovqa">; // fmovqa cc, r, r
477 def FMOVQN : F4_7<2, 0b110101, 0b0000, 0b000011, "fmovqn">; // fmovqn cc, r, r
478 def FMOVQNE : F4_7<2, 0b110101, 0b1001, 0b000011, "fmovqne">; // fmovqne cc, r, r
479 def FMOVQE : F4_7<2, 0b110101, 0b0000, 0b000011, "fmovqe">; // fmovqe cc, r, r
480 def FMOVQG : F4_7<2, 0b110101, 0b1010, 0b000011, "fmovqg">; // fmovqg cc, r, r
481 def FMOVQLE : F4_7<2, 0b110101, 0b0000, 0b000011, "fmovqle">; // fmovqle cc, r, r
482 def FMOVQGE : F4_7<2, 0b110101, 0b1011, 0b000011, "fmovqge">; // fmovqge cc, r, r
483 def FMOVQL : F4_7<2, 0b110101, 0b0011, 0b000011, "fmovql">; // fmovql cc, r, r
484 def FMOVQGU : F4_7<2, 0b110101, 0b1100, 0b000011, "fmovqgu">; // fmovqgu cc, r, r
485 def FMOVQLEU : F4_7<2, 0b110101, 0b0100, 0b000011, "fmovqleu">; // fmovqleu cc, r, r
486 def FMOVQCC : F4_7<2, 0b110101, 0b1101, 0b000011, "fmovqcc">; // fmovqcc cc, r, r
487 def FMOVQCS : F4_7<2, 0b110101, 0b0101, 0b000011, "fmovqcs">; // fmovqcs cc, r, r
488 def FMOVQPOS : F4_7<2, 0b110101, 0b1110, 0b000011, "fmovqpos">; // fmovqpos cc, r, r
489 def FMOVQNEG : F4_7<2, 0b110101, 0b0110, 0b000011, "fmovqneg">; // fmovqneg cc, r, r
490 def FMOVQVC : F4_7<2, 0b110101, 0b1111, 0b000011, "fmovqvc">; // fmovqvc cc, r, r
491 def FMOVQVS : F4_7<2, 0b110101, 0b0111, 0b000011, "fmovqvs">; // fmovqvs cc, r, r
493 // For floating-point condition codes
494 def FMOVQFA : F4_7<2, 0b110101, 0b0100, 0b000011, "fmovqfa">; // fmovqfa cc,r,r
495 def FMOVQFN : F4_7<2, 0b110101, 0b0000, 0b000011, "fmovqfn">; // fmovqfa cc,r,r
496 def FMOVQFU : F4_7<2, 0b110101, 0b0111, 0b000011, "fmovqfu">; // fmovqfu cc,r,r
497 def FMOVQFG : F4_7<2, 0b110101, 0b0110, 0b000011, "fmovqfg">; // fmovqfg cc,r,r
498 def FMOVQFUG : F4_7<2, 0b110101, 0b0101, 0b000011, "fmovqfug">; // fmovqfug cc,r,r
499 def FMOVQFL : F4_7<2, 0b110101, 0b0100, 0b000011, "fmovqfl">; // fmovqfl cc,r,r
500 def FMOVQFUL : F4_7<2, 0b110101, 0b0011, 0b000011, "fmovqful">; // fmovqful cc,r,r
501 def FMOVQFLG : F4_7<2, 0b110101, 0b0010, 0b000011, "fmovqflg">; // fmovqflg cc,r,r
502 def FMOVQFNE : F4_7<2, 0b110101, 0b0001, 0b000011, "fmovqfne">; // fmovqfne cc,r,r
503 def FMOVQFE : F4_7<2, 0b110101, 0b1001, 0b000011, "fmovqfe">; // fmovqfe cc,r,r
504 def FMOVQFUE : F4_7<2, 0b110101, 0b1010, 0b000011, "fmovqfue">; // fmovqfue cc,r,r
505 def FMOVQFGE : F4_7<2, 0b110101, 0b1011, 0b000011, "fmovqge">; // fmovqge cc,r,r
506 def FMOVQFUGE : F4_7<2, 0b110101, 0b1100, 0b000011, "fmovqfuge">;// fmovqfuge cc,r,r
507 def FMOVQFLE : F4_7<2, 0b110101, 0b1101, 0b000011, "fmovqfle">; // fmovqfle cc,r,r
508 def FMOVQFULE : F4_7<2, 0b110101, 0b1110, 0b000011, "fmovqfule">;// fmovqfule cc,r,r
509 def FMOVQFO : F4_7<2, 0b110101, 0b1111, 0b000011, "fmovqfo">; // fmovqfo cc,r,r
511 // Section A.34: Move FP Register on Integer Register condition (FMOVr) - p192
512 def FMOVRSZ : F4_6<2, 0b110101, 0b001, 0b00101, "fmovrsz">; //fmovsrz r,r,rd
513 def FMOVRSLEZ : F4_6<2, 0b110101, 0b010, 0b00101, "fmovrslez">;//fmovsrz r,r,rd
514 def FMOVRSLZ : F4_6<2, 0b110101, 0b011, 0b00101, "fmovrslz">; //fmovsrz r,r,rd
515 def FMOVRSNZ : F4_6<2, 0b110101, 0b101, 0b00101, "fmovrsne">; //fmovsrz r,r,rd
516 def FMOVRSGZ : F4_6<2, 0b110101, 0b110, 0b00101, "fmovrsgz">; //fmovsrz r,r,rd
517 def FMOVRSGEZ : F4_6<2, 0b110101, 0b111, 0b00101, "fmovrsgez">;//fmovsrz r,r,rd
519 def FMOVRDZ : F4_6<2, 0b110101, 0b001, 0b00110, "fmovrdz">; //fmovsrz r,r,rd
520 def FMOVRDLEZ : F4_6<2, 0b110101, 0b010, 0b00110, "fmovrdlez">;//fmovsrz r,r,rd
521 def FMOVRDLZ : F4_6<2, 0b110101, 0b011, 0b00110, "fmovrdlz">; //fmovsrz r,r,rd
522 def FMOVRDNZ : F4_6<2, 0b110101, 0b101, 0b00110, "fmovrdne">; //fmovsrz r,r,rd
523 def FMOVRDGZ : F4_6<2, 0b110101, 0b110, 0b00110, "fmovrdgz">; //fmovsrz r,r,rd
524 def FMOVRDGEZ : F4_6<2, 0b110101, 0b111, 0b00110, "fmovrdgez">;//fmovsrz r,r,rd
526 def FMOVRQZ : F4_6<2, 0b110101, 0b001, 0b00111, "fmovrqz">; //fmovsrz r,r,rd
527 def FMOVRQLEZ : F4_6<2, 0b110101, 0b010, 0b00111, "fmovrqlez">;//fmovsrz r,r,rd
528 def FMOVRQLZ : F4_6<2, 0b110101, 0b011, 0b00111, "fmovrqlz">; //fmovsrz r,r,rd
529 def FMOVRQNZ : F4_6<2, 0b110101, 0b101, 0b00111, "fmovrqne">; //fmovsrz r,r,rd
530 def FMOVRQGZ : F4_6<2, 0b110101, 0b110, 0b00111, "fmovrqgz">; //fmovsrz r,r,rd
531 def FMOVRQGEZ : F4_6<2, 0b110101, 0b111, 0b00111, "fmovrqgez">;//fmovsrz r,r,rd
534 // Section A.35: Move Integer Register on Condition (MOVcc) - p194
535 // For integer condition codes
536 def MOVAr : F4_3<2, 0b101100, 0b1000, "mova">; // mova i/xcc, rs2, rd
537 def MOVAi : F4_4<2, 0b101100, 0b1000, "mova">; // mova i/xcc, imm, rd
538 def MOVNr : F4_3<2, 0b101100, 0b0000, "movn">; // movn i/xcc, rs2, rd
539 def MOVNi : F4_4<2, 0b101100, 0b0000, "movn">; // movn i/xcc, imm, rd
540 def MOVNEr : F4_3<2, 0b101100, 0b1001, "movne">; // movne i/xcc, rs2, rd
541 def MOVNEi : F4_4<2, 0b101100, 0b1001, "movne">; // movne i/xcc, imm, rd
542 def MOVEr : F4_3<2, 0b101100, 0b0001, "move">; // move i/xcc, rs2, rd
543 def MOVEi : F4_4<2, 0b101100, 0b0001, "move">; // move i/xcc, imm, rd
544 def MOVGr : F4_3<2, 0b101100, 0b1010, "movg">; // movg i/xcc, rs2, rd
545 def MOVGi : F4_4<2, 0b101100, 0b1010, "movg">; // movg i/xcc, imm, rd
546 def MOVLEr : F4_3<2, 0b101100, 0b0010, "movle">; // movle i/xcc, rs2, rd
547 def MOVLEi : F4_4<2, 0b101100, 0b0010, "movle">; // movle i/xcc, imm, rd
548 def MOVGEr : F4_3<2, 0b101100, 0b1011, "movge">; // movge i/xcc, rs2, rd
549 def MOVGEi : F4_4<2, 0b101100, 0b1011, "movge">; // movge i/xcc, imm, rd
550 def MOVLr : F4_3<2, 0b101100, 0b0011, "movl">; // movl i/xcc, rs2, rd
551 def MOVLi : F4_4<2, 0b101100, 0b0011, "movl">; // movl i/xcc, imm, rd
552 def MOVGUr : F4_3<2, 0b101100, 0b1100, "movgu">; // movgu i/xcc, rs2, rd
553 def MOVGUi : F4_4<2, 0b101100, 0b1100, "movgu">; // movgu i/xcc, imm, rd
554 def MOVLEUr : F4_3<2, 0b101100, 0b0100, "movleu">; // movleu i/xcc, rs2, rd
555 def MOVLEUi : F4_4<2, 0b101100, 0b0100, "movleu">; // movleu i/xcc, imm, rd
556 def MOVCCr : F4_3<2, 0b101100, 0b1101, "movcc">; // movcc i/xcc, rs2, rd
557 def MOVCCi : F4_4<2, 0b101100, 0b1101, "movcc">; // movcc i/xcc, imm, rd
558 def MOVCSr : F4_3<2, 0b101100, 0b0101, "movcs">; // movcs i/xcc, rs2, rd
559 def MOVCSi : F4_4<2, 0b101100, 0b0101, "movcs">; // movcs i/xcc, imm, rd
560 def MOVPOSr : F4_3<2, 0b101100, 0b1110, "movpos">; // movpos i/xcc, rs2, rd
561 def MOVPOSi : F4_4<2, 0b101100, 0b1110, "movpos">; // movpos i/xcc, imm, rd
562 def MOVNEGr : F4_3<2, 0b101100, 0b0110, "movneg">; // movneg i/xcc, rs2, rd
563 def MOVNEGi : F4_4<2, 0b101100, 0b0110, "movneg">; // movneg i/xcc, imm, rd
564 def MOVVCr : F4_3<2, 0b101100, 0b1111, "movvc">; // movvc i/xcc, rs2, rd
565 def MOVVCi : F4_4<2, 0b101100, 0b1111, "movvc">; // movvc i/xcc, imm, rd
566 def MOVVSr : F4_3<2, 0b101100, 0b0111, "movvs">; // movvs i/xcc, rs2, rd
567 def MOVVSi : F4_4<2, 0b101100, 0b0111, "movvs">; // movvs i/xcc, imm, rd
569 // For floating-point condition codes
570 def MOVFAr : F4_3<2, 0b101100, 0b1000, "movfa">; // movfa i/xcc, rs2, rd
571 def MOVFAi : F4_4<2, 0b101100, 0b1000, "movfa">; // movfa i/xcc, imm, rd
572 def MOVFNr : F4_3<2, 0b101100, 0b0000, "movfn">; // movfn i/xcc, rs2, rd
573 def MOVFNi : F4_4<2, 0b101100, 0b0000, "movfn">; // movfn i/xcc, imm, rd
574 def MOVFUr : F4_3<2, 0b101100, 0b0111, "movfu">; // movfu i/xcc, rs2, rd
575 def MOVFUi : F4_4<2, 0b101100, 0b0111, "movfu">; // movfu i/xcc, imm, rd
576 def MOVFGr : F4_3<2, 0b101100, 0b0110, "movfg">; // movfg i/xcc, rs2, rd
577 def MOVFGi : F4_4<2, 0b101100, 0b0110, "movfg">; // movfg i/xcc, imm, rd
578 def MOVFUGr : F4_3<2, 0b101100, 0b0101, "movfug">; // movfug i/xcc, rs2, rd
579 def MOVFUGi : F4_4<2, 0b101100, 0b0101, "movfug">; // movfug i/xcc, imm, rd
580 def MOVFLr : F4_3<2, 0b101100, 0b0100, "movfl">; // movfl i/xcc, rs2, rd
581 def MOVFLi : F4_4<2, 0b101100, 0b0100, "movfl">; // movfl i/xcc, imm, rd
582 def MOVFULr : F4_3<2, 0b101100, 0b0011, "movful">; // movful i/xcc, rs2, rd
583 def MOVFULi : F4_4<2, 0b101100, 0b0011, "movful">; // movful i/xcc, imm, rd
584 def MOVFLGr : F4_3<2, 0b101100, 0b0010, "movflg">; // movflg i/xcc, rs2, rd
585 def MOVFLGi : F4_4<2, 0b101100, 0b0010, "movflg">; // movflg i/xcc, imm, rd
586 def MOVFNEr : F4_3<2, 0b101100, 0b0001, "movfne">; // movfne i/xcc, rs2, rd
587 def MOVFNEi : F4_4<2, 0b101100, 0b0001, "movfne">; // movfne i/xcc, imm, rd
588 def MOVFEr : F4_3<2, 0b101100, 0b1001, "movfe">; // movfe i/xcc, rs2, rd
589 def MOVFEi : F4_4<2, 0b101100, 0b1001, "movfe">; // movfe i/xcc, imm, rd
590 def MOVFUEr : F4_3<2, 0b101100, 0b1010, "movfue">; // movfue i/xcc, rs2, rd
591 def MOVFUEi : F4_4<2, 0b101100, 0b1010, "movfue">; // movfue i/xcc, imm, rd
592 def MOVFGEr : F4_3<2, 0b101100, 0b1011, "movfge">; // movfge i/xcc, rs2, rd
593 def MOVFGEi : F4_4<2, 0b101100, 0b1011, "movfge">; // movfge i/xcc, imm, rd
594 def MOVFUGEr : F4_3<2, 0b101100, 0b1100, "movfuge">; // movfuge i/xcc, rs2, rd
595 def MOVFUGEi : F4_4<2, 0b101100, 0b1100, "movfuge">; // movfuge i/xcc, imm, rd
596 def MOVFLEr : F4_3<2, 0b101100, 0b1101, "movfle">; // movfle i/xcc, rs2, rd
597 def MOVFLEi : F4_4<2, 0b101100, 0b1101, "movfle">; // movfle i/xcc, imm, rd
598 def MOVFULEr : F4_3<2, 0b101100, 0b1110, "movfule">; // movfule i/xcc, rs2, rd
599 def MOVFULEi : F4_4<2, 0b101100, 0b1110, "movfule">; // movfule i/xcc, imm, rd
600 def MOVFOr : F4_3<2, 0b101100, 0b1111, "movfo">; // movfo i/xcc, rs2, rd
601 def MOVFOi : F4_4<2, 0b101100, 0b1111, "movfo">; // movfo i/xcc, imm, rd
603 // Section A.36: Move Integer Register on Register Condition (MOVR) - p198
604 def MOVRZr : F3_5<2, 0b101111, 0b001, "movrz">; // movrz rs1, rs2, rd
605 def MOVRZi : F3_6<2, 0b101111, 0b001, "movrz">; // movrz rs1, imm, rd
606 def MOVRLEZr : F3_5<2, 0b101111, 0b010, "movrlez">; // movrlez rs1, rs2, rd
607 def MOVRLEZi : F3_6<2, 0b101111, 0b010, "movrlez">; // movrlez rs1, imm, rd
608 def MOVRLZr : F3_5<2, 0b101111, 0b011, "movrlz">; // movrlz rs1, rs2, rd
609 def MOVRLZi : F3_6<2, 0b101111, 0b011, "movrlz">; // movrlz rs1, imm, rd
610 def MOVRNZr : F3_5<2, 0b101111, 0b101, "movrnz">; // movrnz rs1, rs2, rd
611 def MOVRNZi : F3_6<2, 0b101111, 0b101, "movrnz">; // movrnz rs1, imm, rd
612 def MOVRGZr : F3_5<2, 0b101111, 0b110, "movrgz">; // movrgz rs1, rs2, rd
613 def MOVRGZi : F3_6<2, 0b101111, 0b110, "movrgz">; // movrgz rs1, imm, rd
614 def MOVRGEZr : F3_5<2, 0b101111, 0b111, "movrgez">; // movrgez rs1, rs2, rd
615 def MOVRGEZi : F3_6<2, 0b101111, 0b111, "movrgez">; // movrgez rs1, imm, rd
617 // Section A.37: Multiply and Divide (64-bit) - p199
618 def MULXr : F3_1<2, 0b001001, "mulx">; // mulx r, r, r
619 def MULXi : F3_2<2, 0b001001, "mulx">; // mulx r, i, r
620 def SDIVXr : F3_1<2, 0b101101, "sdivx">; // sdivx r, r, r
621 def SDIVXi : F3_2<2, 0b101101, "sdivx">; // sdivx r, i, r
622 def UDIVXr : F3_1<2, 0b001101, "udivx">; // udivx r, r, r
623 def UDIVXi : F3_2<2, 0b001101, "udivx">; // udivx r, i, r
625 // Section A.38: Multiply (32-bit) - p200
626 // Not used in the SparcV9 backend
628 let Inst{13} = 0 in {
629 def UMULr : F3_1<2, 0b001010, "umul">; // umul r, r, r
630 def SMULr : F3_1<2, 0b001011, "smul">; // smul r, r, r
631 def UMULCCr : F3_1<2, 0b011010, "umulcc">; // mulcc r, r, r
632 def SMULCCr : F3_1<2, 0b011011, "smulcc">; // smulcc r, r, r
634 let Inst{13} = 1 in {
635 def UMULi : F3_1<2, 0b001010, "umul">; // umul r, i, r
636 def SMULi : F3_1<2, 0b001011, "smul">; // smul r, i, r
637 def UMULCCi : F3_1<2, 0b011010, "umulcc">; // umulcc r, i, r
638 def SMULCCi : F3_1<2, 0b011011, "smulcc">; // smulcc r, i, r
642 // Section A.39: Multiply Step - p202
643 // Not currently used in the SparcV9 backend
645 // Section A.40: No operation - p204
646 // NOP is really a pseudo-instruction (special case of SETHI)
650 def NOP : F2_1<"nop">; // nop
655 // Section A.41: Population Count - p205
656 // Not currently used in the SparcV9 backend
658 // Section A.42: Prefetch Data - p206
659 // Not currently used in the SparcV9 backend
661 // Section A.43: Read Privileged Register - p211
662 // Not currently used in the SparcV9 backend
664 // Section A.44: Read State Register
665 // The only instr from this section currently used is RDCCR
667 def RDCCR : F3_17<2, 0b101000, "rd">; // rd %ccr, r
670 // Section A.46: SAVE and RESTORE - p217
671 def SAVEr : F3_1<2, 0b111100, "save">; // save r, r, r
672 def SAVEi : F3_2<2, 0b111100, "save">; // save r, i, r
673 def RESTOREr : F3_1<2, 0b111101, "restore">; // restore r, r, r
674 def RESTOREi : F3_2<2, 0b111101, "restore">; // restore r, i, r
676 // Section A.47: SAVED and RESTORED - p219
677 // Not currently used in SparcV9 backend
679 // Section A.48: SETHI - p220
681 def SETHI : F2_1<"sethi">; // sethi
684 // Section A.49: Shift - p221
685 // Not currently used in the SparcV9 backend
687 uses 5 least significant bits of rs2
689 def SLLr5 : F3_11<2, 0b100101, "sll">; // sll r, r, r
690 def SRLr5 : F3_11<2, 0b100110, "srl">; // srl r, r, r
691 def SRAr5 : F3_11<2, 0b100111, "sra">; // sra r, r, r
692 def SLLXr5 : F3_11<2, 0b100101, "sllx">; // sllx r, r, r
693 def SRLXr5 : F3_11<2, 0b100110, "srlx">; // srlx r, r, r
694 def SRAXr5 : F3_11<2, 0b100111, "srax">; // srax r, r, r
698 // uses 6 least significant bits of rs2
700 def SLLr5 : F3_11<2, 0b100101, "sll">; // sll r, r, r
701 def SRLr5 : F3_11<2, 0b100110, "srl">; // srl r, r, r
702 def SRAr5 : F3_11<2, 0b100111, "sra">; // sra r, r, r
705 def SLLXr6 : F3_11<2, 0b100101, "sllx">; // sllx r, r, r
706 def SRLXr6 : F3_11<2, 0b100110, "srlx">; // srlx r, r, r
707 def SRAXr6 : F3_11<2, 0b100111, "srax">; // srax r, r, r
710 def SLLi5 : F3_12<2, 0b100101, "sll">; // sll r, shcnt32, r
711 def SRLi5 : F3_12<2, 0b100110, "srl">; // srl r, shcnt32, r
712 def SRAi5 : F3_12<2, 0b100111, "sra">; // sra r, shcnt32, r
713 def SLLXi6 : F3_13<2, 0b100101, "sllx">; // sllx r, shcnt64, r
714 def SRLXi6 : F3_13<2, 0b100110, "srlx">; // srlx r, shcnt64, r
715 def SRAXi6 : F3_13<2, 0b100111, "srax">; // srax r, shcnt64, r
717 // Section A.50: Sofware-Initiated Reset - p223
718 // Not currently used in the SparcV9 backend
720 // Section A.51: Store Barrier - p224
721 // Not currently used in the SparcV9 backend
723 // Section A.52: Store Floating-point - p225
724 // Store instructions all want their rd register first
725 def STFr : F3_1rd<3, 0b100100, "st">; // st r, [r+r]
726 def STFi : F3_2rd<3, 0b100100, "st">; // st r, [r+i]
727 def STDFr : F3_1rd<3, 0b100111, "std">; // std r, [r+r]
728 def STDFi : F3_2rd<3, 0b100111, "std">; // std r, [r+i]
730 // Not currently used in the SparcV9 backend
732 def STQFr : F3_1rd<3, 0b100110, "stq">; // stq r, [r+r]
733 def STQFi : F3_2rd<3, 0b100110, "stq">; // stq r, [r+i]
736 // WARNING: We encode %fsr as 1, because we only use STXFSRx, but STFSRx wants
737 // you to encode %fsr as 0. If STFSRx instrs are ever enabled, this will
738 // need to be worked around.
740 let isDeprecated = 1 in {
741 def STFSRr : F3_1rd<3, 0b100101, "st">; // st %fsr, [r+r]
742 def STFSRi : F3_2rd<3, 0b100101, "st">; // st %fsr, [r+i]
745 def STXFSRr : F3_1rd<3, 0b100101, "stx">; // stx %fsr, [r+r]
746 def STXFSRi : F3_2rd<3, 0b100101, "stx">; // stx %fsr, [r+i]
748 // Section A.53: Store Floating-Point into Alternate Space - p227
749 // Not currently used in the SparcV9 backend
751 // Section A.54: Store Integer - p229
752 // Store instructions all want their rd register first
753 def STBr : F3_1rd<3, 0b000101, "stb">; // stb r, [r+r]
754 def STBi : F3_2rd<3, 0b000101, "stb">; // stb r, [r+i]
755 def STHr : F3_1rd<3, 0b000110, "sth">; // sth r, [r+r]
756 def STHi : F3_2rd<3, 0b000110, "sth">; // sth r, [r+i]
757 def STWr : F3_1rd<3, 0b000100, "stw">; // stw r, [r+r]
758 def STWi : F3_2rd<3, 0b000100, "stw">; // stw r, [r+i]
759 def STXr : F3_1rd<3, 0b001110, "stx">; // stx r, [r+r]
760 def STXi : F3_2rd<3, 0b001110, "stx">; // stx r, [r+i]
762 // Section A.55: Store Integer into Alternate Space - p231
763 // Not currently used in the SparcV9 backend
765 // Section A.56: Subtract - p233
766 def SUBr : F3_1<2, 0b000100, "sub">; // sub r, r, r
767 def SUBi : F3_2<2, 0b000100, "sub">; // sub r, i, r
768 def SUBccr : F3_1<2, 0b010100, "subcc">; // subcc r, r, r
769 def SUBcci : F3_2<2, 0b010100, "subcc">; // subcc r, i, r
770 def SUBCr : F3_1<2, 0b001100, "subc">; // subc r, r, r
771 def SUBCi : F3_2<2, 0b001100, "subc">; // subc r, i, r
772 def SUBCccr : F3_1<2, 0b011100, "subccc">; // subccc r, r, r
773 def SUBCcci : F3_2<2, 0b011100, "subccc">; // subccc r, i, r
777 // Section A.63: Write State Register - p244
779 def WRCCRr : F3_1<2, 0b110000, "wr">; // wr r, r, %y/ccr/etc
780 def WRCCRi : F3_2<2, 0b110000, "wr">; // wr r, i, %y/ccr/etc