1 //===-- SparcV9CodeEmitter.cpp --------------------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // SPARC-specific backend for emitting machine code to memory.
12 // This module also contains the code for lazily resolving the targets of call
13 // instructions, including the callback used to redirect calls to functions for
14 // which the code has not yet been generated into the JIT compiler.
16 // This file #includes SparcV9GenCodeEmitter.inc, which contains the code for
17 // getBinaryCodeForInstr(), a method that converts a MachineInstr into the
18 // corresponding binary machine code word.
20 //===----------------------------------------------------------------------===//
22 #include "llvm/Constants.h"
23 #include "llvm/Function.h"
24 #include "llvm/GlobalVariable.h"
25 #include "llvm/PassManager.h"
26 #include "llvm/CodeGen/MachineCodeEmitter.h"
27 #include "llvm/CodeGen/MachineConstantPool.h"
28 #include "llvm/CodeGen/MachineFunctionPass.h"
29 #include "llvm/CodeGen/MachineInstr.h"
30 #include "llvm/Target/TargetMachine.h"
31 #include "llvm/Target/TargetData.h"
32 #include "llvm/Support/Debug.h"
33 #include "SparcV9Internals.h"
34 #include "SparcV9TargetMachine.h"
35 #include "SparcV9RegInfo.h"
36 #include "SparcV9CodeEmitter.h"
37 #include "SparcV9Relocations.h"
38 #include "MachineFunctionInfo.h"
41 bool SparcV9TargetMachine::addPassesToEmitMachineCode(FunctionPassManager &PM,
42 MachineCodeEmitter &MCE) {
43 PM.add(new SparcV9CodeEmitter(*this, MCE));
44 PM.add(createSparcV9MachineCodeDestructionPass());
48 SparcV9CodeEmitter::SparcV9CodeEmitter(TargetMachine &tm,
49 MachineCodeEmitter &M): TM(tm), MCE(M) {}
51 void SparcV9CodeEmitter::emitWord(unsigned Val) {
56 SparcV9CodeEmitter::getRealRegNum(unsigned fakeReg,
58 const SparcV9RegInfo &RI = *TM.getRegInfo();
59 unsigned regClass, regType = RI.getRegType(fakeReg);
60 // At least map fakeReg into its class
61 fakeReg = RI.getClassRegNum(fakeReg, regClass);
64 case SparcV9RegInfo::IntRegClassID: {
65 // SparcV9 manual, p31
66 static const unsigned IntRegMap[] = {
67 // "o0", "o1", "o2", "o3", "o4", "o5", "o7",
68 8, 9, 10, 11, 12, 13, 15,
69 // "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
70 16, 17, 18, 19, 20, 21, 22, 23,
71 // "i0", "i1", "i2", "i3", "i4", "i5", "i6", "i7",
72 24, 25, 26, 27, 28, 29, 30, 31,
73 // "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
74 0, 1, 2, 3, 4, 5, 6, 7,
79 return IntRegMap[fakeReg];
82 case SparcV9RegInfo::FloatRegClassID: {
83 DEBUG(std::cerr << "FP reg: " << fakeReg << "\n");
84 if (regType == SparcV9RegInfo::FPSingleRegType) {
85 // only numbered 0-31, hence can already fit into 5 bits (and 6)
86 DEBUG(std::cerr << "FP single reg, returning: " << fakeReg << "\n");
87 } else if (regType == SparcV9RegInfo::FPDoubleRegType) {
88 // FIXME: This assumes that we only have 5-bit register fields!
89 // From SparcV9 Manual, page 40.
90 // The bit layout becomes: b[4], b[3], b[2], b[1], b[5]
91 fakeReg |= (fakeReg >> 5) & 1;
93 DEBUG(std::cerr << "FP double reg, returning: " << fakeReg << "\n");
97 case SparcV9RegInfo::IntCCRegClassID: {
99 static const unsigned IntCCReg[] = { 6, 4, 2 };
101 assert(fakeReg < sizeof(IntCCReg)/sizeof(IntCCReg[0])
102 && "CC register out of bounds for IntCCReg map");
103 DEBUG(std::cerr << "IntCC reg: " << IntCCReg[fakeReg] << "\n");
104 return IntCCReg[fakeReg];
106 case SparcV9RegInfo::FloatCCRegClassID: {
107 /* These are laid out %fcc0 - %fcc3 => 0 - 3, so are correct */
108 DEBUG(std::cerr << "FP CC reg: " << fakeReg << "\n");
111 case SparcV9RegInfo::SpecialRegClassID: {
112 // Currently only "special" reg is %fsr, which is encoded as 1 in
113 // instructions and 0 in SparcV9SpecialRegClass.
114 static const unsigned SpecialReg[] = { 1 };
115 assert(fakeReg < sizeof(SpecialReg)/sizeof(SpecialReg[0])
116 && "Special register out of bounds for SpecialReg map");
117 DEBUG(std::cerr << "Special reg: " << SpecialReg[fakeReg] << "\n");
118 return SpecialReg[fakeReg];
121 assert(0 && "Invalid unified register number in getRealRegNum");
128 int64_t SparcV9CodeEmitter::getMachineOpValue(MachineInstr &MI,
129 MachineOperand &MO) {
130 int64_t rv = 0; // Return value; defaults to 0 for unhandled cases
131 // or things that get fixed up later by the JIT.
132 if (MO.isPCRelativeDisp() || MO.isGlobalAddress()) {
133 DEBUG(std::cerr << "PCRelativeDisp: ");
134 Value *V = MO.getVRegValue();
135 if (BasicBlock *BB = dyn_cast<BasicBlock>(V)) {
136 DEBUG(std::cerr << "Saving reference to BB (VReg)\n");
137 unsigned* CurrPC = (unsigned*)(intptr_t)MCE.getCurrentPCValue();
138 BBRefs.push_back(std::make_pair(BB, std::make_pair(CurrPC, &MI)));
139 } else if (const ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
140 // The real target of the branch is CI = PC + (rv * 4)
141 // So undo that: give the instruction (CI - PC) / 4
142 rv = (CI->getRawValue() - MCE.getCurrentPCValue()) / 4;
143 } else if (GlobalValue *GV = dyn_cast<GlobalValue>(V)) {
145 if (MI.getOpcode() == V9::CALL) {
146 Reloc = V9::reloc_pcrel_call;
147 } else if (MI.getOpcode() == V9::SETHI) {
149 Reloc = V9::reloc_sethi_hh;
150 else if (MO.isHiBits32())
151 Reloc = V9::reloc_sethi_lm;
153 assert(0 && "Unknown relocation!");
154 } else if (MI.getOpcode() == V9::ORi) {
156 Reloc = V9::reloc_or_lo;
157 else if (MO.isLoBits64())
158 Reloc = V9::reloc_or_hm;
160 assert(0 && "Unknown relocation!");
162 assert(0 && "Unknown relocation!");
165 MCE.addRelocation(MachineRelocation(MCE.getCurrentPCOffset(), Reloc, GV));
168 std::cerr << "ERROR: PC relative disp unhandled:" << MO << "\n";
171 } else if (MO.isRegister() || MO.getType() == MachineOperand::MO_CCRegister)
173 // This is necessary because the SparcV9 backend doesn't actually lay out
174 // registers in the real fashion -- it skips those that it chooses not to
175 // allocate, i.e. those that are the FP, SP, etc.
176 unsigned fakeReg = MO.getReg();
177 unsigned realRegByClass = getRealRegNum(fakeReg, MI);
178 DEBUG(std::cerr << MO << ": Reg[" << std::dec << fakeReg << "] => "
179 << realRegByClass << " (LLC: "
180 << TM.getRegInfo()->getUnifiedRegName(fakeReg) << ")\n");
182 } else if (MO.isImmediate()) {
183 rv = MO.getImmedValue();
184 DEBUG(std::cerr << "immed: " << rv << "\n");
185 } else if (MO.isMachineBasicBlock()) {
186 // Duplicate code of the above case for VirtualRegister, BasicBlock...
187 // It should really hit this case, but SparcV9 backend uses VRegs instead
188 DEBUG(std::cerr << "Saving reference to MBB\n");
189 const BasicBlock *BB = MO.getMachineBasicBlock()->getBasicBlock();
190 unsigned* CurrPC = (unsigned*)(intptr_t)MCE.getCurrentPCValue();
191 BBRefs.push_back(std::make_pair(BB, std::make_pair(CurrPC, &MI)));
192 } else if (MO.isExternalSymbol()) {
193 // SparcV9 backend doesn't generate this (yet...)
194 std::cerr << "ERROR: External symbol unhandled: " << MO << "\n";
196 } else if (MO.isFrameIndex()) {
197 // SparcV9 backend doesn't generate this (yet...)
198 int FrameIndex = MO.getFrameIndex();
199 std::cerr << "ERROR: Frame index unhandled.\n";
201 } else if (MO.isConstantPoolIndex()) {
202 unsigned Index = MO.getConstantPoolIndex();
203 rv = MCE.getConstantPoolEntryAddress(Index);
205 std::cerr << "ERROR: Unknown type of MachineOperand: " << MO << "\n";
209 // Finally, deal with the various bitfield-extracting functions that
210 // are used in SPARC assembly. (Some of these make no sense in combination
211 // with some of the above; we'll trust that the instruction selector
212 // will not produce nonsense, and not check for valid combinations here.)
213 if (MO.isLoBits32()) { // %lo(val) == %lo() in SparcV9 ABI doc
215 } else if (MO.isHiBits32()) { // %lm(val) == %hi() in SparcV9 ABI doc
216 return (rv >> 10) & 0x03fffff;
217 } else if (MO.isLoBits64()) { // %hm(val) == %ulo() in SparcV9 ABI doc
218 return (rv >> 32) & 0x03ff;
219 } else if (MO.isHiBits64()) { // %hh(val) == %uhi() in SparcV9 ABI doc
221 } else { // (unadorned) val
226 unsigned SparcV9CodeEmitter::getValueBit(int64_t Val, unsigned bit) {
231 bool SparcV9CodeEmitter::runOnMachineFunction(MachineFunction &MF) {
232 MCE.startFunction(MF);
233 DEBUG(std::cerr << "Starting function " << MF.getFunction()->getName()
234 << ", address: " << "0x" << std::hex
235 << (long)MCE.getCurrentPCValue() << "\n");
237 MCE.emitConstantPool(MF.getConstantPool());
238 for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I)
240 MCE.finishFunction(MF);
242 DEBUG(std::cerr << "Finishing fn " << MF.getFunction()->getName() << "\n");
244 // Resolve branches to BasicBlocks for the entire function
245 for (unsigned i = 0, e = BBRefs.size(); i != e; ++i) {
246 long Location = BBLocations[BBRefs[i].first];
247 unsigned *Ref = BBRefs[i].second.first;
248 MachineInstr *MI = BBRefs[i].second.second;
249 DEBUG(std::cerr << "Fixup @ " << std::hex << Ref << " to 0x" << Location
250 << " in instr: " << std::dec << *MI);
251 for (unsigned ii = 0, ee = MI->getNumOperands(); ii != ee; ++ii) {
252 MachineOperand &op = MI->getOperand(ii);
253 if (op.isPCRelativeDisp()) {
254 // the instruction's branch target is made such that it branches to
255 // PC + (branchTarget * 4), so undo that arithmetic here:
256 // Location is the target of the branch
257 // Ref is the location of the instruction, and hence the PC
258 int64_t branchTarget = (Location - (long)Ref) >> 2;
260 bool loBits32=false, hiBits32=false, loBits64=false, hiBits64=false;
261 if (op.isLoBits32()) { loBits32=true; }
262 if (op.isHiBits32()) { hiBits32=true; }
263 if (op.isLoBits64()) { loBits64=true; }
264 if (op.isHiBits64()) { hiBits64=true; }
265 MI->SetMachineOperandConst(ii, MachineOperand::MO_SignExtendedImmed,
267 if (loBits32) { MI->getOperand(ii).markLo32(); }
268 else if (hiBits32) { MI->getOperand(ii).markHi32(); }
269 else if (loBits64) { MI->getOperand(ii).markLo64(); }
270 else if (hiBits64) { MI->getOperand(ii).markHi64(); }
271 DEBUG(std::cerr << "Rewrote BB ref: ");
272 unsigned fixedInstr = SparcV9CodeEmitter::getBinaryCodeForInstr(*MI);
273 MCE.emitWordAt (fixedInstr, Ref);
284 void SparcV9CodeEmitter::emitBasicBlock(MachineBasicBlock &MBB) {
285 currBB = MBB.getBasicBlock();
286 BBLocations[currBB] = MCE.getCurrentPCValue();
287 for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); I != E; ++I)
288 if (I->getOpcode() != V9::RDCCR) {
289 emitWord(getBinaryCodeForInstr(*I));
291 // FIXME: The tblgen produced code emitter cannot deal with the fact that
292 // machine operand #0 of the RDCCR instruction should be ignored. This is
293 // really a bug in the representation of the RDCCR instruction (which has
294 // no need to explicitly represent the CCR dest), but we hack around it
296 unsigned RegNo = getMachineOpValue(*I, I->getOperand(1));
298 emitWord((RegNo << 25) | 2168487936U);
302 #include "SparcV9GenCodeEmitter.inc"