1 //===-- SparcV9CodeEmitter.cpp --------------------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // SPARC-specific backend for emitting machine code to memory.
12 // This module also contains the code for lazily resolving the targets
13 // of call instructions, including the callback used to redirect calls
14 // to functions for which the code has not yet been generated into the
17 // This file #includes SparcV9CodeEmitter.inc, which contains the code
18 // for getBinaryCodeForInstr(), a method that converts a MachineInstr
19 // into the corresponding binary machine code word.
21 //===----------------------------------------------------------------------===//
23 #include "llvm/Constants.h"
24 #include "llvm/Function.h"
25 #include "llvm/GlobalVariable.h"
26 #include "llvm/PassManager.h"
27 #include "llvm/CodeGen/MachineCodeEmitter.h"
28 #include "llvm/CodeGen/MachineConstantPool.h"
29 #include "llvm/CodeGen/MachineFunctionInfo.h"
30 #include "llvm/CodeGen/MachineFunctionPass.h"
31 #include "llvm/CodeGen/MachineInstr.h"
32 #include "llvm/Target/TargetMachine.h"
33 #include "llvm/Target/TargetData.h"
34 #include "Support/Debug.h"
35 #include "Support/hash_set"
36 #include "Support/Statistic.h"
37 #include "SparcInternals.h"
38 #include "SparcV9CodeEmitter.h"
39 #include "Config/alloca.h"
42 Statistic<> OverwrittenCalls("call-ovwr", "Number of over-written calls");
43 Statistic<> UnmodifiedCalls("call-skip", "Number of unmodified calls");
44 Statistic<> CallbackCalls("callback", "Number CompilationCallback() calls");
47 bool UltraSparc::addPassesToEmitMachineCode(FunctionPassManager &PM,
48 MachineCodeEmitter &MCE) {
49 MachineCodeEmitter *M = &MCE;
50 DEBUG(M = MachineCodeEmitter::createFilePrinterEmitter(MCE));
51 PM.add(new SparcV9CodeEmitter(*this, *M));
52 PM.add(createMachineCodeDestructionPass()); // Free stuff no longer needed
58 SparcV9CodeEmitter &SparcV9;
59 MachineCodeEmitter &MCE;
61 /// LazyCodeGenMap - Keep track of call sites for functions that are to be
64 std::map<uint64_t, Function*> LazyCodeGenMap;
66 /// LazyResolverMap - Keep track of the lazy resolver created for a
67 /// particular function so that we can reuse them if necessary.
69 std::map<Function*, uint64_t> LazyResolverMap;
72 enum CallType { ShortCall, FarCall };
75 /// We need to keep track of whether we used a simple call or a far call
76 /// (many instructions) in sequence. This means we need to keep track of
77 /// what type of stub we generate.
78 static std::map<uint64_t, CallType> LazyCallFlavor;
81 JITResolver(SparcV9CodeEmitter &V9,
82 MachineCodeEmitter &mce) : SparcV9(V9), MCE(mce) {}
83 uint64_t getLazyResolver(Function *F);
84 uint64_t addFunctionReference(uint64_t Address, Function *F);
85 void deleteFunctionReference(uint64_t Address);
86 void addCallFlavor(uint64_t Address, CallType Flavor) {
87 LazyCallFlavor[Address] = Flavor;
90 // Utility functions for accessing data from static callback
91 uint64_t getCurrentPCValue() {
92 return MCE.getCurrentPCValue();
94 unsigned getBinaryCodeForInstr(MachineInstr &MI) {
95 return SparcV9.getBinaryCodeForInstr(MI);
98 inline void insertFarJumpAtAddr(int64_t Value, uint64_t Addr);
99 void insertJumpAtAddr(int64_t Value, uint64_t &Addr);
102 uint64_t emitStubForFunction(Function *F);
103 static void SaveRegisters(uint64_t DoubleFP[], uint64_t &FSR,
104 uint64_t &FPRS, uint64_t &CCR);
105 static void RestoreRegisters(uint64_t DoubleFP[], uint64_t &FSR,
106 uint64_t &FPRS, uint64_t &CCR);
107 static void CompilationCallback();
108 uint64_t resolveFunctionReference(uint64_t RetAddr);
112 JITResolver *TheJITResolver;
113 std::map<uint64_t, JITResolver::CallType> JITResolver::LazyCallFlavor;
116 /// addFunctionReference - This method is called when we need to emit the
117 /// address of a function that has not yet been emitted, so we don't know the
118 /// address. Instead, we emit a call to the CompilationCallback method, and
119 /// keep track of where we are.
121 uint64_t JITResolver::addFunctionReference(uint64_t Address, Function *F) {
122 LazyCodeGenMap[Address] = F;
123 return (intptr_t)&JITResolver::CompilationCallback;
126 /// deleteFunctionReference - If we are emitting a far call, we already added a
127 /// reference to the function, but it is now incorrect, since the address to the
128 /// JIT resolver is too far away to be a simple call instruction. This is used
129 /// to remove the address from the map.
131 void JITResolver::deleteFunctionReference(uint64_t Address) {
132 std::map<uint64_t, Function*>::iterator I = LazyCodeGenMap.find(Address);
133 assert(I != LazyCodeGenMap.end() && "Not in map!");
134 LazyCodeGenMap.erase(I);
137 uint64_t JITResolver::resolveFunctionReference(uint64_t RetAddr) {
138 std::map<uint64_t, Function*>::iterator I = LazyCodeGenMap.find(RetAddr);
139 assert(I != LazyCodeGenMap.end() && "Not in map!");
140 Function *F = I->second;
141 LazyCodeGenMap.erase(I);
142 return MCE.forceCompilationOf(F);
145 uint64_t JITResolver::getLazyResolver(Function *F) {
146 std::map<Function*, uint64_t>::iterator I = LazyResolverMap.lower_bound(F);
147 if (I != LazyResolverMap.end() && I->first == F) return I->second;
149 uint64_t Stub = emitStubForFunction(F);
150 LazyResolverMap.insert(I, std::make_pair(F, Stub));
154 void JITResolver::insertJumpAtAddr(int64_t JumpTarget, uint64_t &Addr) {
155 DEBUG(std::cerr << "Emitting a jump to 0x" << std::hex << JumpTarget << "\n");
157 // If the target function is close enough to fit into the 19bit disp of
158 // BA, we should use this version, as it's much cheaper to generate.
159 int64_t BranchTarget = (JumpTarget-Addr) >> 2;
160 if (BranchTarget >= (1 << 19) || BranchTarget <= -(1 << 19)) {
161 TheJITResolver->insertFarJumpAtAddr(JumpTarget, Addr);
164 MachineInstr *I = BuildMI(V9::BA, 1).addSImm(BranchTarget);
165 *((unsigned*)(intptr_t)Addr) = getBinaryCodeForInstr(*I);
170 I = BuildMI(V9::NOP, 0);
171 *((unsigned*)(intptr_t)Addr) = getBinaryCodeForInstr(*I);
176 void JITResolver::insertFarJumpAtAddr(int64_t Target, uint64_t Addr) {
177 static const unsigned
178 o6 = SparcIntRegClass::o6, g0 = SparcIntRegClass::g0,
179 g1 = SparcIntRegClass::g1, g5 = SparcIntRegClass::g5;
181 MachineInstr* BinaryCode[] = {
183 // Get address to branch into %g1, using %g5 as a temporary
185 // sethi %uhi(Target), %g5 ;; get upper 22 bits of Target into %g5
186 BuildMI(V9::SETHI, 2).addSImm(Target >> 42).addReg(g5),
187 // or %g5, %ulo(Target), %g5 ;; get 10 lower bits of upper word into %g5
188 BuildMI(V9::ORi, 3).addReg(g5).addSImm((Target >> 32) & 0x03ff).addReg(g5),
189 // sllx %g5, 32, %g5 ;; shift those 10 bits to the upper word
190 BuildMI(V9::SLLXi6, 3).addReg(g5).addSImm(32).addReg(g5),
191 // sethi %hi(Target), %g1 ;; extract bits 10-31 into the dest reg
192 BuildMI(V9::SETHI, 2).addSImm((Target >> 10) & 0x03fffff).addReg(g1),
193 // or %g5, %g1, %g1 ;; get upper word (in %g5) into %g1
194 BuildMI(V9::ORr, 3).addReg(g5).addReg(g1).addReg(g1),
195 // or %g1, %lo(Target), %g1 ;; get lowest 10 bits of Target into %g1
196 BuildMI(V9::ORi, 3).addReg(g1).addSImm(Target & 0x03ff).addReg(g1),
197 // jmpl %g1, %g0, %g0 ;; indirect branch on %g1
198 BuildMI(V9::JMPLRETr, 3).addReg(g1).addReg(g0).addReg(g0),
203 for (unsigned i=0, e=sizeof(BinaryCode)/sizeof(BinaryCode[0]); i!=e; ++i) {
204 *((unsigned*)(intptr_t)Addr) = getBinaryCodeForInstr(*BinaryCode[i]);
205 delete BinaryCode[i];
210 void JITResolver::SaveRegisters(uint64_t DoubleFP[], uint64_t &FSR,
211 uint64_t &FPRS, uint64_t &CCR) {
212 #if defined(sparc) || defined(__sparc__) || defined(__sparcv9)
215 __asm__ __volatile__ (// Save condition-code registers
219 : "=m"(FSR), "=r"(FPRS), "=r"(CCR));
222 // GCC says: `asm' only allows up to thirty parameters!
223 __asm__ __volatile__ (// Save Single/Double FP registers, part 1
224 "std %%f0, %0;\n\t" "std %%f2, %1;\n\t"
225 "std %%f4, %2;\n\t" "std %%f6, %3;\n\t"
226 "std %%f8, %4;\n\t" "std %%f10, %5;\n\t"
227 "std %%f12, %6;\n\t" "std %%f14, %7;\n\t"
228 "std %%f16, %8;\n\t" "std %%f18, %9;\n\t"
229 "std %%f20, %10;\n\t" "std %%f22, %11;\n\t"
230 "std %%f24, %12;\n\t" "std %%f26, %13;\n\t"
231 "std %%f28, %14;\n\t" "std %%f30, %15;\n\t"
232 : "=m"(DoubleFP[ 0]), "=m"(DoubleFP[ 1]),
233 "=m"(DoubleFP[ 2]), "=m"(DoubleFP[ 3]),
234 "=m"(DoubleFP[ 4]), "=m"(DoubleFP[ 5]),
235 "=m"(DoubleFP[ 6]), "=m"(DoubleFP[ 7]),
236 "=m"(DoubleFP[ 8]), "=m"(DoubleFP[ 9]),
237 "=m"(DoubleFP[10]), "=m"(DoubleFP[11]),
238 "=m"(DoubleFP[12]), "=m"(DoubleFP[13]),
239 "=m"(DoubleFP[14]), "=m"(DoubleFP[15]));
241 __asm__ __volatile__ (// Save Double FP registers, part 2
242 "std %%f32, %0;\n\t" "std %%f34, %1;\n\t"
243 "std %%f36, %2;\n\t" "std %%f38, %3;\n\t"
244 "std %%f40, %4;\n\t" "std %%f42, %5;\n\t"
245 "std %%f44, %6;\n\t" "std %%f46, %7;\n\t"
246 "std %%f48, %8;\n\t" "std %%f50, %9;\n\t"
247 "std %%f52, %10;\n\t" "std %%f54, %11;\n\t"
248 "std %%f56, %12;\n\t" "std %%f58, %13;\n\t"
249 "std %%f60, %14;\n\t" "std %%f62, %15;\n\t"
250 : "=m"(DoubleFP[16]), "=m"(DoubleFP[17]),
251 "=m"(DoubleFP[18]), "=m"(DoubleFP[19]),
252 "=m"(DoubleFP[20]), "=m"(DoubleFP[21]),
253 "=m"(DoubleFP[22]), "=m"(DoubleFP[23]),
254 "=m"(DoubleFP[24]), "=m"(DoubleFP[25]),
255 "=m"(DoubleFP[26]), "=m"(DoubleFP[27]),
256 "=m"(DoubleFP[28]), "=m"(DoubleFP[29]),
257 "=m"(DoubleFP[30]), "=m"(DoubleFP[31]));
262 void JITResolver::RestoreRegisters(uint64_t DoubleFP[], uint64_t &FSR,
263 uint64_t &FPRS, uint64_t &CCR)
265 #if defined(sparc) || defined(__sparc__) || defined(__sparcv9)
268 __asm__ __volatile__ (// Restore condition-code registers
270 "wr %1, 0, %%fprs;\n\t"
271 "wr %2, 0, %%ccr;\n\t"
272 :: "m"(FSR), "r"(FPRS), "r"(CCR));
275 // GCC says: `asm' only allows up to thirty parameters!
276 __asm__ __volatile__ (// Restore Single/Double FP registers, part 1
277 "ldd %0, %%f0;\n\t" "ldd %1, %%f2;\n\t"
278 "ldd %2, %%f4;\n\t" "ldd %3, %%f6;\n\t"
279 "ldd %4, %%f8;\n\t" "ldd %5, %%f10;\n\t"
280 "ldd %6, %%f12;\n\t" "ldd %7, %%f14;\n\t"
281 "ldd %8, %%f16;\n\t" "ldd %9, %%f18;\n\t"
282 "ldd %10, %%f20;\n\t" "ldd %11, %%f22;\n\t"
283 "ldd %12, %%f24;\n\t" "ldd %13, %%f26;\n\t"
284 "ldd %14, %%f28;\n\t" "ldd %15, %%f30;\n\t"
285 :: "m"(DoubleFP[0]), "m"(DoubleFP[1]),
286 "m"(DoubleFP[2]), "m"(DoubleFP[3]),
287 "m"(DoubleFP[4]), "m"(DoubleFP[5]),
288 "m"(DoubleFP[6]), "m"(DoubleFP[7]),
289 "m"(DoubleFP[8]), "m"(DoubleFP[9]),
290 "m"(DoubleFP[10]), "m"(DoubleFP[11]),
291 "m"(DoubleFP[12]), "m"(DoubleFP[13]),
292 "m"(DoubleFP[14]), "m"(DoubleFP[15]));
294 __asm__ __volatile__ (// Restore Double FP registers, part 2
295 "ldd %0, %%f32;\n\t" "ldd %1, %%f34;\n\t"
296 "ldd %2, %%f36;\n\t" "ldd %3, %%f38;\n\t"
297 "ldd %4, %%f40;\n\t" "ldd %5, %%f42;\n\t"
298 "ldd %6, %%f44;\n\t" "ldd %7, %%f46;\n\t"
299 "ldd %8, %%f48;\n\t" "ldd %9, %%f50;\n\t"
300 "ldd %10, %%f52;\n\t" "ldd %11, %%f54;\n\t"
301 "ldd %12, %%f56;\n\t" "ldd %13, %%f58;\n\t"
302 "ldd %14, %%f60;\n\t" "ldd %15, %%f62;\n\t"
303 :: "m"(DoubleFP[16]), "m"(DoubleFP[17]),
304 "m"(DoubleFP[18]), "m"(DoubleFP[19]),
305 "m"(DoubleFP[20]), "m"(DoubleFP[21]),
306 "m"(DoubleFP[22]), "m"(DoubleFP[23]),
307 "m"(DoubleFP[24]), "m"(DoubleFP[25]),
308 "m"(DoubleFP[26]), "m"(DoubleFP[27]),
309 "m"(DoubleFP[28]), "m"(DoubleFP[29]),
310 "m"(DoubleFP[30]), "m"(DoubleFP[31]));
314 void JITResolver::CompilationCallback() {
315 // Local space to save double registers
316 uint64_t DoubleFP[32];
317 uint64_t FSR, FPRS, CCR;
319 SaveRegisters(DoubleFP, FSR, FPRS, CCR);
322 uint64_t CameFrom = (uint64_t)(intptr_t)__builtin_return_address(0);
323 uint64_t CameFrom1 = (uint64_t)(intptr_t)__builtin_return_address(1);
324 int64_t Target = (int64_t)TheJITResolver->resolveFunctionReference(CameFrom);
325 DEBUG(std::cerr << "In callback! Addr=0x" << std::hex << CameFrom << "\n");
326 register int64_t returnAddr = 0;
327 #if defined(sparc) || defined(__sparc__) || defined(__sparcv9)
328 __asm__ __volatile__ ("add %%i7, %%g0, %0" : "=r" (returnAddr) : );
329 DEBUG(std::cerr << "Read i7 (return addr) = "
330 << std::hex << returnAddr << ", value: "
331 << std::hex << *(unsigned*)returnAddr << "\n");
334 // If we can rewrite the ORIGINAL caller, we eliminate the whole need for a
335 // trampoline function stub!!
336 unsigned OrigCallInst = *((unsigned*)(intptr_t)CameFrom1);
337 int64_t OrigTarget = (Target-CameFrom1) >> 2;
338 if ((OrigCallInst & (1 << 30)) &&
339 (OrigTarget <= (1 << 30) && OrigTarget >= -(1 << 30)))
341 // The original call instruction was CALL <immed>, which means we can
342 // overwrite it directly, since the offset will fit into 30 bits
343 MachineInstr *C = BuildMI(V9::CALL, 1).addSImm(OrigTarget);
344 *((unsigned*)(intptr_t)CameFrom1)=TheJITResolver->getBinaryCodeForInstr(*C);
351 // Rewrite the call target so that we don't fault every time we execute it.
354 static const unsigned o6 = SparcIntRegClass::o6;
356 // Subtract enough to overwrite up to the 'save' instruction
357 // This depends on whether we made a short call (1 instruction) or the
358 // farCall (7 instructions)
359 uint64_t Offset = (LazyCallFlavor[CameFrom] == ShortCall) ? 4 : 28;
360 uint64_t CodeBegin = CameFrom - Offset;
362 // FIXME FIXME FIXME FIXME: __builtin_frame_address doesn't work if frame
363 // pointer elimination has been performed. Having a variable sized alloca
364 // disables frame pointer elimination currently, even if it's dead. This is
367 // FIXME FIXME FIXME FIXME
369 // Make sure that what we're about to overwrite is indeed "save"
370 MachineInstr *SV =BuildMI(V9::SAVEi, 3).addReg(o6).addSImm(-192).addReg(o6);
371 unsigned SaveInst = TheJITResolver->getBinaryCodeForInstr(*SV);
373 unsigned CodeInMem = *(unsigned*)(intptr_t)CodeBegin;
374 if (CodeInMem != SaveInst) {
375 std::cerr << "About to overwrite smthg not a save instr!";
379 TheJITResolver->insertJumpAtAddr(Target, CodeBegin);
381 RestoreRegisters(DoubleFP, FSR, FPRS, CCR);
383 // Change the return address to re-execute the restore, then the jump.
384 // However, we can't just modify %i7 here, because we return to the function
385 // that will restore the floating-point registers for us. Thus, we just return
386 // the value we want it to be, and the parent will take care of setting %i7
388 DEBUG(std::cerr << "Callback returning to: 0x"
389 << std::hex << (CameFrom-Offset-12) << "\n");
390 #if defined(sparc) || defined(__sparc__) || defined(__sparcv9)
391 __asm__ __volatile__ ("sub %%i7, %0, %%i7" : : "r" (Offset+12));
395 /// emitStubForFunction - This method is used by the JIT when it needs to emit
396 /// the address of a function for a function whose code has not yet been
397 /// generated. In order to do this, it generates a stub which jumps to the lazy
398 /// function compiler, which will eventually get fixed to call the function
401 uint64_t JITResolver::emitStubForFunction(Function *F) {
402 MCE.startFunctionStub(*F, 44);
404 DEBUG(std::cerr << "Emitting stub at addr: 0x"
405 << std::hex << MCE.getCurrentPCValue() << "\n");
407 unsigned o6 = SparcIntRegClass::o6, g0 = SparcIntRegClass::g0;
409 // restore %g0, 0, %g0
410 MachineInstr *R = BuildMI(V9::RESTOREi, 3).addMReg(g0).addSImm(0)
411 .addMReg(g0, MOTy::Def);
412 SparcV9.emitWord(SparcV9.getBinaryCodeForInstr(*R));
415 // save %sp, -192, %sp
416 MachineInstr *SV = BuildMI(V9::SAVEi, 3).addReg(o6).addSImm(-192).addReg(o6);
417 SparcV9.emitWord(SparcV9.getBinaryCodeForInstr(*SV));
420 int64_t CurrPC = MCE.getCurrentPCValue();
421 int64_t Addr = (int64_t)addFunctionReference(CurrPC, F);
422 int64_t CallTarget = (Addr-CurrPC) >> 2;
423 if (CallTarget >= (1 << 29) || CallTarget <= -(1 << 29)) {
424 // Since this is a far call, the actual address of the call is shifted
425 // by the number of instructions it takes to calculate the exact address
426 deleteFunctionReference(CurrPC);
427 SparcV9.emitFarCall(Addr, F);
429 // call CallTarget ;; invoke the callback
430 MachineInstr *Call = BuildMI(V9::CALL, 1).addSImm(CallTarget);
431 SparcV9.emitWord(SparcV9.getBinaryCodeForInstr(*Call));
434 // nop ;; call delay slot
435 MachineInstr *Nop = BuildMI(V9::NOP, 0);
436 SparcV9.emitWord(SparcV9.getBinaryCodeForInstr(*Nop));
439 addCallFlavor(CurrPC, ShortCall);
442 SparcV9.emitWord(0xDEADBEEF); // marker so that we know it's really a stub
443 return (intptr_t)MCE.finishFunctionStub(*F)+4; /* 1 instr past the restore */
447 SparcV9CodeEmitter::SparcV9CodeEmitter(TargetMachine &tm,
448 MachineCodeEmitter &M): TM(tm), MCE(M)
450 TheJITResolver = new JITResolver(*this, M);
453 SparcV9CodeEmitter::~SparcV9CodeEmitter() {
454 delete TheJITResolver;
457 void SparcV9CodeEmitter::emitWord(unsigned Val) {
458 // Output the constant in big endian byte order...
460 for (int i = 3; i >= 0; --i) {
461 byteVal = Val >> 8*i;
462 MCE.emitByte(byteVal & 255);
467 SparcV9CodeEmitter::getRealRegNum(unsigned fakeReg,
469 const TargetRegInfo &RI = TM.getRegInfo();
470 unsigned regClass, regType = RI.getRegType(fakeReg);
471 // At least map fakeReg into its class
472 fakeReg = RI.getClassRegNum(fakeReg, regClass);
475 case UltraSparcRegInfo::IntRegClassID: {
477 static const unsigned IntRegMap[] = {
478 // "o0", "o1", "o2", "o3", "o4", "o5", "o7",
479 8, 9, 10, 11, 12, 13, 15,
480 // "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
481 16, 17, 18, 19, 20, 21, 22, 23,
482 // "i0", "i1", "i2", "i3", "i4", "i5", "i6", "i7",
483 24, 25, 26, 27, 28, 29, 30, 31,
484 // "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
485 0, 1, 2, 3, 4, 5, 6, 7,
490 return IntRegMap[fakeReg];
493 case UltraSparcRegInfo::FloatRegClassID: {
494 DEBUG(std::cerr << "FP reg: " << fakeReg << "\n");
495 if (regType == UltraSparcRegInfo::FPSingleRegType) {
496 // only numbered 0-31, hence can already fit into 5 bits (and 6)
497 DEBUG(std::cerr << "FP single reg, returning: " << fakeReg << "\n");
498 } else if (regType == UltraSparcRegInfo::FPDoubleRegType) {
499 // FIXME: This assumes that we only have 5-bit register fields!
500 // From Sparc Manual, page 40.
501 // The bit layout becomes: b[4], b[3], b[2], b[1], b[5]
502 fakeReg |= (fakeReg >> 5) & 1;
504 DEBUG(std::cerr << "FP double reg, returning: " << fakeReg << "\n");
508 case UltraSparcRegInfo::IntCCRegClassID: {
510 static const unsigned IntCCReg[] = { 6, 4, 2 };
512 assert(fakeReg < sizeof(IntCCReg)/sizeof(IntCCReg[0])
513 && "CC register out of bounds for IntCCReg map");
514 DEBUG(std::cerr << "IntCC reg: " << IntCCReg[fakeReg] << "\n");
515 return IntCCReg[fakeReg];
517 case UltraSparcRegInfo::FloatCCRegClassID: {
518 /* These are laid out %fcc0 - %fcc3 => 0 - 3, so are correct */
519 DEBUG(std::cerr << "FP CC reg: " << fakeReg << "\n");
523 assert(0 && "Invalid unified register number in getRegType");
529 // WARNING: if the call used the delay slot to do meaningful work, that's not
530 // being accounted for, and the behavior will be incorrect!!
531 inline void SparcV9CodeEmitter::emitFarCall(uint64_t Target, Function *F) {
532 static const unsigned o6 = SparcIntRegClass::o6,
533 o7 = SparcIntRegClass::o7, g0 = SparcIntRegClass::g0,
534 g1 = SparcIntRegClass::g1, g5 = SparcIntRegClass::g5;
536 MachineInstr* BinaryCode[] = {
538 // Get address to branch into %g1, using %g5 as a temporary
540 // sethi %uhi(Target), %g5 ;; get upper 22 bits of Target into %g5
541 BuildMI(V9::SETHI, 2).addSImm(Target >> 42).addReg(g5),
542 // or %g5, %ulo(Target), %g5 ;; get 10 lower bits of upper word into %1
543 BuildMI(V9::ORi, 3).addReg(g5).addSImm((Target >> 32) & 0x03ff).addReg(g5),
544 // sllx %g5, 32, %g5 ;; shift those 10 bits to the upper word
545 BuildMI(V9::SLLXi6, 3).addReg(g5).addSImm(32).addReg(g5),
546 // sethi %hi(Target), %g1 ;; extract bits 10-31 into the dest reg
547 BuildMI(V9::SETHI, 2).addSImm((Target >> 10) & 0x03fffff).addReg(g1),
548 // or %g5, %g1, %g1 ;; get upper word (in %g5) into %g1
549 BuildMI(V9::ORr, 3).addReg(g5).addReg(g1).addReg(g1),
550 // or %g1, %lo(Target), %g1 ;; get lowest 10 bits of Target into %g1
551 BuildMI(V9::ORi, 3).addReg(g1).addSImm(Target & 0x03ff).addReg(g1),
552 // jmpl %g1, %g0, %o7 ;; indirect call on %g1
553 BuildMI(V9::JMPLRETr, 3).addReg(g1).addReg(g0).addReg(o7),
558 for (unsigned i=0, e=sizeof(BinaryCode)/sizeof(BinaryCode[0]); i!=e; ++i) {
559 // This is where we save the return address in the LazyResolverMap!!
560 if (i == 6 && F != 0) { // Do this right before the JMPL
561 uint64_t CurrPC = MCE.getCurrentPCValue();
562 TheJITResolver->addFunctionReference(CurrPC, F);
563 // Remember that this is a far call, to subtract appropriate offset later
564 TheJITResolver->addCallFlavor(CurrPC, JITResolver::FarCall);
567 emitWord(getBinaryCodeForInstr(*BinaryCode[i]));
568 delete BinaryCode[i];
572 void UltraSparc::replaceMachineCodeForFunction (void *Old, void *New) {
573 assert (TheJITResolver &&
574 "Can only call replaceMachineCodeForFunction from within JIT");
575 uint64_t Target = (uint64_t)(intptr_t)New;
576 uint64_t CodeBegin = (uint64_t)(intptr_t)Old;
577 TheJITResolver->insertJumpAtAddr(Target, CodeBegin);
580 int64_t SparcV9CodeEmitter::getMachineOpValue(MachineInstr &MI,
581 MachineOperand &MO) {
582 int64_t rv = 0; // Return value; defaults to 0 for unhandled cases
583 // or things that get fixed up later by the JIT.
585 if (MO.isVirtualRegister()) {
586 std::cerr << "ERROR: virtual register found in machine code.\n";
588 } else if (MO.isPCRelativeDisp()) {
589 DEBUG(std::cerr << "PCRelativeDisp: ");
590 Value *V = MO.getVRegValue();
591 if (BasicBlock *BB = dyn_cast<BasicBlock>(V)) {
592 DEBUG(std::cerr << "Saving reference to BB (VReg)\n");
593 unsigned* CurrPC = (unsigned*)(intptr_t)MCE.getCurrentPCValue();
594 BBRefs.push_back(std::make_pair(BB, std::make_pair(CurrPC, &MI)));
595 } else if (const Constant *C = dyn_cast<Constant>(V)) {
596 if (const ConstantInt *CI = dyn_cast<ConstantInt>(C)) {
597 rv = CI->getRawValue() - MCE.getCurrentPCValue();
599 std::cerr << "Cannot have non-integral const in instruction: "
603 } else if (GlobalValue *GV = dyn_cast<GlobalValue>(V)) {
604 // same as MO.isGlobalAddress()
605 DEBUG(std::cerr << "GlobalValue: ");
606 // external function calls, etc.?
607 if (Function *F = dyn_cast<Function>(GV)) {
608 DEBUG(std::cerr << "Function: ");
609 // NOTE: This results in stubs being generated even for
610 // external, native functions, which is not optimal. See PR103.
611 rv = (int64_t)MCE.getGlobalValueAddress(F);
613 DEBUG(std::cerr << "not yet generated\n");
614 // Function has not yet been code generated!
615 TheJITResolver->addFunctionReference(MCE.getCurrentPCValue(), F);
616 // Delayed resolution...
617 rv = TheJITResolver->getLazyResolver(F);
619 DEBUG(std::cerr << "already generated: 0x" << std::hex << rv << "\n");
622 rv = (int64_t)MCE.getGlobalValueAddress(GV);
623 DEBUG(std::cerr << "Global addr: 0x" << std::hex << rv << "\n");
625 // The real target of the call is Addr = PC + (rv * 4)
626 // So undo that: give the instruction (Addr - PC) / 4
627 if (MI.getOpcode() == V9::CALL) {
628 int64_t CurrPC = MCE.getCurrentPCValue();
629 DEBUG(std::cerr << "rv addr: 0x" << std::hex << rv << "\n"
630 << "curr PC: 0x" << std::hex << CurrPC << "\n");
631 int64_t CallInstTarget = (rv - CurrPC) >> 2;
632 if (CallInstTarget >= (1<<29) || CallInstTarget <= -(1<<29)) {
633 DEBUG(std::cerr << "Making far call!\n");
634 // address is out of bounds for the 30-bit call,
635 // make an indirect jump-and-link
637 // this invalidates the instruction so that the call with an incorrect
638 // address will not be emitted
641 // The call fits into 30 bits, so just return the corrected address
644 DEBUG(std::cerr << "returning addr: 0x" << rv << "\n");
647 std::cerr << "ERROR: PC relative disp unhandled:" << MO << "\n";
650 } else if (MO.isPhysicalRegister() ||
651 MO.getType() == MachineOperand::MO_CCRegister)
653 // This is necessary because the Sparc backend doesn't actually lay out
654 // registers in the real fashion -- it skips those that it chooses not to
655 // allocate, i.e. those that are the FP, SP, etc.
656 unsigned fakeReg = MO.getAllocatedRegNum();
657 unsigned realRegByClass = getRealRegNum(fakeReg, MI);
658 DEBUG(std::cerr << MO << ": Reg[" << std::dec << fakeReg << "] => "
659 << realRegByClass << " (LLC: "
660 << TM.getRegInfo().getUnifiedRegName(fakeReg) << ")\n");
662 } else if (MO.isImmediate()) {
663 rv = MO.getImmedValue();
664 DEBUG(std::cerr << "immed: " << rv << "\n");
665 } else if (MO.isGlobalAddress()) {
666 DEBUG(std::cerr << "GlobalAddress: not PC-relative\n");
668 (intptr_t)getGlobalAddress(cast<GlobalValue>(MO.getVRegValue()),
669 MI, MO.isPCRelative());
670 } else if (MO.isMachineBasicBlock()) {
671 // Duplicate code of the above case for VirtualRegister, BasicBlock...
672 // It should really hit this case, but Sparc backend uses VRegs instead
673 DEBUG(std::cerr << "Saving reference to MBB\n");
674 const BasicBlock *BB = MO.getMachineBasicBlock()->getBasicBlock();
675 unsigned* CurrPC = (unsigned*)(intptr_t)MCE.getCurrentPCValue();
676 BBRefs.push_back(std::make_pair(BB, std::make_pair(CurrPC, &MI)));
677 } else if (MO.isExternalSymbol()) {
678 // Sparc backend doesn't generate this (yet...)
679 std::cerr << "ERROR: External symbol unhandled: " << MO << "\n";
681 } else if (MO.isFrameIndex()) {
682 // Sparc backend doesn't generate this (yet...)
683 int FrameIndex = MO.getFrameIndex();
684 std::cerr << "ERROR: Frame index unhandled.\n";
686 } else if (MO.isConstantPoolIndex()) {
687 unsigned Index = MO.getConstantPoolIndex();
688 rv = MCE.getConstantPoolEntryAddress(Index);
690 std::cerr << "ERROR: Unknown type of MachineOperand: " << MO << "\n";
694 // Finally, deal with the various bitfield-extracting functions that
695 // are used in SPARC assembly. (Some of these make no sense in combination
696 // with some of the above; we'll trust that the instruction selector
697 // will not produce nonsense, and not check for valid combinations here.)
698 if (MO.opLoBits32()) { // %lo(val) == %lo() in Sparc ABI doc
700 } else if (MO.opHiBits32()) { // %lm(val) == %hi() in Sparc ABI doc
701 return (rv >> 10) & 0x03fffff;
702 } else if (MO.opLoBits64()) { // %hm(val) == %ulo() in Sparc ABI doc
703 return (rv >> 32) & 0x03ff;
704 } else if (MO.opHiBits64()) { // %hh(val) == %uhi() in Sparc ABI doc
706 } else { // (unadorned) val
711 unsigned SparcV9CodeEmitter::getValueBit(int64_t Val, unsigned bit) {
716 bool SparcV9CodeEmitter::runOnMachineFunction(MachineFunction &MF) {
717 MCE.startFunction(MF);
718 DEBUG(std::cerr << "Starting function " << MF.getFunction()->getName()
719 << ", address: " << "0x" << std::hex
720 << (long)MCE.getCurrentPCValue() << "\n");
722 MCE.emitConstantPool(MF.getConstantPool());
723 for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I)
725 MCE.finishFunction(MF);
727 DEBUG(std::cerr << "Finishing fn " << MF.getFunction()->getName() << "\n");
729 // Resolve branches to BasicBlocks for the entire function
730 for (unsigned i = 0, e = BBRefs.size(); i != e; ++i) {
731 long Location = BBLocations[BBRefs[i].first];
732 unsigned *Ref = BBRefs[i].second.first;
733 MachineInstr *MI = BBRefs[i].second.second;
734 DEBUG(std::cerr << "Fixup @ " << std::hex << Ref << " to 0x" << Location
735 << " in instr: " << std::dec << *MI);
736 for (unsigned ii = 0, ee = MI->getNumOperands(); ii != ee; ++ii) {
737 MachineOperand &op = MI->getOperand(ii);
738 if (op.isPCRelativeDisp()) {
739 // the instruction's branch target is made such that it branches to
740 // PC + (branchTarget * 4), so undo that arithmetic here:
741 // Location is the target of the branch
742 // Ref is the location of the instruction, and hence the PC
743 int64_t branchTarget = (Location - (long)Ref) >> 2;
745 bool loBits32=false, hiBits32=false, loBits64=false, hiBits64=false;
746 if (op.opLoBits32()) { loBits32=true; }
747 if (op.opHiBits32()) { hiBits32=true; }
748 if (op.opLoBits64()) { loBits64=true; }
749 if (op.opHiBits64()) { hiBits64=true; }
750 MI->SetMachineOperandConst(ii, MachineOperand::MO_SignExtendedImmed,
752 if (loBits32) { MI->setOperandLo32(ii); }
753 else if (hiBits32) { MI->setOperandHi32(ii); }
754 else if (loBits64) { MI->setOperandLo64(ii); }
755 else if (hiBits64) { MI->setOperandHi64(ii); }
756 DEBUG(std::cerr << "Rewrote BB ref: ");
757 unsigned fixedInstr = SparcV9CodeEmitter::getBinaryCodeForInstr(*MI);
769 void SparcV9CodeEmitter::emitBasicBlock(MachineBasicBlock &MBB) {
770 currBB = MBB.getBasicBlock();
771 BBLocations[currBB] = MCE.getCurrentPCValue();
772 for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); I != E; ++I){
773 unsigned binCode = getBinaryCodeForInstr(**I);
774 if (binCode == (1 << 30)) {
775 // this is an invalid call: the addr is out of bounds. that means a code
776 // sequence has already been emitted, and this is a no-op
777 DEBUG(std::cerr << "Call supressed: already emitted far call.\n");
784 void* SparcV9CodeEmitter::getGlobalAddress(GlobalValue *V, MachineInstr &MI,
787 if (isPCRelative) { // must be a call, this is a major hack!
788 // Try looking up the function to see if it is already compiled!
789 if (void *Addr = (void*)(intptr_t)MCE.getGlobalValueAddress(V)) {
790 intptr_t CurByte = MCE.getCurrentPCValue();
791 // The real target of the call is Addr = PC + (target * 4)
792 // CurByte is the PC, Addr we just received
793 return (void*) (((long)Addr - (long)CurByte) >> 2);
795 if (Function *F = dyn_cast<Function>(V)) {
796 // Function has not yet been code generated!
797 TheJITResolver->addFunctionReference(MCE.getCurrentPCValue(),
799 // Delayed resolution...
801 (void*)(intptr_t)TheJITResolver->getLazyResolver(cast<Function>(V));
803 std::cerr << "Unhandled global: " << *V << "\n";
808 return (void*)(intptr_t)MCE.getGlobalValueAddress(V);
812 #include "SparcV9CodeEmitter.inc"