1 //===-- SparcV9CodeEmitter.cpp --------------------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // SPARC-specific backend for emitting machine code to memory.
12 // This module also contains the code for lazily resolving the targets
13 // of call instructions, including the callback used to redirect calls
14 // to functions for which the code has not yet been generated into the
17 // This file #includes SparcV9CodeEmitter.inc, which contains the code
18 // for getBinaryCodeForInstr(), a method that converts a MachineInstr
19 // into the corresponding binary machine code word.
21 //===----------------------------------------------------------------------===//
23 #include "llvm/Constants.h"
24 #include "llvm/Function.h"
25 #include "llvm/GlobalVariable.h"
26 #include "llvm/PassManager.h"
27 #include "llvm/CodeGen/MachineCodeEmitter.h"
28 #include "llvm/CodeGen/MachineConstantPool.h"
29 #include "llvm/CodeGen/MachineFunctionPass.h"
30 #include "llvm/CodeGen/MachineInstr.h"
31 #include "llvm/Target/TargetMachine.h"
32 #include "llvm/Target/TargetData.h"
33 #include "llvm/Support/Debug.h"
34 #include "llvm/ADT/hash_set"
35 #include "llvm/ADT/Statistic.h"
36 #include "SparcV9Internals.h"
37 #include "SparcV9TargetMachine.h"
38 #include "SparcV9RegInfo.h"
39 #include "SparcV9CodeEmitter.h"
40 #include "MachineFunctionInfo.h"
41 #include "llvm/Config/alloca.h"
46 Statistic<> OverwrittenCalls("call-ovwr", "Number of over-written calls");
47 Statistic<> UnmodifiedCalls("call-skip", "Number of unmodified calls");
48 Statistic<> CallbackCalls("callback", "Number CompilationCallback() calls");
51 bool SparcV9TargetMachine::addPassesToEmitMachineCode(FunctionPassManager &PM,
52 MachineCodeEmitter &MCE) {
53 PM.add(new SparcV9CodeEmitter(*this, MCE));
54 PM.add(createSparcV9MachineCodeDestructionPass());
60 SparcV9CodeEmitter &SparcV9;
61 MachineCodeEmitter &MCE;
63 /// LazyCodeGenMap - Keep track of call sites for functions that are to be
66 std::map<uint64_t, Function*> LazyCodeGenMap;
68 /// LazyResolverMap - Keep track of the lazy resolver created for a
69 /// particular function so that we can reuse them if necessary.
71 std::map<Function*, uint64_t> LazyResolverMap;
74 enum CallType { ShortCall, FarCall };
77 /// We need to keep track of whether we used a simple call or a far call
78 /// (many instructions) in sequence. This means we need to keep track of
79 /// what type of stub we generate.
80 static std::map<uint64_t, CallType> LazyCallFlavor;
83 JITResolver(SparcV9CodeEmitter &V9,
84 MachineCodeEmitter &mce) : SparcV9(V9), MCE(mce) {}
85 uint64_t getLazyResolver(Function *F);
86 uint64_t addFunctionReference(uint64_t Address, Function *F);
87 void deleteFunctionReference(uint64_t Address);
88 void addCallFlavor(uint64_t Address, CallType Flavor) {
89 LazyCallFlavor[Address] = Flavor;
92 // Utility functions for accessing data from static callback
93 uint64_t getCurrentPCValue() {
94 return MCE.getCurrentPCValue();
96 unsigned getBinaryCodeForInstr(MachineInstr &MI) {
97 return SparcV9.getBinaryCodeForInstr(MI);
100 inline void insertFarJumpAtAddr(int64_t Value, uint64_t Addr);
101 void insertJumpAtAddr(int64_t Value, uint64_t &Addr);
104 uint64_t emitStubForFunction(Function *F);
105 static void SaveRegisters(uint64_t DoubleFP[], uint64_t CC[],
107 static void RestoreRegisters(uint64_t DoubleFP[], uint64_t CC[],
109 static void CompilationCallback();
110 uint64_t resolveFunctionReference(uint64_t RetAddr);
114 JITResolver *TheJITResolver;
115 std::map<uint64_t, JITResolver::CallType> JITResolver::LazyCallFlavor;
118 /// addFunctionReference - This method is called when we need to emit the
119 /// address of a function that has not yet been emitted, so we don't know the
120 /// address. Instead, we emit a call to the CompilationCallback method, and
121 /// keep track of where we are.
123 uint64_t JITResolver::addFunctionReference(uint64_t Address, Function *F) {
124 LazyCodeGenMap[Address] = F;
125 return (intptr_t)&JITResolver::CompilationCallback;
128 /// deleteFunctionReference - If we are emitting a far call, we already added a
129 /// reference to the function, but it is now incorrect, since the address to the
130 /// JIT resolver is too far away to be a simple call instruction. This is used
131 /// to remove the address from the map.
133 void JITResolver::deleteFunctionReference(uint64_t Address) {
134 std::map<uint64_t, Function*>::iterator I = LazyCodeGenMap.find(Address);
135 assert(I != LazyCodeGenMap.end() && "Not in map!");
136 LazyCodeGenMap.erase(I);
139 uint64_t JITResolver::resolveFunctionReference(uint64_t RetAddr) {
140 std::map<uint64_t, Function*>::iterator I = LazyCodeGenMap.find(RetAddr);
141 assert(I != LazyCodeGenMap.end() && "Not in map!");
142 Function *F = I->second;
143 LazyCodeGenMap.erase(I);
144 return MCE.forceCompilationOf(F);
147 uint64_t JITResolver::getLazyResolver(Function *F) {
148 std::map<Function*, uint64_t>::iterator I = LazyResolverMap.lower_bound(F);
149 if (I != LazyResolverMap.end() && I->first == F) return I->second;
151 uint64_t Stub = emitStubForFunction(F);
152 LazyResolverMap.insert(I, std::make_pair(F, Stub));
156 void JITResolver::insertJumpAtAddr(int64_t JumpTarget, uint64_t &Addr) {
157 DEBUG(std::cerr << "Emitting a jump to 0x" << std::hex << JumpTarget << "\n");
159 // If the target function is close enough to fit into the 19bit disp of
160 // BA, we should use this version, as it's much cheaper to generate.
161 int64_t BranchTarget = (JumpTarget-Addr) >> 2;
162 if (BranchTarget >= (1 << 19) || BranchTarget <= -(1 << 19)) {
163 TheJITResolver->insertFarJumpAtAddr(JumpTarget, Addr);
166 MachineInstr *I = BuildMI(V9::BA, 1).addSImm(BranchTarget);
167 *((unsigned*)(intptr_t)Addr) = getBinaryCodeForInstr(*I);
172 I = BuildMI(V9::NOP, 0);
173 *((unsigned*)(intptr_t)Addr) = getBinaryCodeForInstr(*I);
178 void JITResolver::insertFarJumpAtAddr(int64_t Target, uint64_t Addr) {
179 static const unsigned
180 o6 = SparcV9IntRegClass::o6, g0 = SparcV9IntRegClass::g0,
181 g1 = SparcV9IntRegClass::g1, g5 = SparcV9IntRegClass::g5;
183 MachineInstr* BinaryCode[] = {
185 // Get address to branch into %g1, using %g5 as a temporary
187 // sethi %uhi(Target), %g5 ;; get upper 22 bits of Target into %g5
188 BuildMI(V9::SETHI, 2).addSImm(Target >> 42).addReg(g5),
189 // or %g5, %ulo(Target), %g5 ;; get 10 lower bits of upper word into %g5
190 BuildMI(V9::ORi, 3).addReg(g5).addSImm((Target >> 32) & 0x03ff).addReg(g5),
191 // sllx %g5, 32, %g5 ;; shift those 10 bits to the upper word
192 BuildMI(V9::SLLXi6, 3).addReg(g5).addSImm(32).addReg(g5),
193 // sethi %hi(Target), %g1 ;; extract bits 10-31 into the dest reg
194 BuildMI(V9::SETHI, 2).addSImm((Target >> 10) & 0x03fffff).addReg(g1),
195 // or %g5, %g1, %g1 ;; get upper word (in %g5) into %g1
196 BuildMI(V9::ORr, 3).addReg(g5).addReg(g1).addReg(g1),
197 // or %g1, %lo(Target), %g1 ;; get lowest 10 bits of Target into %g1
198 BuildMI(V9::ORi, 3).addReg(g1).addSImm(Target & 0x03ff).addReg(g1),
199 // jmpl %g1, %g0, %g0 ;; indirect branch on %g1
200 BuildMI(V9::JMPLRETr, 3).addReg(g1).addReg(g0).addReg(g0),
205 for (unsigned i=0, e=sizeof(BinaryCode)/sizeof(BinaryCode[0]); i!=e; ++i) {
206 *((unsigned*)(intptr_t)Addr) = getBinaryCodeForInstr(*BinaryCode[i]);
207 delete BinaryCode[i];
212 void JITResolver::SaveRegisters(uint64_t DoubleFP[], uint64_t CC[],
213 uint64_t Globals[]) {
214 #if defined(__sparcv9)
216 __asm__ __volatile__ (// Save condition-code registers
220 : "=m"(CC[0]), "=r"(CC[1]), "=r"(CC[2]));
222 __asm__ __volatile__ (// Save globals g1 and g5
225 : "=m"(Globals[0]), "=m"(Globals[1]));
227 // GCC says: `asm' only allows up to thirty parameters!
228 __asm__ __volatile__ (// Save Single/Double FP registers, part 1
229 "std %%f0, %0;\n\t" "std %%f2, %1;\n\t"
230 "std %%f4, %2;\n\t" "std %%f6, %3;\n\t"
231 "std %%f8, %4;\n\t" "std %%f10, %5;\n\t"
232 "std %%f12, %6;\n\t" "std %%f14, %7;\n\t"
233 "std %%f16, %8;\n\t" "std %%f18, %9;\n\t"
234 "std %%f20, %10;\n\t" "std %%f22, %11;\n\t"
235 "std %%f24, %12;\n\t" "std %%f26, %13;\n\t"
236 "std %%f28, %14;\n\t" "std %%f30, %15;\n\t"
237 : "=m"(DoubleFP[ 0]), "=m"(DoubleFP[ 1]),
238 "=m"(DoubleFP[ 2]), "=m"(DoubleFP[ 3]),
239 "=m"(DoubleFP[ 4]), "=m"(DoubleFP[ 5]),
240 "=m"(DoubleFP[ 6]), "=m"(DoubleFP[ 7]),
241 "=m"(DoubleFP[ 8]), "=m"(DoubleFP[ 9]),
242 "=m"(DoubleFP[10]), "=m"(DoubleFP[11]),
243 "=m"(DoubleFP[12]), "=m"(DoubleFP[13]),
244 "=m"(DoubleFP[14]), "=m"(DoubleFP[15]));
246 __asm__ __volatile__ (// Save Double FP registers, part 2
247 "std %%f32, %0;\n\t" "std %%f34, %1;\n\t"
248 "std %%f36, %2;\n\t" "std %%f38, %3;\n\t"
249 "std %%f40, %4;\n\t" "std %%f42, %5;\n\t"
250 "std %%f44, %6;\n\t" "std %%f46, %7;\n\t"
251 "std %%f48, %8;\n\t" "std %%f50, %9;\n\t"
252 "std %%f52, %10;\n\t" "std %%f54, %11;\n\t"
253 "std %%f56, %12;\n\t" "std %%f58, %13;\n\t"
254 "std %%f60, %14;\n\t" "std %%f62, %15;\n\t"
255 : "=m"(DoubleFP[16]), "=m"(DoubleFP[17]),
256 "=m"(DoubleFP[18]), "=m"(DoubleFP[19]),
257 "=m"(DoubleFP[20]), "=m"(DoubleFP[21]),
258 "=m"(DoubleFP[22]), "=m"(DoubleFP[23]),
259 "=m"(DoubleFP[24]), "=m"(DoubleFP[25]),
260 "=m"(DoubleFP[26]), "=m"(DoubleFP[27]),
261 "=m"(DoubleFP[28]), "=m"(DoubleFP[29]),
262 "=m"(DoubleFP[30]), "=m"(DoubleFP[31]));
264 std::cerr << "ERROR: RUNNING CODE THAT ONLY WORKS ON A SPARCV9 HOST!\n";
270 void JITResolver::RestoreRegisters(uint64_t DoubleFP[], uint64_t CC[],
273 #if defined(__sparcv9)
275 __asm__ __volatile__ (// Restore condition-code registers
277 "wr %1, 0, %%fprs;\n\t"
278 "wr %2, 0, %%ccr;\n\t"
279 :: "m"(CC[0]), "r"(CC[1]), "r"(CC[2]));
281 __asm__ __volatile__ (// Restore globals g1 and g5
284 :: "m"(Globals[0]), "m"(Globals[1]));
286 // GCC says: `asm' only allows up to thirty parameters!
287 __asm__ __volatile__ (// Restore Single/Double FP registers, part 1
288 "ldd %0, %%f0;\n\t" "ldd %1, %%f2;\n\t"
289 "ldd %2, %%f4;\n\t" "ldd %3, %%f6;\n\t"
290 "ldd %4, %%f8;\n\t" "ldd %5, %%f10;\n\t"
291 "ldd %6, %%f12;\n\t" "ldd %7, %%f14;\n\t"
292 "ldd %8, %%f16;\n\t" "ldd %9, %%f18;\n\t"
293 "ldd %10, %%f20;\n\t" "ldd %11, %%f22;\n\t"
294 "ldd %12, %%f24;\n\t" "ldd %13, %%f26;\n\t"
295 "ldd %14, %%f28;\n\t" "ldd %15, %%f30;\n\t"
296 :: "m"(DoubleFP[0]), "m"(DoubleFP[1]),
297 "m"(DoubleFP[2]), "m"(DoubleFP[3]),
298 "m"(DoubleFP[4]), "m"(DoubleFP[5]),
299 "m"(DoubleFP[6]), "m"(DoubleFP[7]),
300 "m"(DoubleFP[8]), "m"(DoubleFP[9]),
301 "m"(DoubleFP[10]), "m"(DoubleFP[11]),
302 "m"(DoubleFP[12]), "m"(DoubleFP[13]),
303 "m"(DoubleFP[14]), "m"(DoubleFP[15]));
305 __asm__ __volatile__ (// Restore Double FP registers, part 2
306 "ldd %0, %%f32;\n\t" "ldd %1, %%f34;\n\t"
307 "ldd %2, %%f36;\n\t" "ldd %3, %%f38;\n\t"
308 "ldd %4, %%f40;\n\t" "ldd %5, %%f42;\n\t"
309 "ldd %6, %%f44;\n\t" "ldd %7, %%f46;\n\t"
310 "ldd %8, %%f48;\n\t" "ldd %9, %%f50;\n\t"
311 "ldd %10, %%f52;\n\t" "ldd %11, %%f54;\n\t"
312 "ldd %12, %%f56;\n\t" "ldd %13, %%f58;\n\t"
313 "ldd %14, %%f60;\n\t" "ldd %15, %%f62;\n\t"
314 :: "m"(DoubleFP[16]), "m"(DoubleFP[17]),
315 "m"(DoubleFP[18]), "m"(DoubleFP[19]),
316 "m"(DoubleFP[20]), "m"(DoubleFP[21]),
317 "m"(DoubleFP[22]), "m"(DoubleFP[23]),
318 "m"(DoubleFP[24]), "m"(DoubleFP[25]),
319 "m"(DoubleFP[26]), "m"(DoubleFP[27]),
320 "m"(DoubleFP[28]), "m"(DoubleFP[29]),
321 "m"(DoubleFP[30]), "m"(DoubleFP[31]));
323 std::cerr << "ERROR: RUNNING CODE THAT ONLY WORKS ON A SPARCV9 HOST!\n";
328 void JITResolver::CompilationCallback() {
329 // Local space to save the registers
330 uint64_t DoubleFP[32];
334 SaveRegisters(DoubleFP, CC, Globals);
337 uint64_t CameFrom = (uint64_t)(intptr_t)__builtin_return_address(0);
338 uint64_t CameFrom1 = (uint64_t)(intptr_t)__builtin_return_address(1);
339 int64_t Target = (int64_t)TheJITResolver->resolveFunctionReference(CameFrom);
340 DEBUG(std::cerr << "In callback! Addr=0x" << std::hex << CameFrom << "\n");
341 register int64_t returnAddr = 0;
342 #if defined(__sparcv9)
343 __asm__ __volatile__ ("add %%i7, %%g0, %0" : "=r" (returnAddr) : );
344 DEBUG(std::cerr << "Read i7 (return addr) = "
345 << std::hex << returnAddr << ", value: "
346 << std::hex << *(unsigned*)returnAddr << "\n");
348 std::cerr << "ERROR: RUNNING CODE THAT ONLY WORKS ON A SPARCV9 HOST!\n";
352 // If we can rewrite the ORIGINAL caller, we eliminate the whole need for a
353 // trampoline function stub!!
354 unsigned OrigCallInst = *((unsigned*)(intptr_t)CameFrom1);
355 int64_t OrigTarget = (Target-CameFrom1) >> 2;
356 if ((OrigCallInst & (1 << 30)) &&
357 (OrigTarget <= (1 << 30) && OrigTarget >= -(1 << 30)))
359 // The original call instruction was CALL <immed>, which means we can
360 // overwrite it directly, since the offset will fit into 30 bits
361 MachineInstr *C = BuildMI(V9::CALL, 1).addSImm(OrigTarget);
362 *((unsigned*)(intptr_t)CameFrom1)=TheJITResolver->getBinaryCodeForInstr(*C);
369 // Rewrite the call target so that we don't fault every time we execute it.
372 static const unsigned o6 = SparcV9IntRegClass::o6;
374 // Subtract enough to overwrite up to the 'save' instruction
375 // This depends on whether we made a short call (1 instruction) or the
376 // farCall (7 instructions)
377 uint64_t Offset = (LazyCallFlavor[CameFrom] == ShortCall) ? 4 : 28;
378 uint64_t CodeBegin = CameFrom - Offset;
380 // FIXME FIXME FIXME FIXME: __builtin_frame_address doesn't work if frame
381 // pointer elimination has been performed. Having a variable sized alloca
382 // disables frame pointer elimination currently, even if it's dead. This is
385 // FIXME FIXME FIXME FIXME
387 // Make sure that what we're about to overwrite is indeed "save"
388 MachineInstr *SV =BuildMI(V9::SAVEi, 3).addReg(o6).addSImm(-192).addReg(o6);
389 unsigned SaveInst = TheJITResolver->getBinaryCodeForInstr(*SV);
391 unsigned CodeInMem = *(unsigned*)(intptr_t)CodeBegin;
392 if (CodeInMem != SaveInst) {
393 std::cerr << "About to overwrite smthg not a save instr!";
397 TheJITResolver->insertJumpAtAddr(Target, CodeBegin);
399 // Flush the I-Cache: FLUSH clears out a doubleword at a given address
400 // Self-modifying code MUST clear out the I-Cache to be portable
401 #if defined(__sparcv9)
402 for (int i = -Offset, e = 32-((int64_t)Offset); i < e; i += 8)
403 __asm__ __volatile__ ("flush %%i7 + %0" : : "r" (i));
406 // Change the return address to re-execute the restore, then the jump.
407 DEBUG(std::cerr << "Callback returning to: 0x"
408 << std::hex << (CameFrom-Offset-12) << "\n");
409 #if defined(__sparcv9)
410 __asm__ __volatile__ ("sub %%i7, %0, %%i7" : : "r" (Offset+12));
413 RestoreRegisters(DoubleFP, CC, Globals);
416 /// emitStubForFunction - This method is used by the JIT when it needs to emit
417 /// the address of a function for a function whose code has not yet been
418 /// generated. In order to do this, it generates a stub which jumps to the lazy
419 /// function compiler, which will eventually get fixed to call the function
422 uint64_t JITResolver::emitStubForFunction(Function *F) {
423 MCE.startFunctionStub(44);
425 DEBUG(std::cerr << "Emitting stub at addr: 0x"
426 << std::hex << MCE.getCurrentPCValue() << "\n");
428 unsigned o6 = SparcV9IntRegClass::o6, g0 = SparcV9IntRegClass::g0;
430 // restore %g0, 0, %g0
431 MachineInstr *R = BuildMI(V9::RESTOREi, 3).addMReg(g0).addSImm(0)
432 .addMReg(g0, MachineOperand::Def);
433 SparcV9.emitWord(SparcV9.getBinaryCodeForInstr(*R));
436 // save %sp, -192, %sp
437 MachineInstr *SV = BuildMI(V9::SAVEi, 3).addReg(o6).addSImm(-192).addReg(o6);
438 SparcV9.emitWord(SparcV9.getBinaryCodeForInstr(*SV));
441 int64_t CurrPC = MCE.getCurrentPCValue();
442 int64_t Addr = (int64_t)addFunctionReference(CurrPC, F);
443 int64_t CallTarget = (Addr-CurrPC) >> 2;
444 if (CallTarget >= (1 << 29) || CallTarget <= -(1 << 29)) {
445 // Since this is a far call, the actual address of the call is shifted
446 // by the number of instructions it takes to calculate the exact address
447 deleteFunctionReference(CurrPC);
448 SparcV9.emitFarCall(Addr, F);
450 // call CallTarget ;; invoke the callback
451 MachineInstr *Call = BuildMI(V9::CALL, 1).addSImm(CallTarget);
452 SparcV9.emitWord(SparcV9.getBinaryCodeForInstr(*Call));
455 // nop ;; call delay slot
456 MachineInstr *Nop = BuildMI(V9::NOP, 0);
457 SparcV9.emitWord(SparcV9.getBinaryCodeForInstr(*Nop));
460 addCallFlavor(CurrPC, ShortCall);
463 SparcV9.emitWord(0xDEADBEEF); // marker so that we know it's really a stub
464 return (intptr_t)MCE.finishFunctionStub(F)+4; /* 1 instr past the restore */
467 SparcV9CodeEmitter::SparcV9CodeEmitter(TargetMachine &tm,
468 MachineCodeEmitter &M): TM(tm), MCE(M)
470 TheJITResolver = new JITResolver(*this, M);
473 SparcV9CodeEmitter::~SparcV9CodeEmitter() {
474 delete TheJITResolver;
477 void SparcV9CodeEmitter::emitWord(unsigned Val) {
482 SparcV9CodeEmitter::getRealRegNum(unsigned fakeReg,
484 const SparcV9RegInfo &RI = *TM.getRegInfo();
485 unsigned regClass, regType = RI.getRegType(fakeReg);
486 // At least map fakeReg into its class
487 fakeReg = RI.getClassRegNum(fakeReg, regClass);
490 case SparcV9RegInfo::IntRegClassID: {
491 // SparcV9 manual, p31
492 static const unsigned IntRegMap[] = {
493 // "o0", "o1", "o2", "o3", "o4", "o5", "o7",
494 8, 9, 10, 11, 12, 13, 15,
495 // "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
496 16, 17, 18, 19, 20, 21, 22, 23,
497 // "i0", "i1", "i2", "i3", "i4", "i5", "i6", "i7",
498 24, 25, 26, 27, 28, 29, 30, 31,
499 // "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
500 0, 1, 2, 3, 4, 5, 6, 7,
505 return IntRegMap[fakeReg];
508 case SparcV9RegInfo::FloatRegClassID: {
509 DEBUG(std::cerr << "FP reg: " << fakeReg << "\n");
510 if (regType == SparcV9RegInfo::FPSingleRegType) {
511 // only numbered 0-31, hence can already fit into 5 bits (and 6)
512 DEBUG(std::cerr << "FP single reg, returning: " << fakeReg << "\n");
513 } else if (regType == SparcV9RegInfo::FPDoubleRegType) {
514 // FIXME: This assumes that we only have 5-bit register fields!
515 // From SparcV9 Manual, page 40.
516 // The bit layout becomes: b[4], b[3], b[2], b[1], b[5]
517 fakeReg |= (fakeReg >> 5) & 1;
519 DEBUG(std::cerr << "FP double reg, returning: " << fakeReg << "\n");
523 case SparcV9RegInfo::IntCCRegClassID: {
525 static const unsigned IntCCReg[] = { 6, 4, 2 };
527 assert(fakeReg < sizeof(IntCCReg)/sizeof(IntCCReg[0])
528 && "CC register out of bounds for IntCCReg map");
529 DEBUG(std::cerr << "IntCC reg: " << IntCCReg[fakeReg] << "\n");
530 return IntCCReg[fakeReg];
532 case SparcV9RegInfo::FloatCCRegClassID: {
533 /* These are laid out %fcc0 - %fcc3 => 0 - 3, so are correct */
534 DEBUG(std::cerr << "FP CC reg: " << fakeReg << "\n");
537 case SparcV9RegInfo::SpecialRegClassID: {
538 // Currently only "special" reg is %fsr, which is encoded as 1 in
539 // instructions and 0 in SparcV9SpecialRegClass.
540 static const unsigned SpecialReg[] = { 1 };
541 assert(fakeReg < sizeof(SpecialReg)/sizeof(SpecialReg[0])
542 && "Special register out of bounds for SpecialReg map");
543 DEBUG(std::cerr << "Special reg: " << SpecialReg[fakeReg] << "\n");
544 return SpecialReg[fakeReg];
547 assert(0 && "Invalid unified register number in getRealRegNum");
553 // WARNING: if the call used the delay slot to do meaningful work, that's not
554 // being accounted for, and the behavior will be incorrect!!
555 inline void SparcV9CodeEmitter::emitFarCall(uint64_t Target, Function *F) {
556 static const unsigned o6 = SparcV9IntRegClass::o6,
557 o7 = SparcV9IntRegClass::o7, g0 = SparcV9IntRegClass::g0,
558 g1 = SparcV9IntRegClass::g1, g5 = SparcV9IntRegClass::g5;
560 MachineInstr* BinaryCode[] = {
562 // Get address to branch into %g1, using %g5 as a temporary
564 // sethi %uhi(Target), %g5 ;; get upper 22 bits of Target into %g5
565 BuildMI(V9::SETHI, 2).addSImm(Target >> 42).addReg(g5),
566 // or %g5, %ulo(Target), %g5 ;; get 10 lower bits of upper word into %1
567 BuildMI(V9::ORi, 3).addReg(g5).addSImm((Target >> 32) & 0x03ff).addReg(g5),
568 // sllx %g5, 32, %g5 ;; shift those 10 bits to the upper word
569 BuildMI(V9::SLLXi6, 3).addReg(g5).addSImm(32).addReg(g5),
570 // sethi %hi(Target), %g1 ;; extract bits 10-31 into the dest reg
571 BuildMI(V9::SETHI, 2).addSImm((Target >> 10) & 0x03fffff).addReg(g1),
572 // or %g5, %g1, %g1 ;; get upper word (in %g5) into %g1
573 BuildMI(V9::ORr, 3).addReg(g5).addReg(g1).addReg(g1),
574 // or %g1, %lo(Target), %g1 ;; get lowest 10 bits of Target into %g1
575 BuildMI(V9::ORi, 3).addReg(g1).addSImm(Target & 0x03ff).addReg(g1),
576 // jmpl %g1, %g0, %o7 ;; indirect call on %g1
577 BuildMI(V9::JMPLRETr, 3).addReg(g1).addReg(g0).addReg(o7),
582 for (unsigned i=0, e=sizeof(BinaryCode)/sizeof(BinaryCode[0]); i!=e; ++i) {
583 // This is where we save the return address in the LazyResolverMap!!
584 if (i == 6 && F != 0) { // Do this right before the JMPL
585 uint64_t CurrPC = MCE.getCurrentPCValue();
586 TheJITResolver->addFunctionReference(CurrPC, F);
587 // Remember that this is a far call, to subtract appropriate offset later
588 TheJITResolver->addCallFlavor(CurrPC, JITResolver::FarCall);
591 emitWord(getBinaryCodeForInstr(*BinaryCode[i]));
592 delete BinaryCode[i];
596 void SparcV9JITInfo::replaceMachineCodeForFunction (void *Old, void *New) {
597 assert (TheJITResolver &&
598 "Can only call replaceMachineCodeForFunction from within JIT");
599 uint64_t Target = (uint64_t)(intptr_t)New;
600 uint64_t CodeBegin = (uint64_t)(intptr_t)Old;
601 TheJITResolver->insertJumpAtAddr(Target, CodeBegin);
604 int64_t SparcV9CodeEmitter::getMachineOpValue(MachineInstr &MI,
605 MachineOperand &MO) {
606 int64_t rv = 0; // Return value; defaults to 0 for unhandled cases
607 // or things that get fixed up later by the JIT.
608 if (MO.isPCRelativeDisp()) {
609 DEBUG(std::cerr << "PCRelativeDisp: ");
610 Value *V = MO.getVRegValue();
611 if (BasicBlock *BB = dyn_cast<BasicBlock>(V)) {
612 DEBUG(std::cerr << "Saving reference to BB (VReg)\n");
613 unsigned* CurrPC = (unsigned*)(intptr_t)MCE.getCurrentPCValue();
614 BBRefs.push_back(std::make_pair(BB, std::make_pair(CurrPC, &MI)));
615 } else if (const ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
616 // The real target of the branch is CI = PC + (rv * 4)
617 // So undo that: give the instruction (CI - PC) / 4
618 rv = (CI->getRawValue() - MCE.getCurrentPCValue()) / 4;
619 } else if (GlobalValue *GV = dyn_cast<GlobalValue>(V)) {
620 // same as MO.isGlobalAddress()
621 DEBUG(std::cerr << "GlobalValue: ");
622 // external function calls, etc.?
623 if (Function *F = dyn_cast<Function>(GV)) {
624 DEBUG(std::cerr << "Function: ");
625 // NOTE: This results in stubs being generated even for
626 // external, native functions, which is not optimal. See PR103.
627 rv = (int64_t)MCE.getGlobalValueAddress(F);
629 DEBUG(std::cerr << "not yet generated\n");
630 // Function has not yet been code generated!
631 TheJITResolver->addFunctionReference(MCE.getCurrentPCValue(), F);
632 // Delayed resolution...
633 rv = TheJITResolver->getLazyResolver(F);
635 DEBUG(std::cerr << "already generated: 0x" << std::hex << rv << "\n");
638 rv = (int64_t)MCE.getGlobalValueAddress(GV);
639 DEBUG(std::cerr << "Global addr: 0x" << std::hex << rv << "\n");
641 // The real target of the call is Addr = PC + (rv * 4)
642 // So undo that: give the instruction (Addr - PC) / 4
643 if (MI.getOpcode() == V9::CALL) {
644 int64_t CurrPC = MCE.getCurrentPCValue();
645 DEBUG(std::cerr << "rv addr: 0x" << std::hex << rv << "\n"
646 << "curr PC: 0x" << std::hex << CurrPC << "\n");
647 int64_t CallInstTarget = (rv - CurrPC) >> 2;
648 if (CallInstTarget >= (1<<29) || CallInstTarget <= -(1<<29)) {
649 DEBUG(std::cerr << "Making far call!\n");
650 // address is out of bounds for the 30-bit call,
651 // make an indirect jump-and-link
653 // this invalidates the instruction so that the call with an incorrect
654 // address will not be emitted
657 // The call fits into 30 bits, so just return the corrected address
660 DEBUG(std::cerr << "returning addr: 0x" << rv << "\n");
663 std::cerr << "ERROR: PC relative disp unhandled:" << MO << "\n";
666 } else if (MO.isRegister() || MO.getType() == MachineOperand::MO_CCRegister)
668 // This is necessary because the SparcV9 backend doesn't actually lay out
669 // registers in the real fashion -- it skips those that it chooses not to
670 // allocate, i.e. those that are the FP, SP, etc.
671 unsigned fakeReg = MO.getReg();
672 unsigned realRegByClass = getRealRegNum(fakeReg, MI);
673 DEBUG(std::cerr << MO << ": Reg[" << std::dec << fakeReg << "] => "
674 << realRegByClass << " (LLC: "
675 << TM.getRegInfo()->getUnifiedRegName(fakeReg) << ")\n");
677 } else if (MO.isImmediate()) {
678 rv = MO.getImmedValue();
679 DEBUG(std::cerr << "immed: " << rv << "\n");
680 } else if (MO.isGlobalAddress()) {
681 DEBUG(std::cerr << "GlobalAddress: not PC-relative\n");
683 (intptr_t)getGlobalAddress(cast<GlobalValue>(MO.getVRegValue()),
684 MI, MO.isPCRelative());
685 } else if (MO.isMachineBasicBlock()) {
686 // Duplicate code of the above case for VirtualRegister, BasicBlock...
687 // It should really hit this case, but SparcV9 backend uses VRegs instead
688 DEBUG(std::cerr << "Saving reference to MBB\n");
689 const BasicBlock *BB = MO.getMachineBasicBlock()->getBasicBlock();
690 unsigned* CurrPC = (unsigned*)(intptr_t)MCE.getCurrentPCValue();
691 BBRefs.push_back(std::make_pair(BB, std::make_pair(CurrPC, &MI)));
692 } else if (MO.isExternalSymbol()) {
693 // SparcV9 backend doesn't generate this (yet...)
694 std::cerr << "ERROR: External symbol unhandled: " << MO << "\n";
696 } else if (MO.isFrameIndex()) {
697 // SparcV9 backend doesn't generate this (yet...)
698 int FrameIndex = MO.getFrameIndex();
699 std::cerr << "ERROR: Frame index unhandled.\n";
701 } else if (MO.isConstantPoolIndex()) {
702 unsigned Index = MO.getConstantPoolIndex();
703 rv = MCE.getConstantPoolEntryAddress(Index);
705 std::cerr << "ERROR: Unknown type of MachineOperand: " << MO << "\n";
709 // Finally, deal with the various bitfield-extracting functions that
710 // are used in SPARC assembly. (Some of these make no sense in combination
711 // with some of the above; we'll trust that the instruction selector
712 // will not produce nonsense, and not check for valid combinations here.)
713 if (MO.isLoBits32()) { // %lo(val) == %lo() in SparcV9 ABI doc
715 } else if (MO.isHiBits32()) { // %lm(val) == %hi() in SparcV9 ABI doc
716 return (rv >> 10) & 0x03fffff;
717 } else if (MO.isLoBits64()) { // %hm(val) == %ulo() in SparcV9 ABI doc
718 return (rv >> 32) & 0x03ff;
719 } else if (MO.isHiBits64()) { // %hh(val) == %uhi() in SparcV9 ABI doc
721 } else { // (unadorned) val
726 unsigned SparcV9CodeEmitter::getValueBit(int64_t Val, unsigned bit) {
731 bool SparcV9CodeEmitter::runOnMachineFunction(MachineFunction &MF) {
732 MCE.startFunction(MF);
733 DEBUG(std::cerr << "Starting function " << MF.getFunction()->getName()
734 << ", address: " << "0x" << std::hex
735 << (long)MCE.getCurrentPCValue() << "\n");
737 MCE.emitConstantPool(MF.getConstantPool());
738 for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I)
740 MCE.finishFunction(MF);
742 DEBUG(std::cerr << "Finishing fn " << MF.getFunction()->getName() << "\n");
744 // Resolve branches to BasicBlocks for the entire function
745 for (unsigned i = 0, e = BBRefs.size(); i != e; ++i) {
746 long Location = BBLocations[BBRefs[i].first];
747 unsigned *Ref = BBRefs[i].second.first;
748 MachineInstr *MI = BBRefs[i].second.second;
749 DEBUG(std::cerr << "Fixup @ " << std::hex << Ref << " to 0x" << Location
750 << " in instr: " << std::dec << *MI);
751 for (unsigned ii = 0, ee = MI->getNumOperands(); ii != ee; ++ii) {
752 MachineOperand &op = MI->getOperand(ii);
753 if (op.isPCRelativeDisp()) {
754 // the instruction's branch target is made such that it branches to
755 // PC + (branchTarget * 4), so undo that arithmetic here:
756 // Location is the target of the branch
757 // Ref is the location of the instruction, and hence the PC
758 int64_t branchTarget = (Location - (long)Ref) >> 2;
760 bool loBits32=false, hiBits32=false, loBits64=false, hiBits64=false;
761 if (op.isLoBits32()) { loBits32=true; }
762 if (op.isHiBits32()) { hiBits32=true; }
763 if (op.isLoBits64()) { loBits64=true; }
764 if (op.isHiBits64()) { hiBits64=true; }
765 MI->SetMachineOperandConst(ii, MachineOperand::MO_SignExtendedImmed,
767 if (loBits32) { MI->getOperand(ii).markLo32(); }
768 else if (hiBits32) { MI->getOperand(ii).markHi32(); }
769 else if (loBits64) { MI->getOperand(ii).markLo64(); }
770 else if (hiBits64) { MI->getOperand(ii).markHi64(); }
771 DEBUG(std::cerr << "Rewrote BB ref: ");
772 unsigned fixedInstr = SparcV9CodeEmitter::getBinaryCodeForInstr(*MI);
773 MCE.emitWordAt (fixedInstr, Ref);
784 void SparcV9CodeEmitter::emitBasicBlock(MachineBasicBlock &MBB) {
785 currBB = MBB.getBasicBlock();
786 BBLocations[currBB] = MCE.getCurrentPCValue();
787 for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); I != E; ++I){
788 unsigned binCode = getBinaryCodeForInstr(*I);
789 if (binCode == (1 << 30)) {
790 // this is an invalid call: the addr is out of bounds. that means a code
791 // sequence has already been emitted, and this is a no-op
792 DEBUG(std::cerr << "Call suppressed: already emitted far call.\n");
799 void* SparcV9CodeEmitter::getGlobalAddress(GlobalValue *V, MachineInstr &MI,
802 if (isPCRelative) { // must be a call, this is a major hack!
803 // Try looking up the function to see if it is already compiled!
804 if (void *Addr = (void*)(intptr_t)MCE.getGlobalValueAddress(V)) {
805 intptr_t CurByte = MCE.getCurrentPCValue();
806 // The real target of the call is Addr = PC + (target * 4)
807 // CurByte is the PC, Addr we just received
808 return (void*) (((long)Addr - (long)CurByte) >> 2);
810 if (Function *F = dyn_cast<Function>(V)) {
811 // Function has not yet been code generated!
812 TheJITResolver->addFunctionReference(MCE.getCurrentPCValue(),
814 // Delayed resolution...
816 (void*)(intptr_t)TheJITResolver->getLazyResolver(cast<Function>(V));
818 std::cerr << "Unhandled global: " << *V << "\n";
823 return (void*)(intptr_t)MCE.getGlobalValueAddress(V);
827 #include "SparcV9CodeEmitter.inc"
829 } // End llvm namespace