1 //===-- SparcV9CodeEmitter.cpp --------------------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // SPARC-specific backend for emitting machine code to memory.
12 // This module also contains the code for lazily resolving the targets
13 // of call instructions, including the callback used to redirect calls
14 // to functions for which the code has not yet been generated into the
17 // This file #includes SparcV9CodeEmitter.inc, which contains the code
18 // for getBinaryCodeForInstr(), a method that converts a MachineInstr
19 // into the corresponding binary machine code word.
21 //===----------------------------------------------------------------------===//
23 #include "llvm/Constants.h"
24 #include "llvm/Function.h"
25 #include "llvm/GlobalVariable.h"
26 #include "llvm/PassManager.h"
27 #include "llvm/CodeGen/MachineCodeEmitter.h"
28 #include "llvm/CodeGen/MachineConstantPool.h"
29 #include "llvm/CodeGen/MachineFunctionPass.h"
30 #include "llvm/CodeGen/MachineInstr.h"
31 #include "llvm/Target/TargetMachine.h"
32 #include "llvm/Target/TargetData.h"
33 #include "llvm/Support/Debug.h"
34 #include "SparcV9Internals.h"
35 #include "SparcV9TargetMachine.h"
36 #include "SparcV9RegInfo.h"
37 #include "SparcV9CodeEmitter.h"
38 #include "SparcV9Relocations.h"
39 #include "MachineFunctionInfo.h"
42 bool SparcV9TargetMachine::addPassesToEmitMachineCode(FunctionPassManager &PM,
43 MachineCodeEmitter &MCE) {
44 PM.add(new SparcV9CodeEmitter(*this, MCE));
45 PM.add(createSparcV9MachineCodeDestructionPass());
49 SparcV9CodeEmitter::SparcV9CodeEmitter(TargetMachine &tm,
50 MachineCodeEmitter &M): TM(tm), MCE(M) {}
52 void SparcV9CodeEmitter::emitWord(unsigned Val) {
57 SparcV9CodeEmitter::getRealRegNum(unsigned fakeReg,
59 const SparcV9RegInfo &RI = *TM.getRegInfo();
60 unsigned regClass, regType = RI.getRegType(fakeReg);
61 // At least map fakeReg into its class
62 fakeReg = RI.getClassRegNum(fakeReg, regClass);
65 case SparcV9RegInfo::IntRegClassID: {
66 // SparcV9 manual, p31
67 static const unsigned IntRegMap[] = {
68 // "o0", "o1", "o2", "o3", "o4", "o5", "o7",
69 8, 9, 10, 11, 12, 13, 15,
70 // "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
71 16, 17, 18, 19, 20, 21, 22, 23,
72 // "i0", "i1", "i2", "i3", "i4", "i5", "i6", "i7",
73 24, 25, 26, 27, 28, 29, 30, 31,
74 // "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
75 0, 1, 2, 3, 4, 5, 6, 7,
80 return IntRegMap[fakeReg];
83 case SparcV9RegInfo::FloatRegClassID: {
84 DEBUG(std::cerr << "FP reg: " << fakeReg << "\n");
85 if (regType == SparcV9RegInfo::FPSingleRegType) {
86 // only numbered 0-31, hence can already fit into 5 bits (and 6)
87 DEBUG(std::cerr << "FP single reg, returning: " << fakeReg << "\n");
88 } else if (regType == SparcV9RegInfo::FPDoubleRegType) {
89 // FIXME: This assumes that we only have 5-bit register fields!
90 // From SparcV9 Manual, page 40.
91 // The bit layout becomes: b[4], b[3], b[2], b[1], b[5]
92 fakeReg |= (fakeReg >> 5) & 1;
94 DEBUG(std::cerr << "FP double reg, returning: " << fakeReg << "\n");
98 case SparcV9RegInfo::IntCCRegClassID: {
100 static const unsigned IntCCReg[] = { 6, 4, 2 };
102 assert(fakeReg < sizeof(IntCCReg)/sizeof(IntCCReg[0])
103 && "CC register out of bounds for IntCCReg map");
104 DEBUG(std::cerr << "IntCC reg: " << IntCCReg[fakeReg] << "\n");
105 return IntCCReg[fakeReg];
107 case SparcV9RegInfo::FloatCCRegClassID: {
108 /* These are laid out %fcc0 - %fcc3 => 0 - 3, so are correct */
109 DEBUG(std::cerr << "FP CC reg: " << fakeReg << "\n");
112 case SparcV9RegInfo::SpecialRegClassID: {
113 // Currently only "special" reg is %fsr, which is encoded as 1 in
114 // instructions and 0 in SparcV9SpecialRegClass.
115 static const unsigned SpecialReg[] = { 1 };
116 assert(fakeReg < sizeof(SpecialReg)/sizeof(SpecialReg[0])
117 && "Special register out of bounds for SpecialReg map");
118 DEBUG(std::cerr << "Special reg: " << SpecialReg[fakeReg] << "\n");
119 return SpecialReg[fakeReg];
122 assert(0 && "Invalid unified register number in getRealRegNum");
129 int64_t SparcV9CodeEmitter::getMachineOpValue(MachineInstr &MI,
130 MachineOperand &MO) {
131 int64_t rv = 0; // Return value; defaults to 0 for unhandled cases
132 // or things that get fixed up later by the JIT.
133 if (MO.isPCRelativeDisp() || MO.isGlobalAddress()) {
134 DEBUG(std::cerr << "PCRelativeDisp: ");
135 Value *V = MO.getVRegValue();
136 if (BasicBlock *BB = dyn_cast<BasicBlock>(V)) {
137 DEBUG(std::cerr << "Saving reference to BB (VReg)\n");
138 unsigned* CurrPC = (unsigned*)(intptr_t)MCE.getCurrentPCValue();
139 BBRefs.push_back(std::make_pair(BB, std::make_pair(CurrPC, &MI)));
140 } else if (const ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
141 // The real target of the branch is CI = PC + (rv * 4)
142 // So undo that: give the instruction (CI - PC) / 4
143 rv = (CI->getRawValue() - MCE.getCurrentPCValue()) / 4;
144 } else if (GlobalValue *GV = dyn_cast<GlobalValue>(V)) {
146 bool isLocal = false;
147 if (MI.getOpcode() == V9::CALL) {
148 Reloc = V9::reloc_pcrel_call;
149 #if 0 // FIXME: No need to emit stubs for internal functions.
150 if (!GV->hasExternalLinkage() && isa<Function>(GV))
153 } else if (MI.getOpcode() == V9::SETHI) {
155 Reloc = V9::reloc_sethi_hh;
156 else if (MO.isHiBits32())
157 Reloc = V9::reloc_sethi_lm;
159 assert(0 && "Unknown relocation!");
160 } else if (MI.getOpcode() == V9::ORi) {
162 Reloc = V9::reloc_or_lo;
163 else if (MO.isLoBits64())
164 Reloc = V9::reloc_or_hm;
166 assert(0 && "Unknown relocation!");
168 assert(0 && "Unknown relocation!");
171 MCE.addRelocation(MachineRelocation(MCE.getCurrentPCOffset(), Reloc, GV,
175 std::cerr << "ERROR: PC relative disp unhandled:" << MO << "\n";
178 } else if (MO.isRegister() || MO.getType() == MachineOperand::MO_CCRegister)
180 // This is necessary because the SparcV9 backend doesn't actually lay out
181 // registers in the real fashion -- it skips those that it chooses not to
182 // allocate, i.e. those that are the FP, SP, etc.
183 unsigned fakeReg = MO.getReg();
184 unsigned realRegByClass = getRealRegNum(fakeReg, MI);
185 DEBUG(std::cerr << MO << ": Reg[" << std::dec << fakeReg << "] => "
186 << realRegByClass << " (LLC: "
187 << TM.getRegInfo()->getUnifiedRegName(fakeReg) << ")\n");
189 } else if (MO.isImmediate()) {
190 rv = MO.getImmedValue();
191 DEBUG(std::cerr << "immed: " << rv << "\n");
192 } else if (MO.isMachineBasicBlock()) {
193 // Duplicate code of the above case for VirtualRegister, BasicBlock...
194 // It should really hit this case, but SparcV9 backend uses VRegs instead
195 DEBUG(std::cerr << "Saving reference to MBB\n");
196 const BasicBlock *BB = MO.getMachineBasicBlock()->getBasicBlock();
197 unsigned* CurrPC = (unsigned*)(intptr_t)MCE.getCurrentPCValue();
198 BBRefs.push_back(std::make_pair(BB, std::make_pair(CurrPC, &MI)));
199 } else if (MO.isExternalSymbol()) {
200 // SparcV9 backend doesn't generate this (yet...)
201 std::cerr << "ERROR: External symbol unhandled: " << MO << "\n";
203 } else if (MO.isFrameIndex()) {
204 // SparcV9 backend doesn't generate this (yet...)
205 int FrameIndex = MO.getFrameIndex();
206 std::cerr << "ERROR: Frame index unhandled.\n";
208 } else if (MO.isConstantPoolIndex()) {
209 unsigned Index = MO.getConstantPoolIndex();
210 rv = MCE.getConstantPoolEntryAddress(Index);
212 std::cerr << "ERROR: Unknown type of MachineOperand: " << MO << "\n";
216 // Finally, deal with the various bitfield-extracting functions that
217 // are used in SPARC assembly. (Some of these make no sense in combination
218 // with some of the above; we'll trust that the instruction selector
219 // will not produce nonsense, and not check for valid combinations here.)
220 if (MO.isLoBits32()) { // %lo(val) == %lo() in SparcV9 ABI doc
222 } else if (MO.isHiBits32()) { // %lm(val) == %hi() in SparcV9 ABI doc
223 return (rv >> 10) & 0x03fffff;
224 } else if (MO.isLoBits64()) { // %hm(val) == %ulo() in SparcV9 ABI doc
225 return (rv >> 32) & 0x03ff;
226 } else if (MO.isHiBits64()) { // %hh(val) == %uhi() in SparcV9 ABI doc
228 } else { // (unadorned) val
233 unsigned SparcV9CodeEmitter::getValueBit(int64_t Val, unsigned bit) {
238 bool SparcV9CodeEmitter::runOnMachineFunction(MachineFunction &MF) {
239 MCE.startFunction(MF);
240 DEBUG(std::cerr << "Starting function " << MF.getFunction()->getName()
241 << ", address: " << "0x" << std::hex
242 << (long)MCE.getCurrentPCValue() << "\n");
244 MCE.emitConstantPool(MF.getConstantPool());
245 for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I)
247 MCE.finishFunction(MF);
249 DEBUG(std::cerr << "Finishing fn " << MF.getFunction()->getName() << "\n");
251 // Resolve branches to BasicBlocks for the entire function
252 for (unsigned i = 0, e = BBRefs.size(); i != e; ++i) {
253 long Location = BBLocations[BBRefs[i].first];
254 unsigned *Ref = BBRefs[i].second.first;
255 MachineInstr *MI = BBRefs[i].second.second;
256 DEBUG(std::cerr << "Fixup @ " << std::hex << Ref << " to 0x" << Location
257 << " in instr: " << std::dec << *MI);
258 for (unsigned ii = 0, ee = MI->getNumOperands(); ii != ee; ++ii) {
259 MachineOperand &op = MI->getOperand(ii);
260 if (op.isPCRelativeDisp()) {
261 // the instruction's branch target is made such that it branches to
262 // PC + (branchTarget * 4), so undo that arithmetic here:
263 // Location is the target of the branch
264 // Ref is the location of the instruction, and hence the PC
265 int64_t branchTarget = (Location - (long)Ref) >> 2;
267 bool loBits32=false, hiBits32=false, loBits64=false, hiBits64=false;
268 if (op.isLoBits32()) { loBits32=true; }
269 if (op.isHiBits32()) { hiBits32=true; }
270 if (op.isLoBits64()) { loBits64=true; }
271 if (op.isHiBits64()) { hiBits64=true; }
272 MI->SetMachineOperandConst(ii, MachineOperand::MO_SignExtendedImmed,
274 if (loBits32) { MI->getOperand(ii).markLo32(); }
275 else if (hiBits32) { MI->getOperand(ii).markHi32(); }
276 else if (loBits64) { MI->getOperand(ii).markLo64(); }
277 else if (hiBits64) { MI->getOperand(ii).markHi64(); }
278 DEBUG(std::cerr << "Rewrote BB ref: ");
279 unsigned fixedInstr = SparcV9CodeEmitter::getBinaryCodeForInstr(*MI);
280 MCE.emitWordAt (fixedInstr, Ref);
291 void SparcV9CodeEmitter::emitBasicBlock(MachineBasicBlock &MBB) {
292 currBB = MBB.getBasicBlock();
293 BBLocations[currBB] = MCE.getCurrentPCValue();
294 for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); I != E; ++I)
295 if (I->getOpcode() != V9::RDCCR) {
296 emitWord(getBinaryCodeForInstr(*I));
298 // FIXME: The tblgen produced code emitter cannot deal with the fact that
299 // machine operand #0 of the RDCCR instruction should be ignored. This is
300 // really a bug in the representation of the RDCCR instruction (which has
301 // no need to explicitly represent the CCR dest), but we hack around it
303 unsigned RegNo = getMachineOpValue(*I, I->getOperand(1));
305 emitWord((RegNo << 25) | 2168487936U);
311 #include "SparcV9CodeEmitter.inc"
312 } // End llvm namespace