1 //===-- SparcInstrInfo.cpp ------------------------------------------------===//
3 //===----------------------------------------------------------------------===//
5 #include "SparcInternals.h"
6 #include "SparcInstrSelectionSupport.h"
7 #include "llvm/CodeGen/InstrSelection.h"
8 #include "llvm/CodeGen/InstrSelectionSupport.h"
9 #include "llvm/CodeGen/MachineFunction.h"
10 #include "llvm/CodeGen/MachineCodeForInstruction.h"
11 #include "llvm/Function.h"
12 #include "llvm/Constants.h"
13 #include "llvm/DerivedTypes.h"
17 static const uint32_t MAXLO = (1 << 10) - 1; // set bits set by %lo(*)
18 static const uint32_t MAXSIMM = (1 << 12) - 1; // set bits in simm13 field of OR
21 //----------------------------------------------------------------------------
22 // Function: CreateSETUWConst
24 // Set a 32-bit unsigned constant in the register `dest', using
25 // SETHI, OR in the worst case. This function correctly emulates
26 // the SETUW pseudo-op for SPARC v9 (if argument isSigned == false).
28 // The isSigned=true case is used to implement SETSW without duplicating code.
30 // Optimize some common cases:
31 // (1) Small value that fits in simm13 field of OR: don't need SETHI.
32 // (2) isSigned = true and C is a small negative signed value, i.e.,
33 // high bits are 1, and the remaining bits fit in simm13(OR).
34 //----------------------------------------------------------------------------
37 CreateSETUWConst(const TargetMachine& target, uint32_t C,
38 Instruction* dest, vector<MachineInstr*>& mvec,
39 bool isSigned = false)
41 MachineInstr *miSETHI = NULL, *miOR = NULL;
43 // In order to get efficient code, we should not generate the SETHI if
44 // all high bits are 1 (i.e., this is a small signed value that fits in
45 // the simm13 field of OR). So we check for and handle that case specially.
46 // NOTE: The value C = 0x80000000 is bad: sC < 0 *and* -sC < 0.
47 // In fact, sC == -sC, so we have to check for this explicitly.
48 int32_t sC = (int32_t) C;
49 bool smallNegValue =isSigned && sC < 0 && sC != -sC && -sC < (int32_t)MAXSIMM;
51 // Set the high 22 bits in dest if non-zero and simm13 field of OR not enough
52 if (!smallNegValue && (C & ~MAXLO) && C > MAXSIMM)
54 miSETHI = Create2OperandInstr_UImmed(SETHI, C, dest);
55 miSETHI->setOperandHi32(0);
56 mvec.push_back(miSETHI);
59 // Set the low 10 or 12 bits in dest. This is necessary if no SETHI
60 // was generated, or if the low 10 bits are non-zero.
61 if (miSETHI==NULL || C & MAXLO)
64 { // unsigned value with high-order bits set using SETHI
65 miOR = Create3OperandInstr_UImmed(OR, dest, C, dest);
66 miOR->setOperandLo32(1);
69 { // unsigned or small signed value that fits in simm13 field of OR
70 assert(smallNegValue || (C & ~MAXSIMM) == 0);
71 miOR = new MachineInstr(OR);
72 miOR->SetMachineOperandReg(0, target.getRegInfo().getZeroRegNum());
73 miOR->SetMachineOperandConst(1, MachineOperand::MO_SignExtendedImmed,
75 miOR->SetMachineOperandVal(2,MachineOperand::MO_VirtualRegister,dest);
80 assert((miSETHI || miOR) && "Oops, no code was generated!");
84 //----------------------------------------------------------------------------
85 // Function: CreateSETSWConst
87 // Set a 32-bit signed constant in the register `dest', with sign-extension
88 // to 64 bits. This uses SETHI, OR, SRA in the worst case.
89 // This function correctly emulates the SETSW pseudo-op for SPARC v9.
91 // Optimize the same cases as SETUWConst, plus:
92 // (1) SRA is not needed for positive or small negative values.
93 //----------------------------------------------------------------------------
96 CreateSETSWConst(const TargetMachine& target, int32_t C,
97 Instruction* dest, vector<MachineInstr*>& mvec)
101 // Set the low 32 bits of dest
102 CreateSETUWConst(target, (uint32_t) C, dest, mvec, /*isSigned*/true);
104 // Sign-extend to the high 32 bits if needed
105 if (C < 0 && (-C) > (int32_t) MAXSIMM)
107 MI = Create3OperandInstr_UImmed(SRA, dest, 0, dest);
113 //----------------------------------------------------------------------------
114 // Function: CreateSETXConst
116 // Set a 64-bit signed or unsigned constant in the register `dest'.
117 // Use SETUWConst for each 32 bit word, plus a left-shift-by-32 in between.
118 // This function correctly emulates the SETX pseudo-op for SPARC v9.
120 // Optimize the same cases as SETUWConst for each 32 bit word.
121 //----------------------------------------------------------------------------
124 CreateSETXConst(const TargetMachine& target, uint64_t C,
125 Instruction* tmpReg, Instruction* dest,
126 vector<MachineInstr*>& mvec)
128 assert(C > (unsigned int) ~0 && "Use SETUW/SETSW for 32-bit values!");
132 // Code to set the upper 32 bits of the value in register `tmpReg'
133 CreateSETUWConst(target, (C >> 32), tmpReg, mvec);
135 // Shift tmpReg left by 32 bits
136 MI = Create3OperandInstr_UImmed(SLLX, tmpReg, 32, tmpReg);
139 // Code to set the low 32 bits of the value in register `dest'
140 CreateSETUWConst(target, C, dest, mvec);
142 // dest = OR(tmpReg, dest)
143 MI = Create3OperandInstr(OR, dest, tmpReg, dest);
148 //----------------------------------------------------------------------------
149 // Function: CreateSETUWLabel
151 // Set a 32-bit constant (given by a symbolic label) in the register `dest'.
152 //----------------------------------------------------------------------------
155 CreateSETUWLabel(const TargetMachine& target, Value* val,
156 Instruction* dest, vector<MachineInstr*>& mvec)
160 // Set the high 22 bits in dest
161 MI = Create2OperandInstr(SETHI, val, dest);
162 MI->setOperandHi32(0);
165 // Set the low 10 bits in dest
166 MI = Create3OperandInstr(OR, dest, val, dest);
167 MI->setOperandLo32(1);
172 //----------------------------------------------------------------------------
173 // Function: CreateSETXLabel
175 // Set a 64-bit constant (given by a symbolic label) in the register `dest'.
176 //----------------------------------------------------------------------------
179 CreateSETXLabel(const TargetMachine& target,
180 Value* val, Instruction* tmpReg, Instruction* dest,
181 vector<MachineInstr*>& mvec)
183 assert(isa<Constant>(val) || isa<GlobalValue>(val) &&
184 "I only know about constant values and global addresses");
188 MI = Create2OperandInstr_Addr(SETHI, val, tmpReg);
189 MI->setOperandHi64(0);
192 MI = Create3OperandInstr_Addr(OR, tmpReg, val, tmpReg);
193 MI->setOperandLo64(1);
196 MI = Create3OperandInstr_UImmed(SLLX, tmpReg, 32, tmpReg);
199 MI = Create2OperandInstr_Addr(SETHI, val, dest);
200 MI->setOperandHi32(0);
203 MI = Create3OperandInstr(OR, dest, tmpReg, dest);
206 MI = Create3OperandInstr_Addr(OR, dest, val, dest);
207 MI->setOperandLo32(1);
212 //----------------------------------------------------------------------------
213 // Function: CreateUIntSetInstruction
215 // Create code to Set an unsigned constant in the register `dest'.
216 // Uses CreateSETUWConst, CreateSETSWConst or CreateSETXConst as needed.
217 // CreateSETSWConst is an optimization for the case that the unsigned value
218 // has all ones in the 33 high bits (so that sign-extension sets them all).
219 //----------------------------------------------------------------------------
222 CreateUIntSetInstruction(const TargetMachine& target,
223 uint64_t C, Instruction* dest,
224 std::vector<MachineInstr*>& mvec,
225 MachineCodeForInstruction& mcfi)
227 static const uint64_t lo32 = (uint32_t) ~0;
228 if (C <= lo32) // High 32 bits are 0. Set low 32 bits.
229 CreateSETUWConst(target, (uint32_t) C, dest, mvec);
230 else if ((C & ~lo32) == ~lo32 && (C & (1 << 31)))
231 { // All high 33 (not 32) bits are 1s: sign-extension will take care
232 // of high 32 bits, so use the sequence for signed int
233 CreateSETSWConst(target, (int32_t) C, dest, mvec);
236 { // C does not fit in 32 bits
237 TmpInstruction* tmpReg = new TmpInstruction(Type::IntTy);
238 mcfi.addTemp(tmpReg);
239 CreateSETXConst(target, C, tmpReg, dest, mvec);
244 //----------------------------------------------------------------------------
245 // Function: CreateIntSetInstruction
247 // Create code to Set a signed constant in the register `dest'.
248 // Really the same as CreateUIntSetInstruction.
249 //----------------------------------------------------------------------------
252 CreateIntSetInstruction(const TargetMachine& target,
253 int64_t C, Instruction* dest,
254 std::vector<MachineInstr*>& mvec,
255 MachineCodeForInstruction& mcfi)
257 CreateUIntSetInstruction(target, (uint64_t) C, dest, mvec, mcfi);
261 //---------------------------------------------------------------------------
262 // Create a table of LLVM opcode -> max. immediate constant likely to
263 // be usable for that operation.
264 //---------------------------------------------------------------------------
266 // Entry == 0 ==> no immediate constant field exists at all.
267 // Entry > 0 ==> abs(immediate constant) <= Entry
269 vector<int> MaxConstantsTable(Instruction::OtherOpsEnd);
272 MaxConstantForInstr(unsigned llvmOpCode)
274 int modelOpCode = -1;
276 if (llvmOpCode >= Instruction::BinaryOpsBegin &&
277 llvmOpCode < Instruction::BinaryOpsEnd)
281 case Instruction::Ret: modelOpCode = JMPLCALL; break;
283 case Instruction::Malloc:
284 case Instruction::Alloca:
285 case Instruction::GetElementPtr:
286 case Instruction::PHINode:
287 case Instruction::Cast:
288 case Instruction::Call: modelOpCode = ADD; break;
290 case Instruction::Shl:
291 case Instruction::Shr: modelOpCode = SLLX; break;
296 return (modelOpCode < 0)? 0: SparcMachineInstrDesc[modelOpCode].maxImmedConst;
300 InitializeMaxConstantsTable()
303 assert(MaxConstantsTable.size() == Instruction::OtherOpsEnd &&
304 "assignments below will be illegal!");
305 for (op = Instruction::TermOpsBegin; op < Instruction::TermOpsEnd; ++op)
306 MaxConstantsTable[op] = MaxConstantForInstr(op);
307 for (op = Instruction::BinaryOpsBegin; op < Instruction::BinaryOpsEnd; ++op)
308 MaxConstantsTable[op] = MaxConstantForInstr(op);
309 for (op = Instruction::MemoryOpsBegin; op < Instruction::MemoryOpsEnd; ++op)
310 MaxConstantsTable[op] = MaxConstantForInstr(op);
311 for (op = Instruction::OtherOpsBegin; op < Instruction::OtherOpsEnd; ++op)
312 MaxConstantsTable[op] = MaxConstantForInstr(op);
316 //---------------------------------------------------------------------------
317 // class UltraSparcInstrInfo
320 // Information about individual instructions.
321 // Most information is stored in the SparcMachineInstrDesc array above.
322 // Other information is computed on demand, and most such functions
323 // default to member functions in base class MachineInstrInfo.
324 //---------------------------------------------------------------------------
327 UltraSparcInstrInfo::UltraSparcInstrInfo()
328 : MachineInstrInfo(SparcMachineInstrDesc,
329 /*descSize = */ NUM_TOTAL_OPCODES,
330 /*numRealOpCodes = */ NUM_REAL_OPCODES)
332 InitializeMaxConstantsTable();
336 UltraSparcInstrInfo::ConstantMayNotFitInImmedField(const Constant* CV,
337 const Instruction* I) const
339 if (I->getOpcode() >= MaxConstantsTable.size()) // user-defined op (or bug!)
342 if (isa<ConstantPointerNull>(CV)) // can always use %g0
345 if (const ConstantUInt* U = dyn_cast<ConstantUInt>(CV))
346 /* Large unsigned longs may really just be small negative signed longs */
347 return (labs((int64_t) U->getValue()) > MaxConstantsTable[I->getOpcode()]);
349 if (const ConstantSInt* S = dyn_cast<ConstantSInt>(CV))
350 return (labs(S->getValue()) > MaxConstantsTable[I->getOpcode()]);
352 if (isa<ConstantBool>(CV))
353 return (1 > MaxConstantsTable[I->getOpcode()]);
359 // Create an instruction sequence to put the constant `val' into
360 // the virtual register `dest'. `val' may be a Constant or a
361 // GlobalValue, viz., the constant address of a global variable or function.
362 // The generated instructions are returned in `mvec'.
363 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
364 // Any stack space required is allocated via MachineFunction.
367 UltraSparcInstrInfo::CreateCodeToLoadConst(const TargetMachine& target,
371 vector<MachineInstr*>& mvec,
372 MachineCodeForInstruction& mcfi) const
374 assert(isa<Constant>(val) || isa<GlobalValue>(val) &&
375 "I only know about constant values and global addresses");
377 // Use a "set" instruction for known constants or symbolic constants (labels)
378 // that can go in an integer reg.
379 // We have to use a "load" instruction for all other constants,
380 // in particular, floating point constants.
382 const Type* valType = val->getType();
384 // Unfortunate special case: a ConstantPointerRef is just a
385 // reference to GlobalValue.
386 if (isa<ConstantPointerRef>(val))
387 val = cast<ConstantPointerRef>(val)->getValue();
389 if (isa<GlobalValue>(val))
391 TmpInstruction* tmpReg =
392 new TmpInstruction(PointerType::get(val->getType()), val);
393 mcfi.addTemp(tmpReg);
394 CreateSETXLabel(target, val, tmpReg, dest, mvec);
396 else if (valType->isIntegral())
398 bool isValidConstant;
399 unsigned opSize = target.DataLayout.getTypeSize(val->getType());
400 unsigned destSize = target.DataLayout.getTypeSize(dest->getType());
402 if (! dest->getType()->isSigned())
404 uint64_t C = GetConstantValueAsUnsignedInt(val, isValidConstant);
405 assert(isValidConstant && "Unrecognized constant");
407 if (opSize > destSize ||
408 (val->getType()->isSigned()
409 && destSize < target.DataLayout.getIntegerRegize()))
410 { // operand is larger than dest,
411 // OR both are equal but smaller than the full register size
412 // AND operand is signed, so it may have extra sign bits:
414 C = C & ((1U << 8*destSize) - 1);
416 CreateUIntSetInstruction(target, C, dest, mvec, mcfi);
420 int64_t C = GetConstantValueAsSignedInt(val, isValidConstant);
421 assert(isValidConstant && "Unrecognized constant");
423 if (opSize > destSize)
424 // operand is larger than dest: mask high bits
425 C = C & ((1U << 8*destSize) - 1);
427 if (opSize > destSize ||
428 (opSize == destSize && !val->getType()->isSigned()))
429 // sign-extend from destSize to 64 bits
430 C = ((C & (1U << (8*destSize - 1)))
431 ? C | ~((1U << 8*destSize) - 1)
434 CreateIntSetInstruction(target, C, dest, mvec, mcfi);
439 // Make an instruction sequence to load the constant, viz:
440 // SETX <addr-of-constant>, tmpReg, addrReg
441 // LOAD /*addr*/ addrReg, /*offset*/ 0, dest
443 // First, create a tmp register to be used by the SETX sequence.
444 TmpInstruction* tmpReg =
445 new TmpInstruction(PointerType::get(val->getType()), val);
446 mcfi.addTemp(tmpReg);
448 // Create another TmpInstruction for the address register
449 TmpInstruction* addrReg =
450 new TmpInstruction(PointerType::get(val->getType()), val);
451 mcfi.addTemp(addrReg);
453 // Put the address (a symbolic name) into a register
454 CreateSETXLabel(target, val, tmpReg, addrReg, mvec);
456 // Generate the load instruction
457 int64_t zeroOffset = 0; // to avoid ambiguity with (Value*) 0
459 Create3OperandInstr_SImmed(ChooseLoadInstruction(val->getType()),
460 addrReg, zeroOffset, dest);
463 // Make sure constant is emitted to constant pool in assembly code.
464 MachineFunction::get(F).addToConstantPool(cast<Constant>(val));
469 // Create an instruction sequence to copy an integer register `val'
470 // to a floating point register `dest' by copying to memory and back.
471 // val must be an integral type. dest must be a Float or Double.
472 // The generated instructions are returned in `mvec'.
473 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
474 // Any stack space required is allocated via MachineFunction.
477 UltraSparcInstrInfo::CreateCodeToCopyIntToFloat(const TargetMachine& target,
481 vector<MachineInstr*>& mvec,
482 MachineCodeForInstruction& mcfi) const
484 assert((val->getType()->isIntegral() || isa<PointerType>(val->getType()))
485 && "Source type must be integral (integer or bool) or pointer");
486 assert(dest->getType()->isFloatingPoint()
487 && "Dest type must be float/double");
489 // Get a stack slot to use for the copy
490 int offset = MachineFunction::get(F).allocateLocalVar(target, val);
492 // Get the size of the source value being copied.
493 size_t srcSize = target.DataLayout.getTypeSize(val->getType());
495 // Store instruction stores `val' to [%fp+offset].
496 // The store and load opCodes are based on the size of the source value.
497 // If the value is smaller than 32 bits, we must sign- or zero-extend it
498 // to 32 bits since the load-float will load 32 bits.
499 // Note that the store instruction is the same for signed and unsigned ints.
500 const Type* storeType = (srcSize <= 4)? Type::IntTy : Type::LongTy;
501 Value* storeVal = val;
502 if (srcSize < target.DataLayout.getTypeSize(Type::FloatTy))
503 { // sign- or zero-extend respectively
504 storeVal = new TmpInstruction(storeType, val);
505 if (val->getType()->isSigned())
506 CreateSignExtensionInstructions(target, F, val, storeVal, 8*srcSize,
509 CreateZeroExtensionInstructions(target, F, val, storeVal, 8*srcSize,
512 MachineInstr* store=new MachineInstr(ChooseStoreInstruction(storeType));
513 store->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister, storeVal);
514 store->SetMachineOperandReg(1, target.getRegInfo().getFramePointer());
515 store->SetMachineOperandConst(2,MachineOperand::MO_SignExtendedImmed,offset);
516 mvec.push_back(store);
518 // Load instruction loads [%fp+offset] to `dest'.
519 // The type of the load opCode is the floating point type that matches the
520 // stored type in size:
521 // On SparcV9: float for int or smaller, double for long.
523 const Type* loadType = (srcSize <= 4)? Type::FloatTy : Type::DoubleTy;
524 MachineInstr* load = new MachineInstr(ChooseLoadInstruction(loadType));
525 load->SetMachineOperandReg(0, target.getRegInfo().getFramePointer());
526 load->SetMachineOperandConst(1, MachineOperand::MO_SignExtendedImmed,offset);
527 load->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister, dest);
528 mvec.push_back(load);
531 // Similarly, create an instruction sequence to copy an FP register
532 // `val' to an integer register `dest' by copying to memory and back.
533 // The generated instructions are returned in `mvec'.
534 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
535 // Any stack space required is allocated via MachineFunction.
538 UltraSparcInstrInfo::CreateCodeToCopyFloatToInt(const TargetMachine& target,
542 vector<MachineInstr*>& mvec,
543 MachineCodeForInstruction& mcfi) const
545 const Type* opTy = val->getType();
546 const Type* destTy = dest->getType();
548 assert(opTy->isFloatingPoint() && "Source type must be float/double");
549 assert((destTy->isIntegral() || isa<PointerType>(destTy))
550 && "Dest type must be integer, bool or pointer");
552 int offset = MachineFunction::get(F).allocateLocalVar(target, val);
554 // Store instruction stores `val' to [%fp+offset].
555 // The store opCode is based only the source value being copied.
557 MachineInstr* store=new MachineInstr(ChooseStoreInstruction(opTy));
558 store->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister, val);
559 store->SetMachineOperandReg(1, target.getRegInfo().getFramePointer());
560 store->SetMachineOperandConst(2,MachineOperand::MO_SignExtendedImmed,offset);
561 mvec.push_back(store);
563 // Load instruction loads [%fp+offset] to `dest'.
564 // The type of the load opCode is the integer type that matches the
565 // source type in size:
566 // On SparcV9: int for float, long for double.
567 // Note that we *must* use signed loads even for unsigned dest types, to
568 // ensure correct sign-extension for UByte, UShort or UInt:
570 const Type* loadTy = (opTy == Type::FloatTy)? Type::IntTy : Type::LongTy;
571 MachineInstr* load = new MachineInstr(ChooseLoadInstruction(loadTy));
572 load->SetMachineOperandReg(0, target.getRegInfo().getFramePointer());
573 load->SetMachineOperandConst(1, MachineOperand::MO_SignExtendedImmed,offset);
574 load->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister, dest);
575 mvec.push_back(load);
579 // Create instruction(s) to copy src to dest, for arbitrary types
580 // The generated instructions are returned in `mvec'.
581 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
582 // Any stack space required is allocated via MachineFunction.
585 UltraSparcInstrInfo::CreateCopyInstructionsByType(const TargetMachine& target,
589 vector<MachineInstr*>& mvec,
590 MachineCodeForInstruction& mcfi) const
592 bool loadConstantToReg = false;
594 const Type* resultType = dest->getType();
596 MachineOpCode opCode = ChooseAddInstructionByType(resultType);
597 if (opCode == INVALID_OPCODE)
599 assert(0 && "Unsupported result type in CreateCopyInstructionsByType()");
603 // if `src' is a constant that doesn't fit in the immed field or if it is
604 // a global variable (i.e., a constant address), generate a load
605 // instruction instead of an add
607 if (isa<Constant>(src))
609 unsigned int machineRegNum;
611 MachineOperand::MachineOperandType opType =
612 ChooseRegOrImmed(src, opCode, target, /*canUseImmed*/ true,
613 machineRegNum, immedValue);
615 if (opType == MachineOperand::MO_VirtualRegister)
616 loadConstantToReg = true;
618 else if (isa<GlobalValue>(src))
619 loadConstantToReg = true;
621 if (loadConstantToReg)
622 { // `src' is constant and cannot fit in immed field for the ADD
623 // Insert instructions to "load" the constant into a register
624 target.getInstrInfo().CreateCodeToLoadConst(target, F, src, dest,
628 { // Create an add-with-0 instruction of the appropriate type.
629 // Make `src' the second operand, in case it is a constant
630 // Use (unsigned long) 0 for a NULL pointer value.
632 const Type* zeroValueType =
633 isa<PointerType>(resultType) ? Type::ULongTy : resultType;
634 MachineInstr* minstr =
635 Create3OperandInstr(opCode, Constant::getNullValue(zeroValueType),
637 mvec.push_back(minstr);
642 // Helper function for sign-extension and zero-extension.
643 // For SPARC v9, we sign-extend the given operand using SLL; SRA/SRL.
645 CreateBitExtensionInstructions(bool signExtend,
646 const TargetMachine& target,
650 unsigned int numLowBits,
651 vector<MachineInstr*>& mvec,
652 MachineCodeForInstruction& mcfi)
656 assert(numLowBits <= 32 && "Otherwise, nothing should be done here!");
659 { // SLL is needed since operand size is < 32 bits.
660 TmpInstruction *tmpI = new TmpInstruction(destVal->getType(),
661 srcVal, destVal, "make32");
663 M = Create3OperandInstr_UImmed(SLLX, srcVal, 32-numLowBits, tmpI);
668 M = Create3OperandInstr_UImmed(signExtend? SRA : SRL,
669 srcVal, 32-numLowBits, destVal);
674 // Create instruction sequence to produce a sign-extended register value
675 // from an arbitrary-sized integer value (sized in bits, not bytes).
676 // The generated instructions are returned in `mvec'.
677 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
678 // Any stack space required is allocated via MachineFunction.
681 UltraSparcInstrInfo::CreateSignExtensionInstructions(
682 const TargetMachine& target,
686 unsigned int numLowBits,
687 vector<MachineInstr*>& mvec,
688 MachineCodeForInstruction& mcfi) const
690 CreateBitExtensionInstructions(/*signExtend*/ true, target, F, srcVal,
691 destVal, numLowBits, mvec, mcfi);
695 // Create instruction sequence to produce a zero-extended register value
696 // from an arbitrary-sized integer value (sized in bits, not bytes).
697 // For SPARC v9, we sign-extend the given operand using SLL; SRL.
698 // The generated instructions are returned in `mvec'.
699 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
700 // Any stack space required is allocated via MachineFunction.
703 UltraSparcInstrInfo::CreateZeroExtensionInstructions(
704 const TargetMachine& target,
708 unsigned int numLowBits,
709 vector<MachineInstr*>& mvec,
710 MachineCodeForInstruction& mcfi) const
712 CreateBitExtensionInstructions(/*signExtend*/ false, target, F, srcVal,
713 destVal, numLowBits, mvec, mcfi);