1 //===-- SparcInstrInfo.cpp ------------------------------------------------===//
3 //===----------------------------------------------------------------------===//
5 #include "SparcInternals.h"
6 #include "SparcInstrSelectionSupport.h"
7 #include "llvm/CodeGen/InstrSelection.h"
8 #include "llvm/CodeGen/InstrSelectionSupport.h"
9 #include "llvm/CodeGen/MachineCodeForMethod.h"
10 #include "llvm/CodeGen/MachineCodeForInstruction.h"
11 #include "llvm/Function.h"
12 #include "llvm/Constants.h"
13 #include "llvm/DerivedTypes.h"
17 static const uint32_t MAXLO = (1 << 10) - 1; // set bits set by %lo(*)
18 static const uint32_t MAXSIMM = (1 << 12) - 1; // set bits in simm13 field of OR
21 //----------------------------------------------------------------------------
22 // Function: CreateSETUWConst
24 // Set a 32-bit unsigned constant in the register `dest', using
25 // SETHI, OR in the worst case. This function correctly emulates
26 // the SETUW pseudo-op for SPARC v9 (if argument isSigned == false).
28 // The isSigned=true case is used to implement SETSW without duplicating code.
30 // Optimize some common cases:
31 // (1) Small value that fits in simm13 field of OR: don't need SETHI.
32 // (2) isSigned = true and C is a small negative signed value, i.e.,
33 // high bits are 1, and the remaining bits fit in simm13(OR).
34 //----------------------------------------------------------------------------
37 CreateSETUWConst(const TargetMachine& target, uint32_t C,
38 Instruction* dest, vector<MachineInstr*>& mvec,
39 bool isSigned = false)
41 MachineInstr *miSETHI = NULL, *miOR = NULL;
43 // In order to get efficient code, we should not generate the SETHI if
44 // all high bits are 1 (i.e., this is a small signed value that fits in
45 // the simm13 field of OR). So we check for and handle that case specially.
46 // NOTE: The value C = 0x80000000 is bad: sC < 0 *and* -sC < 0.
47 // In fact, sC == -sC, so we have to check for this explicitly.
48 int32_t sC = (int32_t) C;
49 bool smallNegValue =isSigned && sC < 0 && sC != -sC && -sC < (int32_t)MAXSIMM;
51 // Set the high 22 bits in dest if non-zero and simm13 field of OR not enough
52 if (!smallNegValue && (C & ~MAXLO) && C > MAXSIMM)
54 miSETHI = Create2OperandInstr_UImmed(SETHI, C, dest);
55 miSETHI->setOperandHi32(0);
56 mvec.push_back(miSETHI);
59 // Set the low 10 or 12 bits in dest. This is necessary if no SETHI
60 // was generated, or if the low 10 bits are non-zero.
61 if (miSETHI==NULL || C & MAXLO)
64 { // unsigned value with high-order bits set using SETHI
65 miOR = Create3OperandInstr_UImmed(OR, dest, C, dest);
66 miOR->setOperandLo32(1);
69 { // unsigned or small signed value that fits in simm13 field of OR
70 assert(smallNegValue || (C & ~MAXSIMM) == 0);
71 miOR = new MachineInstr(OR);
72 miOR->SetMachineOperandReg(0, target.getRegInfo().getZeroRegNum());
73 miOR->SetMachineOperandConst(1, MachineOperand::MO_SignExtendedImmed,
75 miOR->SetMachineOperandVal(2,MachineOperand::MO_VirtualRegister,dest);
80 assert((miSETHI || miOR) && "Oops, no code was generated!");
84 //----------------------------------------------------------------------------
85 // Function: CreateSETSWConst
87 // Set a 32-bit signed constant in the register `dest', with sign-extension
88 // to 64 bits. This uses SETHI, OR, SRA in the worst case.
89 // This function correctly emulates the SETSW pseudo-op for SPARC v9.
91 // Optimize the same cases as SETUWConst, plus:
92 // (1) SRA is not needed for positive or small negative values.
93 //----------------------------------------------------------------------------
96 CreateSETSWConst(const TargetMachine& target, int32_t C,
97 Instruction* dest, vector<MachineInstr*>& mvec)
101 // Set the low 32 bits of dest
102 CreateSETUWConst(target, (uint32_t) C, dest, mvec, /*isSigned*/true);
104 // Sign-extend to the high 32 bits if needed
105 if (C < 0 && (-C) > (int32_t) MAXSIMM)
107 MI = Create3OperandInstr_UImmed(SRA, dest, 0, dest);
113 //----------------------------------------------------------------------------
114 // Function: CreateSETXConst
116 // Set a 64-bit signed or unsigned constant in the register `dest'.
117 // Use SETUWConst for each 32 bit word, plus a left-shift-by-32 in between.
118 // This function correctly emulates the SETX pseudo-op for SPARC v9.
120 // Optimize the same cases as SETUWConst for each 32 bit word.
121 //----------------------------------------------------------------------------
124 CreateSETXConst(const TargetMachine& target, uint64_t C,
125 Instruction* tmpReg, Instruction* dest,
126 vector<MachineInstr*>& mvec)
128 assert(C > (unsigned int) ~0 && "Use SETUW/SETSW for 32-bit values!");
132 // Code to set the upper 32 bits of the value in register `tmpReg'
133 CreateSETUWConst(target, (C >> 32), tmpReg, mvec);
135 // Shift tmpReg left by 32 bits
136 MI = Create3OperandInstr_UImmed(SLLX, tmpReg, 32, tmpReg);
139 // Code to set the low 32 bits of the value in register `dest'
140 CreateSETUWConst(target, C, dest, mvec);
142 // dest = OR(tmpReg, dest)
143 MI = Create3OperandInstr(OR, dest, tmpReg, dest);
148 //----------------------------------------------------------------------------
149 // Function: CreateSETUWLabel
151 // Set a 32-bit constant (given by a symbolic label) in the register `dest'.
152 //----------------------------------------------------------------------------
155 CreateSETUWLabel(const TargetMachine& target, Value* val,
156 Instruction* dest, vector<MachineInstr*>& mvec)
160 // Set the high 22 bits in dest
161 MI = Create2OperandInstr(SETHI, val, dest);
162 MI->setOperandHi32(0);
165 // Set the low 10 bits in dest
166 MI = Create3OperandInstr(OR, dest, val, dest);
167 MI->setOperandLo32(1);
172 //----------------------------------------------------------------------------
173 // Function: CreateSETXLabel
175 // Set a 64-bit constant (given by a symbolic label) in the register `dest'.
176 //----------------------------------------------------------------------------
179 CreateSETXLabel(const TargetMachine& target,
180 Value* val, Instruction* tmpReg, Instruction* dest,
181 vector<MachineInstr*>& mvec)
183 assert(isa<Constant>(val) || isa<GlobalValue>(val) &&
184 "I only know about constant values and global addresses");
188 MI = Create2OperandInstr_Addr(SETHI, val, tmpReg);
189 MI->setOperandHi64(0);
192 MI = Create3OperandInstr_Addr(OR, tmpReg, val, tmpReg);
193 MI->setOperandLo64(1);
196 MI = Create3OperandInstr_UImmed(SLLX, tmpReg, 32, tmpReg);
199 MI = Create2OperandInstr_Addr(SETHI, val, dest);
200 MI->setOperandHi32(0);
203 MI = Create3OperandInstr(OR, dest, tmpReg, dest);
206 MI = Create3OperandInstr_Addr(OR, dest, val, dest);
207 MI->setOperandLo32(1);
212 //----------------------------------------------------------------------------
213 // Function: CreateUIntSetInstruction
215 // Create code to Set an unsigned constant in the register `dest'.
216 // Uses CreateSETUWConst, CreateSETSWConst or CreateSETXConst as needed.
217 // CreateSETSWConst is an optimization for the case that the unsigned value
218 // has all ones in the 33 high bits (so that sign-extension sets them all).
219 //----------------------------------------------------------------------------
222 CreateUIntSetInstruction(const TargetMachine& target,
223 uint64_t C, Instruction* dest,
224 std::vector<MachineInstr*>& mvec,
225 MachineCodeForInstruction& mcfi)
227 static const uint64_t lo32 = (uint32_t) ~0;
228 if (C <= lo32) // High 32 bits are 0. Set low 32 bits.
229 CreateSETUWConst(target, (uint32_t) C, dest, mvec);
230 else if ((C & ~lo32) == ~lo32 && (C & (1 << 31)))
231 { // All high 33 (not 32) bits are 1s: sign-extension will take care
232 // of high 32 bits, so use the sequence for signed int
233 CreateSETSWConst(target, (int32_t) C, dest, mvec);
236 { // C does not fit in 32 bits
237 TmpInstruction* tmpReg = new TmpInstruction(Type::IntTy);
238 mcfi.addTemp(tmpReg);
239 CreateSETXConst(target, C, tmpReg, dest, mvec);
244 //----------------------------------------------------------------------------
245 // Function: CreateIntSetInstruction
247 // Create code to Set a signed constant in the register `dest'.
248 // Really the same as CreateUIntSetInstruction.
249 //----------------------------------------------------------------------------
252 CreateIntSetInstruction(const TargetMachine& target,
253 int64_t C, Instruction* dest,
254 std::vector<MachineInstr*>& mvec,
255 MachineCodeForInstruction& mcfi)
257 CreateUIntSetInstruction(target, (uint64_t) C, dest, mvec, mcfi);
261 //---------------------------------------------------------------------------
262 // Create a table of LLVM opcode -> max. immediate constant likely to
263 // be usable for that operation.
264 //---------------------------------------------------------------------------
266 // Entry == 0 ==> no immediate constant field exists at all.
267 // Entry > 0 ==> abs(immediate constant) <= Entry
269 vector<unsigned int> MaxConstantsTable(Instruction::NumOtherOps);
272 MaxConstantForInstr(unsigned llvmOpCode)
274 int modelOpCode = -1;
276 if (llvmOpCode >= Instruction::FirstBinaryOp &&
277 llvmOpCode < Instruction::NumBinaryOps)
281 case Instruction::Ret: modelOpCode = JMPLCALL; break;
283 case Instruction::Malloc:
284 case Instruction::Alloca:
285 case Instruction::GetElementPtr:
286 case Instruction::PHINode:
287 case Instruction::Cast:
288 case Instruction::Call: modelOpCode = ADD; break;
290 case Instruction::Shl:
291 case Instruction::Shr: modelOpCode = SLLX; break;
296 return (modelOpCode < 0)? 0: SparcMachineInstrDesc[modelOpCode].maxImmedConst;
300 InitializeMaxConstantsTable()
303 assert(MaxConstantsTable.size() == Instruction::NumOtherOps &&
304 "assignments below will be illegal!");
305 for (op = Instruction::FirstTermOp; op < Instruction::NumTermOps; ++op)
306 MaxConstantsTable[op] = MaxConstantForInstr(op);
307 for (op = Instruction::FirstBinaryOp; op < Instruction::NumBinaryOps; ++op)
308 MaxConstantsTable[op] = MaxConstantForInstr(op);
309 for (op = Instruction::FirstMemoryOp; op < Instruction::NumMemoryOps; ++op)
310 MaxConstantsTable[op] = MaxConstantForInstr(op);
311 for (op = Instruction::FirstOtherOp; op < Instruction::NumOtherOps; ++op)
312 MaxConstantsTable[op] = MaxConstantForInstr(op);
316 //---------------------------------------------------------------------------
317 // class UltraSparcInstrInfo
320 // Information about individual instructions.
321 // Most information is stored in the SparcMachineInstrDesc array above.
322 // Other information is computed on demand, and most such functions
323 // default to member functions in base class MachineInstrInfo.
324 //---------------------------------------------------------------------------
327 UltraSparcInstrInfo::UltraSparcInstrInfo(const TargetMachine& tgt)
328 : MachineInstrInfo(tgt, SparcMachineInstrDesc,
329 /*descSize = */ NUM_TOTAL_OPCODES,
330 /*numRealOpCodes = */ NUM_REAL_OPCODES)
332 InitializeMaxConstantsTable();
336 UltraSparcInstrInfo::ConstantMayNotFitInImmedField(const Constant* CV,
337 const Instruction* I) const
339 if (I->getOpcode() >= MaxConstantsTable.size()) // user-defined op (or bug!)
342 if (isa<ConstantPointerNull>(CV)) // can always use %g0
345 if (const ConstantUInt* U = dyn_cast<ConstantUInt>(CV))
346 return (U->getValue() > MaxConstantsTable[I->getOpcode()]);
348 if (const ConstantSInt* S = dyn_cast<ConstantSInt>(CV))
349 return (labs(S->getValue()) > (int) MaxConstantsTable[I->getOpcode()]);
351 if (isa<ConstantBool>(CV))
352 return (1U > MaxConstantsTable[I->getOpcode()]);
358 // Create an instruction sequence to put the constant `val' into
359 // the virtual register `dest'. `val' may be a Constant or a
360 // GlobalValue, viz., the constant address of a global variable or function.
361 // The generated instructions are returned in `mvec'.
362 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
363 // Any stack space required is allocated via MachineCodeForMethod.
366 UltraSparcInstrInfo::CreateCodeToLoadConst(const TargetMachine& target,
370 vector<MachineInstr*>& mvec,
371 MachineCodeForInstruction& mcfi) const
373 assert(isa<Constant>(val) || isa<GlobalValue>(val) &&
374 "I only know about constant values and global addresses");
376 // Use a "set" instruction for known constants or symbolic constants (labels)
377 // that can go in an integer reg.
378 // We have to use a "load" instruction for all other constants,
379 // in particular, floating point constants.
381 const Type* valType = val->getType();
383 if (isa<GlobalValue>(val))
385 TmpInstruction* tmpReg =
386 new TmpInstruction(PointerType::get(val->getType()), val);
387 mcfi.addTemp(tmpReg);
388 CreateSETXLabel(target, val, tmpReg, dest, mvec);
390 else if (valType->isIntegral())
392 bool isValidConstant;
393 unsigned opSize = target.DataLayout.getTypeSize(val->getType());
394 unsigned destSize = target.DataLayout.getTypeSize(dest->getType());
396 if (! dest->getType()->isSigned())
398 uint64_t C = GetConstantValueAsUnsignedInt(val, isValidConstant);
399 assert(isValidConstant && "Unrecognized constant");
401 if (opSize > destSize ||
402 (val->getType()->isSigned()
403 && destSize < target.DataLayout.getIntegerRegize()))
404 { // operand is larger than dest,
405 // OR both are equal but smaller than the full register size
406 // AND operand is signed, so it may have extra sign bits:
408 C = C & ((1U << 8*destSize) - 1);
410 CreateUIntSetInstruction(target, C, dest, mvec, mcfi);
414 int64_t C = GetConstantValueAsSignedInt(val, isValidConstant);
415 assert(isValidConstant && "Unrecognized constant");
417 if (opSize > destSize)
418 // operand is larger than dest: mask high bits
419 C = C & ((1U << 8*destSize) - 1);
421 if (opSize > destSize ||
422 (opSize == destSize && !val->getType()->isSigned()))
423 // sign-extend from destSize to 64 bits
424 C = ((C & (1U << (8*destSize - 1)))
425 ? C | ~((1U << 8*destSize) - 1)
428 CreateIntSetInstruction(target, C, dest, mvec, mcfi);
433 // Make an instruction sequence to load the constant, viz:
434 // SETX <addr-of-constant>, tmpReg, addrReg
435 // LOAD /*addr*/ addrReg, /*offset*/ 0, dest
437 // First, create a tmp register to be used by the SETX sequence.
438 TmpInstruction* tmpReg =
439 new TmpInstruction(PointerType::get(val->getType()), val);
440 mcfi.addTemp(tmpReg);
442 // Create another TmpInstruction for the address register
443 TmpInstruction* addrReg =
444 new TmpInstruction(PointerType::get(val->getType()), val);
445 mcfi.addTemp(addrReg);
447 // Put the address (a symbolic name) into a register
448 CreateSETXLabel(target, val, tmpReg, addrReg, mvec);
450 // Generate the load instruction
451 int64_t zeroOffset = 0; // to avoid ambiguity with (Value*) 0
453 Create3OperandInstr_SImmed(ChooseLoadInstruction(val->getType()),
454 addrReg, zeroOffset, dest);
457 // Make sure constant is emitted to constant pool in assembly code.
458 MachineCodeForMethod::get(F).addToConstantPool(cast<Constant>(val));
463 // Create an instruction sequence to copy an integer register `val'
464 // to a floating point register `dest' by copying to memory and back.
465 // val must be an integral type. dest must be a Float or Double.
466 // The generated instructions are returned in `mvec'.
467 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
468 // Any stack space required is allocated via MachineCodeForMethod.
471 UltraSparcInstrInfo::CreateCodeToCopyIntToFloat(const TargetMachine& target,
475 vector<MachineInstr*>& mvec,
476 MachineCodeForInstruction& mcfi) const
478 assert((val->getType()->isIntegral() || isa<PointerType>(val->getType()))
479 && "Source type must be integral (integer or bool) or pointer");
480 assert(dest->getType()->isFloatingPoint()
481 && "Dest type must be float/double");
483 // Get a stack slot to use for the copy
484 int offset = MachineCodeForMethod::get(F).allocateLocalVar(target, val);
486 // Get the size of the source value being copied.
487 size_t srcSize = target.DataLayout.getTypeSize(val->getType());
489 // Store instruction stores `val' to [%fp+offset].
490 // The store and load opCodes are based on the size of the source value.
491 // If the value is smaller than 32 bits, we must sign- or zero-extend it
492 // to 32 bits since the load-float will load 32 bits.
493 // Note that the store instruction is the same for signed and unsigned ints.
494 const Type* storeType = (srcSize <= 4)? Type::IntTy : Type::LongTy;
495 Value* storeVal = val;
496 if (srcSize < target.DataLayout.getTypeSize(Type::FloatTy))
497 { // sign- or zero-extend respectively
498 storeVal = new TmpInstruction(storeType, val);
499 if (val->getType()->isSigned())
500 CreateSignExtensionInstructions(target, F, val, 8*srcSize, storeVal,
503 CreateZeroExtensionInstructions(target, F, val, 8*srcSize, storeVal,
506 MachineInstr* store=new MachineInstr(ChooseStoreInstruction(storeType));
507 store->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister, storeVal);
508 store->SetMachineOperandReg(1, target.getRegInfo().getFramePointer());
509 store->SetMachineOperandConst(2,MachineOperand::MO_SignExtendedImmed,offset);
510 mvec.push_back(store);
512 // Load instruction loads [%fp+offset] to `dest'.
513 // The type of the load opCode is the floating point type that matches the
514 // stored type in size:
515 // On SparcV9: float for int or smaller, double for long.
517 const Type* loadType = (srcSize <= 4)? Type::FloatTy : Type::DoubleTy;
518 MachineInstr* load = new MachineInstr(ChooseLoadInstruction(loadType));
519 load->SetMachineOperandReg(0, target.getRegInfo().getFramePointer());
520 load->SetMachineOperandConst(1, MachineOperand::MO_SignExtendedImmed,offset);
521 load->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister, dest);
522 mvec.push_back(load);
525 // Similarly, create an instruction sequence to copy an FP register
526 // `val' to an integer register `dest' by copying to memory and back.
527 // The generated instructions are returned in `mvec'.
528 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
529 // Any stack space required is allocated via MachineCodeForMethod.
532 UltraSparcInstrInfo::CreateCodeToCopyFloatToInt(const TargetMachine& target,
536 vector<MachineInstr*>& mvec,
537 MachineCodeForInstruction& mcfi) const
539 const Type* opTy = val->getType();
540 const Type* destTy = dest->getType();
542 assert(opTy->isFloatingPoint() && "Source type must be float/double");
543 assert((destTy->isIntegral() || isa<PointerType>(destTy))
544 && "Dest type must be integer, bool or pointer");
546 int offset = MachineCodeForMethod::get(F).allocateLocalVar(target, val);
548 // Store instruction stores `val' to [%fp+offset].
549 // The store opCode is based only the source value being copied.
551 MachineInstr* store=new MachineInstr(ChooseStoreInstruction(opTy));
552 store->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister, val);
553 store->SetMachineOperandReg(1, target.getRegInfo().getFramePointer());
554 store->SetMachineOperandConst(2,MachineOperand::MO_SignExtendedImmed,offset);
555 mvec.push_back(store);
557 // Load instruction loads [%fp+offset] to `dest'.
558 // The type of the load opCode is the integer type that matches the
559 // source type in size:
560 // On SparcV9: int for float, long for double.
561 // Note that we *must* use signed loads even for unsigned dest types, to
562 // ensure correct sign-extension for UByte, UShort or UInt:
564 const Type* loadTy = (opTy == Type::FloatTy)? Type::IntTy : Type::LongTy;
565 MachineInstr* load = new MachineInstr(ChooseLoadInstruction(loadTy));
566 load->SetMachineOperandReg(0, target.getRegInfo().getFramePointer());
567 load->SetMachineOperandConst(1, MachineOperand::MO_SignExtendedImmed,offset);
568 load->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister, dest);
569 mvec.push_back(load);
573 // Create instruction(s) to copy src to dest, for arbitrary types
574 // The generated instructions are returned in `mvec'.
575 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
576 // Any stack space required is allocated via MachineCodeForMethod.
579 UltraSparcInstrInfo::CreateCopyInstructionsByType(const TargetMachine& target,
583 vector<MachineInstr*>& mvec,
584 MachineCodeForInstruction& mcfi) const
586 bool loadConstantToReg = false;
588 const Type* resultType = dest->getType();
590 MachineOpCode opCode = ChooseAddInstructionByType(resultType);
591 if (opCode == INVALID_OPCODE)
593 assert(0 && "Unsupported result type in CreateCopyInstructionsByType()");
597 // if `src' is a constant that doesn't fit in the immed field or if it is
598 // a global variable (i.e., a constant address), generate a load
599 // instruction instead of an add
601 if (isa<Constant>(src))
603 unsigned int machineRegNum;
605 MachineOperand::MachineOperandType opType =
606 ChooseRegOrImmed(src, opCode, target, /*canUseImmed*/ true,
607 machineRegNum, immedValue);
609 if (opType == MachineOperand::MO_VirtualRegister)
610 loadConstantToReg = true;
612 else if (isa<GlobalValue>(src))
613 loadConstantToReg = true;
615 if (loadConstantToReg)
616 { // `src' is constant and cannot fit in immed field for the ADD
617 // Insert instructions to "load" the constant into a register
618 target.getInstrInfo().CreateCodeToLoadConst(target, F, src, dest,
622 { // Create an add-with-0 instruction of the appropriate type.
623 // Make `src' the second operand, in case it is a constant
624 // Use (unsigned long) 0 for a NULL pointer value.
626 const Type* zeroValueType =
627 isa<PointerType>(resultType) ? Type::ULongTy : resultType;
628 MachineInstr* minstr =
629 Create3OperandInstr(opCode, Constant::getNullValue(zeroValueType),
631 mvec.push_back(minstr);
636 // Helper function for sign-extension and zero-extension.
637 // For SPARC v9, we sign-extend the given operand using SLL; SRA/SRL.
639 CreateBitExtensionInstructions(bool signExtend,
640 const TargetMachine& target,
643 unsigned int srcSizeInBits,
645 vector<MachineInstr*>& mvec,
646 MachineCodeForInstruction& mcfi)
649 assert(srcSizeInBits <= 32 &&
650 "Hmmm... 32 < srcSizeInBits < 64 unexpected but could be handled.");
652 if (srcSizeInBits < 32)
653 { // SLL is needed since operand size is < 32 bits.
654 TmpInstruction *tmpI = new TmpInstruction(dest->getType(),
655 srcVal, dest,"make32");
657 M = Create3OperandInstr_UImmed(SLLX, srcVal, 32-srcSizeInBits, tmpI);
662 M = Create3OperandInstr_UImmed(signExtend? SRA : SRL,
663 srcVal, 32-srcSizeInBits, dest);
668 // Create instruction sequence to produce a sign-extended register value
669 // from an arbitrary-sized integer value (sized in bits, not bytes).
670 // The generated instructions are returned in `mvec'.
671 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
672 // Any stack space required is allocated via MachineCodeForMethod.
675 UltraSparcInstrInfo::CreateSignExtensionInstructions(
676 const TargetMachine& target,
679 unsigned int srcSizeInBits,
681 vector<MachineInstr*>& mvec,
682 MachineCodeForInstruction& mcfi) const
684 CreateBitExtensionInstructions(/*signExtend*/ true, target, F, srcVal,
685 srcSizeInBits, dest, mvec, mcfi);
689 // Create instruction sequence to produce a zero-extended register value
690 // from an arbitrary-sized integer value (sized in bits, not bytes).
691 // For SPARC v9, we sign-extend the given operand using SLL; SRL.
692 // The generated instructions are returned in `mvec'.
693 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
694 // Any stack space required is allocated via MachineCodeForMethod.
697 UltraSparcInstrInfo::CreateZeroExtensionInstructions(
698 const TargetMachine& target,
701 unsigned int srcSizeInBits,
703 vector<MachineInstr*>& mvec,
704 MachineCodeForInstruction& mcfi) const
706 CreateBitExtensionInstructions(/*signExtend*/ false, target, F, srcVal,
707 srcSizeInBits, dest, mvec, mcfi);