1 //===-- SparcInstrInfo.cpp ------------------------------------------------===//
3 //===----------------------------------------------------------------------===//
5 #include "SparcInternals.h"
6 #include "SparcInstrSelectionSupport.h"
7 #include "llvm/CodeGen/InstrSelection.h"
8 #include "llvm/CodeGen/InstrSelectionSupport.h"
9 #include "llvm/CodeGen/MachineFunction.h"
10 #include "llvm/CodeGen/MachineFunctionInfo.h"
11 #include "llvm/CodeGen/MachineCodeForInstruction.h"
12 #include "llvm/CodeGen/MachineInstrBuilder.h"
13 #include "llvm/Function.h"
14 #include "llvm/Constants.h"
15 #include "llvm/DerivedTypes.h"
19 static const uint32_t MAXLO = (1 << 10) - 1; // set bits set by %lo(*)
20 static const uint32_t MAXSIMM = (1 << 12) - 1; // set bits in simm13 field of OR
23 //---------------------------------------------------------------------------
24 // Function GetConstantValueAsUnsignedInt
25 // Function GetConstantValueAsSignedInt
27 // Convenience functions to get the value of an integral constant, for an
28 // appropriate integer or non-integer type that can be held in a signed
29 // or unsigned integer respectively. The type of the argument must be
31 // Signed or unsigned integer
35 // isValidConstant is set to true if a valid constant was found.
36 //---------------------------------------------------------------------------
39 GetConstantValueAsUnsignedInt(const Value *V,
40 bool &isValidConstant)
42 isValidConstant = true;
45 if (const ConstantBool *CB = dyn_cast<ConstantBool>(V))
46 return (int64_t)CB->getValue();
47 else if (const ConstantSInt *CS = dyn_cast<ConstantSInt>(V))
48 return (uint64_t)CS->getValue();
49 else if (const ConstantUInt *CU = dyn_cast<ConstantUInt>(V))
50 return CU->getValue();
52 isValidConstant = false;
57 GetConstantValueAsSignedInt(const Value *V, bool &isValidConstant)
59 uint64_t C = GetConstantValueAsUnsignedInt(V, isValidConstant);
60 if (isValidConstant) {
61 if (V->getType()->isSigned() || C < INT64_MAX) // safe to cast to signed
64 isValidConstant = false;
70 //----------------------------------------------------------------------------
71 // Function: CreateSETUWConst
73 // Set a 32-bit unsigned constant in the register `dest', using
74 // SETHI, OR in the worst case. This function correctly emulates
75 // the SETUW pseudo-op for SPARC v9 (if argument isSigned == false).
77 // The isSigned=true case is used to implement SETSW without duplicating code.
79 // Optimize some common cases:
80 // (1) Small value that fits in simm13 field of OR: don't need SETHI.
81 // (2) isSigned = true and C is a small negative signed value, i.e.,
82 // high bits are 1, and the remaining bits fit in simm13(OR).
83 //----------------------------------------------------------------------------
86 CreateSETUWConst(const TargetMachine& target, uint32_t C,
87 Instruction* dest, vector<MachineInstr*>& mvec,
88 bool isSigned = false)
90 MachineInstr *miSETHI = NULL, *miOR = NULL;
92 // In order to get efficient code, we should not generate the SETHI if
93 // all high bits are 1 (i.e., this is a small signed value that fits in
94 // the simm13 field of OR). So we check for and handle that case specially.
95 // NOTE: The value C = 0x80000000 is bad: sC < 0 *and* -sC < 0.
96 // In fact, sC == -sC, so we have to check for this explicitly.
97 int32_t sC = (int32_t) C;
98 bool smallNegValue =isSigned && sC < 0 && sC != -sC && -sC < (int32_t)MAXSIMM;
100 // Set the high 22 bits in dest if non-zero and simm13 field of OR not enough
101 if (!smallNegValue && (C & ~MAXLO) && C > MAXSIMM)
103 miSETHI = BuildMI(SETHI, 2).addZImm(C).addRegDef(dest);
104 miSETHI->setOperandHi32(0);
105 mvec.push_back(miSETHI);
108 // Set the low 10 or 12 bits in dest. This is necessary if no SETHI
109 // was generated, or if the low 10 bits are non-zero.
110 if (miSETHI==NULL || C & MAXLO)
113 { // unsigned value with high-order bits set using SETHI
114 miOR = BuildMI(OR, 3).addReg(dest).addZImm(C).addRegDef(dest);
115 miOR->setOperandLo32(1);
118 { // unsigned or small signed value that fits in simm13 field of OR
119 assert(smallNegValue || (C & ~MAXSIMM) == 0);
120 miOR = BuildMI(OR, 3).addMReg(target.getRegInfo().getZeroRegNum())
121 .addSImm(sC).addRegDef(dest);
123 mvec.push_back(miOR);
126 assert((miSETHI || miOR) && "Oops, no code was generated!");
130 //----------------------------------------------------------------------------
131 // Function: CreateSETSWConst
133 // Set a 32-bit signed constant in the register `dest', with sign-extension
134 // to 64 bits. This uses SETHI, OR, SRA in the worst case.
135 // This function correctly emulates the SETSW pseudo-op for SPARC v9.
137 // Optimize the same cases as SETUWConst, plus:
138 // (1) SRA is not needed for positive or small negative values.
139 //----------------------------------------------------------------------------
142 CreateSETSWConst(const TargetMachine& target, int32_t C,
143 Instruction* dest, vector<MachineInstr*>& mvec)
145 // Set the low 32 bits of dest
146 CreateSETUWConst(target, (uint32_t) C, dest, mvec, /*isSigned*/true);
148 // Sign-extend to the high 32 bits if needed
149 if (C < 0 && (-C) > (int32_t) MAXSIMM)
150 mvec.push_back(BuildMI(SRA, 3).addReg(dest).addZImm(0).addRegDef(dest));
154 //----------------------------------------------------------------------------
155 // Function: CreateSETXConst
157 // Set a 64-bit signed or unsigned constant in the register `dest'.
158 // Use SETUWConst for each 32 bit word, plus a left-shift-by-32 in between.
159 // This function correctly emulates the SETX pseudo-op for SPARC v9.
161 // Optimize the same cases as SETUWConst for each 32 bit word.
162 //----------------------------------------------------------------------------
165 CreateSETXConst(const TargetMachine& target, uint64_t C,
166 Instruction* tmpReg, Instruction* dest,
167 vector<MachineInstr*>& mvec)
169 assert(C > (unsigned int) ~0 && "Use SETUW/SETSW for 32-bit values!");
173 // Code to set the upper 32 bits of the value in register `tmpReg'
174 CreateSETUWConst(target, (C >> 32), tmpReg, mvec);
176 // Shift tmpReg left by 32 bits
177 mvec.push_back(BuildMI(SLLX, 3).addReg(tmpReg).addZImm(32).addRegDef(tmpReg));
179 // Code to set the low 32 bits of the value in register `dest'
180 CreateSETUWConst(target, C, dest, mvec);
182 // dest = OR(tmpReg, dest)
183 mvec.push_back(BuildMI(OR, 3).addReg(dest).addReg(tmpReg).addRegDef(dest));
187 //----------------------------------------------------------------------------
188 // Function: CreateSETUWLabel
190 // Set a 32-bit constant (given by a symbolic label) in the register `dest'.
191 //----------------------------------------------------------------------------
194 CreateSETUWLabel(const TargetMachine& target, Value* val,
195 Instruction* dest, vector<MachineInstr*>& mvec)
199 // Set the high 22 bits in dest
200 MI = BuildMI(SETHI, 2).addReg(val).addRegDef(dest);
201 MI->setOperandHi32(0);
204 // Set the low 10 bits in dest
205 MI = BuildMI(OR, 3).addReg(dest).addReg(val).addRegDef(dest);
206 MI->setOperandLo32(1);
211 //----------------------------------------------------------------------------
212 // Function: CreateSETXLabel
214 // Set a 64-bit constant (given by a symbolic label) in the register `dest'.
215 //----------------------------------------------------------------------------
218 CreateSETXLabel(const TargetMachine& target,
219 Value* val, Instruction* tmpReg, Instruction* dest,
220 vector<MachineInstr*>& mvec)
222 assert(isa<Constant>(val) || isa<GlobalValue>(val) &&
223 "I only know about constant values and global addresses");
227 MI = BuildMI(SETHI, 2).addPCDisp(val).addRegDef(tmpReg);
228 MI->setOperandHi64(0);
231 MI = BuildMI(OR, 3).addReg(tmpReg).addPCDisp(val).addRegDef(tmpReg);
232 MI->setOperandLo64(1);
235 mvec.push_back(BuildMI(SLLX, 3).addReg(tmpReg).addZImm(32).addRegDef(tmpReg));
236 MI = BuildMI(SETHI, 2).addPCDisp(val).addRegDef(dest);
237 MI->setOperandHi32(0);
240 MI = BuildMI(OR, 3).addReg(dest).addReg(tmpReg).addRegDef(dest);
243 MI = BuildMI(OR, 3).addReg(dest).addPCDisp(val).addRegDef(dest);
244 MI->setOperandLo32(1);
249 //----------------------------------------------------------------------------
250 // Function: CreateUIntSetInstruction
252 // Create code to Set an unsigned constant in the register `dest'.
253 // Uses CreateSETUWConst, CreateSETSWConst or CreateSETXConst as needed.
254 // CreateSETSWConst is an optimization for the case that the unsigned value
255 // has all ones in the 33 high bits (so that sign-extension sets them all).
256 //----------------------------------------------------------------------------
259 CreateUIntSetInstruction(const TargetMachine& target,
260 uint64_t C, Instruction* dest,
261 std::vector<MachineInstr*>& mvec,
262 MachineCodeForInstruction& mcfi)
264 static const uint64_t lo32 = (uint32_t) ~0;
265 if (C <= lo32) // High 32 bits are 0. Set low 32 bits.
266 CreateSETUWConst(target, (uint32_t) C, dest, mvec);
267 else if ((C & ~lo32) == ~lo32 && (C & (1 << 31)))
268 { // All high 33 (not 32) bits are 1s: sign-extension will take care
269 // of high 32 bits, so use the sequence for signed int
270 CreateSETSWConst(target, (int32_t) C, dest, mvec);
273 { // C does not fit in 32 bits
274 TmpInstruction* tmpReg = new TmpInstruction(Type::IntTy);
275 mcfi.addTemp(tmpReg);
276 CreateSETXConst(target, C, tmpReg, dest, mvec);
281 //----------------------------------------------------------------------------
282 // Function: CreateIntSetInstruction
284 // Create code to Set a signed constant in the register `dest'.
285 // Really the same as CreateUIntSetInstruction.
286 //----------------------------------------------------------------------------
289 CreateIntSetInstruction(const TargetMachine& target,
290 int64_t C, Instruction* dest,
291 std::vector<MachineInstr*>& mvec,
292 MachineCodeForInstruction& mcfi)
294 CreateUIntSetInstruction(target, (uint64_t) C, dest, mvec, mcfi);
298 //---------------------------------------------------------------------------
299 // Create a table of LLVM opcode -> max. immediate constant likely to
300 // be usable for that operation.
301 //---------------------------------------------------------------------------
303 // Entry == 0 ==> no immediate constant field exists at all.
304 // Entry > 0 ==> abs(immediate constant) <= Entry
306 vector<int> MaxConstantsTable(Instruction::OtherOpsEnd);
309 MaxConstantForInstr(unsigned llvmOpCode)
311 int modelOpCode = -1;
313 if (llvmOpCode >= Instruction::BinaryOpsBegin &&
314 llvmOpCode < Instruction::BinaryOpsEnd)
318 case Instruction::Ret: modelOpCode = JMPLCALL; break;
320 case Instruction::Malloc:
321 case Instruction::Alloca:
322 case Instruction::GetElementPtr:
323 case Instruction::PHINode:
324 case Instruction::Cast:
325 case Instruction::Call: modelOpCode = ADD; break;
327 case Instruction::Shl:
328 case Instruction::Shr: modelOpCode = SLLX; break;
333 return (modelOpCode < 0)? 0: SparcMachineInstrDesc[modelOpCode].maxImmedConst;
337 InitializeMaxConstantsTable()
340 assert(MaxConstantsTable.size() == Instruction::OtherOpsEnd &&
341 "assignments below will be illegal!");
342 for (op = Instruction::TermOpsBegin; op < Instruction::TermOpsEnd; ++op)
343 MaxConstantsTable[op] = MaxConstantForInstr(op);
344 for (op = Instruction::BinaryOpsBegin; op < Instruction::BinaryOpsEnd; ++op)
345 MaxConstantsTable[op] = MaxConstantForInstr(op);
346 for (op = Instruction::MemoryOpsBegin; op < Instruction::MemoryOpsEnd; ++op)
347 MaxConstantsTable[op] = MaxConstantForInstr(op);
348 for (op = Instruction::OtherOpsBegin; op < Instruction::OtherOpsEnd; ++op)
349 MaxConstantsTable[op] = MaxConstantForInstr(op);
353 //---------------------------------------------------------------------------
354 // class UltraSparcInstrInfo
357 // Information about individual instructions.
358 // Most information is stored in the SparcMachineInstrDesc array above.
359 // Other information is computed on demand, and most such functions
360 // default to member functions in base class TargetInstrInfo.
361 //---------------------------------------------------------------------------
364 UltraSparcInstrInfo::UltraSparcInstrInfo()
365 : TargetInstrInfo(SparcMachineInstrDesc,
366 /*descSize = */ NUM_TOTAL_OPCODES,
367 /*numRealOpCodes = */ NUM_REAL_OPCODES)
369 InitializeMaxConstantsTable();
373 UltraSparcInstrInfo::ConstantMayNotFitInImmedField(const Constant* CV,
374 const Instruction* I) const
376 if (I->getOpcode() >= MaxConstantsTable.size()) // user-defined op (or bug!)
379 if (isa<ConstantPointerNull>(CV)) // can always use %g0
382 if (const ConstantUInt* U = dyn_cast<ConstantUInt>(CV))
383 /* Large unsigned longs may really just be small negative signed longs */
384 return (labs((int64_t) U->getValue()) > MaxConstantsTable[I->getOpcode()]);
386 if (const ConstantSInt* S = dyn_cast<ConstantSInt>(CV))
387 return (labs(S->getValue()) > MaxConstantsTable[I->getOpcode()]);
389 if (isa<ConstantBool>(CV))
390 return (1 > MaxConstantsTable[I->getOpcode()]);
396 // Create an instruction sequence to put the constant `val' into
397 // the virtual register `dest'. `val' may be a Constant or a
398 // GlobalValue, viz., the constant address of a global variable or function.
399 // The generated instructions are returned in `mvec'.
400 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
401 // Any stack space required is allocated via MachineFunction.
404 UltraSparcInstrInfo::CreateCodeToLoadConst(const TargetMachine& target,
408 vector<MachineInstr*>& mvec,
409 MachineCodeForInstruction& mcfi) const
411 assert(isa<Constant>(val) || isa<GlobalValue>(val) &&
412 "I only know about constant values and global addresses");
414 // Use a "set" instruction for known constants or symbolic constants (labels)
415 // that can go in an integer reg.
416 // We have to use a "load" instruction for all other constants,
417 // in particular, floating point constants.
419 const Type* valType = val->getType();
421 // Unfortunate special case: a ConstantPointerRef is just a
422 // reference to GlobalValue.
423 if (isa<ConstantPointerRef>(val))
424 val = cast<ConstantPointerRef>(val)->getValue();
426 if (isa<GlobalValue>(val))
428 TmpInstruction* tmpReg =
429 new TmpInstruction(PointerType::get(val->getType()), val);
430 mcfi.addTemp(tmpReg);
431 CreateSETXLabel(target, val, tmpReg, dest, mvec);
433 else if (valType->isIntegral())
435 bool isValidConstant;
436 unsigned opSize = target.getTargetData().getTypeSize(val->getType());
437 unsigned destSize = target.getTargetData().getTypeSize(dest->getType());
439 if (! dest->getType()->isSigned())
441 uint64_t C = GetConstantValueAsUnsignedInt(val, isValidConstant);
442 assert(isValidConstant && "Unrecognized constant");
444 if (opSize > destSize ||
445 (val->getType()->isSigned()
446 && destSize < target.getTargetData().getIntegerRegize()))
447 { // operand is larger than dest,
448 // OR both are equal but smaller than the full register size
449 // AND operand is signed, so it may have extra sign bits:
451 C = C & ((1U << 8*destSize) - 1);
453 CreateUIntSetInstruction(target, C, dest, mvec, mcfi);
457 int64_t C = GetConstantValueAsSignedInt(val, isValidConstant);
458 assert(isValidConstant && "Unrecognized constant");
460 if (opSize > destSize)
461 // operand is larger than dest: mask high bits
462 C = C & ((1U << 8*destSize) - 1);
464 if (opSize > destSize ||
465 (opSize == destSize && !val->getType()->isSigned()))
466 // sign-extend from destSize to 64 bits
467 C = ((C & (1U << (8*destSize - 1)))
468 ? C | ~((1U << 8*destSize) - 1)
471 CreateIntSetInstruction(target, C, dest, mvec, mcfi);
476 // Make an instruction sequence to load the constant, viz:
477 // SETX <addr-of-constant>, tmpReg, addrReg
478 // LOAD /*addr*/ addrReg, /*offset*/ 0, dest
480 // First, create a tmp register to be used by the SETX sequence.
481 TmpInstruction* tmpReg =
482 new TmpInstruction(PointerType::get(val->getType()), val);
483 mcfi.addTemp(tmpReg);
485 // Create another TmpInstruction for the address register
486 TmpInstruction* addrReg =
487 new TmpInstruction(PointerType::get(val->getType()), val);
488 mcfi.addTemp(addrReg);
490 // Put the address (a symbolic name) into a register
491 CreateSETXLabel(target, val, tmpReg, addrReg, mvec);
493 // Generate the load instruction
494 int64_t zeroOffset = 0; // to avoid ambiguity with (Value*) 0
495 unsigned Opcode = ChooseLoadInstruction(val->getType());
496 mvec.push_back(BuildMI(Opcode, 3).addReg(addrReg).
497 addSImm(zeroOffset).addRegDef(dest));
499 // Make sure constant is emitted to constant pool in assembly code.
500 MachineFunction::get(F).getInfo()->addToConstantPool(cast<Constant>(val));
505 // Create an instruction sequence to copy an integer register `val'
506 // to a floating point register `dest' by copying to memory and back.
507 // val must be an integral type. dest must be a Float or Double.
508 // The generated instructions are returned in `mvec'.
509 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
510 // Any stack space required is allocated via MachineFunction.
513 UltraSparcInstrInfo::CreateCodeToCopyIntToFloat(const TargetMachine& target,
517 vector<MachineInstr*>& mvec,
518 MachineCodeForInstruction& mcfi) const
520 assert((val->getType()->isIntegral() || isa<PointerType>(val->getType()))
521 && "Source type must be integral (integer or bool) or pointer");
522 assert(dest->getType()->isFloatingPoint()
523 && "Dest type must be float/double");
525 // Get a stack slot to use for the copy
526 int offset = MachineFunction::get(F).getInfo()->allocateLocalVar(val);
528 // Get the size of the source value being copied.
529 size_t srcSize = target.getTargetData().getTypeSize(val->getType());
531 // Store instruction stores `val' to [%fp+offset].
532 // The store and load opCodes are based on the size of the source value.
533 // If the value is smaller than 32 bits, we must sign- or zero-extend it
534 // to 32 bits since the load-float will load 32 bits.
535 // Note that the store instruction is the same for signed and unsigned ints.
536 const Type* storeType = (srcSize <= 4)? Type::IntTy : Type::LongTy;
537 Value* storeVal = val;
538 if (srcSize < target.getTargetData().getTypeSize(Type::FloatTy))
539 { // sign- or zero-extend respectively
540 storeVal = new TmpInstruction(storeType, val);
541 if (val->getType()->isSigned())
542 CreateSignExtensionInstructions(target, F, val, storeVal, 8*srcSize,
545 CreateZeroExtensionInstructions(target, F, val, storeVal, 8*srcSize,
549 unsigned FPReg = target.getRegInfo().getFramePointer();
550 mvec.push_back(BuildMI(ChooseStoreInstruction(storeType), 3)
551 .addReg(storeVal).addMReg(FPReg).addSImm(offset));
553 // Load instruction loads [%fp+offset] to `dest'.
554 // The type of the load opCode is the floating point type that matches the
555 // stored type in size:
556 // On SparcV9: float for int or smaller, double for long.
558 const Type* loadType = (srcSize <= 4)? Type::FloatTy : Type::DoubleTy;
559 mvec.push_back(BuildMI(ChooseLoadInstruction(loadType), 3)
560 .addMReg(FPReg).addSImm(offset).addRegDef(dest));
563 // Similarly, create an instruction sequence to copy an FP register
564 // `val' to an integer register `dest' by copying to memory and back.
565 // The generated instructions are returned in `mvec'.
566 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
567 // Any stack space required is allocated via MachineFunction.
570 UltraSparcInstrInfo::CreateCodeToCopyFloatToInt(const TargetMachine& target,
574 vector<MachineInstr*>& mvec,
575 MachineCodeForInstruction& mcfi) const
577 const Type* opTy = val->getType();
578 const Type* destTy = dest->getType();
580 assert(opTy->isFloatingPoint() && "Source type must be float/double");
581 assert((destTy->isIntegral() || isa<PointerType>(destTy))
582 && "Dest type must be integer, bool or pointer");
584 int offset = MachineFunction::get(F).getInfo()->allocateLocalVar(val);
586 unsigned FPReg = target.getRegInfo().getFramePointer();
588 // Store instruction stores `val' to [%fp+offset].
589 // The store opCode is based only the source value being copied.
591 mvec.push_back(BuildMI(ChooseStoreInstruction(opTy), 3)
592 .addReg(val).addMReg(FPReg).addSImm(offset));
594 // Load instruction loads [%fp+offset] to `dest'.
595 // The type of the load opCode is the integer type that matches the
596 // source type in size:
597 // On SparcV9: int for float, long for double.
598 // Note that we *must* use signed loads even for unsigned dest types, to
599 // ensure correct sign-extension for UByte, UShort or UInt:
601 const Type* loadTy = (opTy == Type::FloatTy)? Type::IntTy : Type::LongTy;
602 mvec.push_back(BuildMI(ChooseLoadInstruction(loadTy), 3).addMReg(FPReg)
603 .addSImm(offset).addRegDef(dest));
607 // Create instruction(s) to copy src to dest, for arbitrary types
608 // The generated instructions are returned in `mvec'.
609 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
610 // Any stack space required is allocated via MachineFunction.
613 UltraSparcInstrInfo::CreateCopyInstructionsByType(const TargetMachine& target,
617 vector<MachineInstr*>& mvec,
618 MachineCodeForInstruction& mcfi) const
620 bool loadConstantToReg = false;
622 const Type* resultType = dest->getType();
624 MachineOpCode opCode = ChooseAddInstructionByType(resultType);
625 if (opCode == INVALID_OPCODE)
627 assert(0 && "Unsupported result type in CreateCopyInstructionsByType()");
631 // if `src' is a constant that doesn't fit in the immed field or if it is
632 // a global variable (i.e., a constant address), generate a load
633 // instruction instead of an add
635 if (isa<Constant>(src))
637 unsigned int machineRegNum;
639 MachineOperand::MachineOperandType opType =
640 ChooseRegOrImmed(src, opCode, target, /*canUseImmed*/ true,
641 machineRegNum, immedValue);
643 if (opType == MachineOperand::MO_VirtualRegister)
644 loadConstantToReg = true;
646 else if (isa<GlobalValue>(src))
647 loadConstantToReg = true;
649 if (loadConstantToReg)
650 { // `src' is constant and cannot fit in immed field for the ADD
651 // Insert instructions to "load" the constant into a register
652 target.getInstrInfo().CreateCodeToLoadConst(target, F, src, dest,
656 { // Create an add-with-0 instruction of the appropriate type.
657 // Make `src' the second operand, in case it is a constant
658 // Use (unsigned long) 0 for a NULL pointer value.
660 const Type* Ty =isa<PointerType>(resultType) ? Type::ULongTy : resultType;
662 BuildMI(opCode, 3).addReg(Constant::getNullValue(Ty))
663 .addReg(src).addRegDef(dest);
669 // Helper function for sign-extension and zero-extension.
670 // For SPARC v9, we sign-extend the given operand using SLL; SRA/SRL.
672 CreateBitExtensionInstructions(bool signExtend,
673 const TargetMachine& target,
677 unsigned int numLowBits,
678 vector<MachineInstr*>& mvec,
679 MachineCodeForInstruction& mcfi)
683 assert(numLowBits <= 32 && "Otherwise, nothing should be done here!");
686 { // SLL is needed since operand size is < 32 bits.
687 TmpInstruction *tmpI = new TmpInstruction(destVal->getType(),
688 srcVal, destVal, "make32");
690 mvec.push_back(BuildMI(SLLX, 3).addReg(srcVal).addZImm(32-numLowBits)
695 mvec.push_back(BuildMI(signExtend? SRA : SRL, 3).addReg(srcVal)
696 .addZImm(32-numLowBits).addRegDef(destVal));
700 // Create instruction sequence to produce a sign-extended register value
701 // from an arbitrary-sized integer value (sized in bits, not bytes).
702 // The generated instructions are returned in `mvec'.
703 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
704 // Any stack space required is allocated via MachineFunction.
707 UltraSparcInstrInfo::CreateSignExtensionInstructions(
708 const TargetMachine& target,
712 unsigned int numLowBits,
713 vector<MachineInstr*>& mvec,
714 MachineCodeForInstruction& mcfi) const
716 CreateBitExtensionInstructions(/*signExtend*/ true, target, F, srcVal,
717 destVal, numLowBits, mvec, mcfi);
721 // Create instruction sequence to produce a zero-extended register value
722 // from an arbitrary-sized integer value (sized in bits, not bytes).
723 // For SPARC v9, we sign-extend the given operand using SLL; SRL.
724 // The generated instructions are returned in `mvec'.
725 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
726 // Any stack space required is allocated via MachineFunction.
729 UltraSparcInstrInfo::CreateZeroExtensionInstructions(
730 const TargetMachine& target,
734 unsigned int numLowBits,
735 vector<MachineInstr*>& mvec,
736 MachineCodeForInstruction& mcfi) const
738 CreateBitExtensionInstructions(/*signExtend*/ false, target, F, srcVal,
739 destVal, numLowBits, mvec, mcfi);