2 //***************************************************************************
9 // 10/15/01 - Vikram Adve - Created
10 //**************************************************************************/
13 #include "SparcInternals.h"
14 #include "SparcInstrSelectionSupport.h"
15 #include "llvm/Target/Sparc.h"
16 #include "llvm/CodeGen/InstrSelection.h"
17 #include "llvm/CodeGen/InstrSelectionSupport.h"
18 #include "llvm/CodeGen/MachineCodeForMethod.h"
19 #include "llvm/Function.h"
20 #include "llvm/Constants.h"
21 #include "llvm/DerivedTypes.h"
24 //************************ Internal Functions ******************************/
27 static inline MachineInstr*
28 CreateIntSetInstruction(int64_t C, Value* dest,
29 std::vector<TmpInstruction*>& tempVec)
32 uint64_t absC = (C >= 0)? C : -C;
33 if (absC > (unsigned int) ~0)
34 { // C does not fit in 32 bits
35 TmpInstruction* tmpReg = new TmpInstruction(Type::IntTy);
36 tempVec.push_back(tmpReg);
38 minstr = new MachineInstr(SETX);
39 minstr->SetMachineOperandConst(0, MachineOperand::MO_SignExtendedImmed, C);
40 minstr->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister, tmpReg,
42 minstr->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister,dest);
46 minstr = new MachineInstr(SETSW);
47 minstr->SetMachineOperandConst(0,MachineOperand::MO_SignExtendedImmed,C);
48 minstr->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister,dest);
54 static inline MachineInstr*
55 CreateUIntSetInstruction(uint64_t C, Value* dest,
56 std::vector<TmpInstruction*>& tempVec)
59 if (C > (unsigned int) ~0)
60 { // C does not fit in 32 bits
61 assert(dest->getType() == Type::ULongTy && "Sign extension problems");
62 TmpInstruction *tmpReg = new TmpInstruction(Type::IntTy);
63 tempVec.push_back(tmpReg);
65 minstr = new MachineInstr(SETX);
66 minstr->SetMachineOperandConst(0,MachineOperand::MO_SignExtendedImmed,C);
67 minstr->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister,
68 tmpReg, /*isdef*/ true);
69 minstr->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister,dest);
71 else if (dest->getType() == Type::ULongTy)
73 minstr = new MachineInstr(SETUW);
74 minstr->SetMachineOperandConst(0, MachineOperand::MO_UnextendedImmed, C);
75 minstr->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister,dest);
78 { // cast to signed type of the right length and use signed op (SETSW)
79 // to get correct sign extension
81 minstr = new MachineInstr(SETSW);
82 minstr->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister,dest);
84 switch (dest->getType()->getPrimitiveID())
87 minstr->SetMachineOperandConst(0,
88 MachineOperand::MO_SignExtendedImmed,
91 case Type::UShortTyID:
92 minstr->SetMachineOperandConst(0,
93 MachineOperand::MO_SignExtendedImmed,
97 minstr->SetMachineOperandConst(0,
98 MachineOperand::MO_SignExtendedImmed,
102 assert(0 && "Unexpected unsigned type");
110 //************************* External Classes *******************************/
112 //---------------------------------------------------------------------------
113 // class UltraSparcInstrInfo
116 // Information about individual instructions.
117 // Most information is stored in the SparcMachineInstrDesc array above.
118 // Other information is computed on demand, and most such functions
119 // default to member functions in base class MachineInstrInfo.
120 //---------------------------------------------------------------------------
123 UltraSparcInstrInfo::UltraSparcInstrInfo(const TargetMachine& tgt)
124 : MachineInstrInfo(tgt, SparcMachineInstrDesc,
125 /*descSize = */ NUM_TOTAL_OPCODES,
126 /*numRealOpCodes = */ NUM_REAL_OPCODES)
131 // Create an instruction sequence to put the constant `val' into
132 // the virtual register `dest'. `val' may be a Constant or a
133 // GlobalValue, viz., the constant address of a global variable or function.
134 // The generated instructions are returned in `minstrVec'.
135 // Any temp. registers (TmpInstruction) created are returned in `tempVec'.
138 UltraSparcInstrInfo::CreateCodeToLoadConst(Function *F, Value* val,
140 std::vector<MachineInstr*>&minstrVec,
141 std::vector<TmpInstruction*>& tempVec) const
143 MachineInstr* minstr;
145 assert(isa<Constant>(val) || isa<GlobalValue>(val) &&
146 "I only know about constant values and global addresses");
148 // Use a "set" instruction for known constants that can go in an integer reg.
149 // Use a "load" instruction for all other constants, in particular,
150 // floating point constants and addresses of globals.
152 const Type* valType = val->getType();
154 if (valType->isIntegral() || valType == Type::BoolTy)
156 if (ConstantUInt* uval = dyn_cast<ConstantUInt>(val))
158 uint64_t C = uval->getValue();
159 minstr = CreateUIntSetInstruction(C, dest, tempVec);
163 bool isValidConstant;
164 int64_t C = GetConstantValueAsSignedInt(val, isValidConstant);
165 assert(isValidConstant && "Unrecognized constant");
166 minstr = CreateIntSetInstruction(C, dest, tempVec);
168 minstrVec.push_back(minstr);
172 // Make an instruction sequence to load the constant, viz:
173 // SETX <addr-of-constant>, tmpReg, addrReg
174 // LOAD /*addr*/ addrReg, /*offset*/ 0, dest
175 // Only the SETX is needed if `val' is a GlobalValue, i.e,. it is
176 // itself a constant address. Otherwise, both are needed.
179 int64_t zeroOffset = 0; // to avoid ambiguity with (Value*) 0
181 TmpInstruction* tmpReg =
182 new TmpInstruction(PointerType::get(val->getType()), val);
183 tempVec.push_back(tmpReg);
185 if (isa<Constant>(val))
187 // Create another TmpInstruction for the hidden integer register
188 TmpInstruction* addrReg =
189 new TmpInstruction(PointerType::get(val->getType()), val);
190 tempVec.push_back(addrReg);
196 minstr = new MachineInstr(SETX);
197 minstr->SetMachineOperandVal(0, MachineOperand::MO_PCRelativeDisp, val);
198 minstr->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister,tmpReg,
200 minstr->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister,
202 minstrVec.push_back(minstr);
204 if (isa<Constant>(val))
206 // Make sure constant is emitted to constant pool in assembly code.
207 MachineCodeForMethod& mcinfo = MachineCodeForMethod::get(F);
208 mcinfo.addToConstantPool(cast<Constant>(val));
210 // Generate the load instruction
211 minstr = new MachineInstr(ChooseLoadInstruction(val->getType()));
212 minstr->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister,
214 minstr->SetMachineOperandConst(1,MachineOperand::MO_SignExtendedImmed,
216 minstr->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister,
218 minstrVec.push_back(minstr);
224 // Create an instruction sequence to copy an integer value `val'
225 // to a floating point value `dest' by copying to memory and back.
226 // val must be an integral type. dest must be a Float or Double.
227 // The generated instructions are returned in `minstrVec'.
228 // Any temp. registers (TmpInstruction) created are returned in `tempVec'.
231 UltraSparcInstrInfo::CreateCodeToCopyIntToFloat(Function *F,
234 std::vector<MachineInstr*>& minstrVec,
235 std::vector<TmpInstruction*>& tempVec,
236 TargetMachine& target) const
238 assert((val->getType()->isIntegral() || val->getType()->isPointerType())
239 && "Source type must be integral");
240 assert((dest->getType() == Type::FloatTy || dest->getType() == Type::DoubleTy)
241 && "Dest type must be float/double");
243 MachineCodeForMethod& mcinfo = MachineCodeForMethod::get(F);
244 int offset = mcinfo.allocateLocalVar(target, val);
246 // Store instruction stores `val' to [%fp+offset].
247 // The store and load opCodes are based on the value being copied, and
248 // they use integer and float types that accomodate the
249 // larger of the source type and the destination type:
250 // On SparcV9: int for float, long for double.
252 Type* tmpType = (dest->getType() == Type::FloatTy)? Type::IntTy
254 MachineInstr* store = new MachineInstr(ChooseStoreInstruction(tmpType));
255 store->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister, val);
256 store->SetMachineOperandReg(1, target.getRegInfo().getFramePointer());
257 store->SetMachineOperandConst(2,MachineOperand::MO_SignExtendedImmed, offset);
258 minstrVec.push_back(store);
260 // Load instruction loads [%fp+offset] to `dest'.
262 MachineInstr* load =new MachineInstr(ChooseLoadInstruction(dest->getType()));
263 load->SetMachineOperandReg(0, target.getRegInfo().getFramePointer());
264 load->SetMachineOperandConst(1, MachineOperand::MO_SignExtendedImmed,offset);
265 load->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister, dest);
266 minstrVec.push_back(load);
270 // Similarly, create an instruction sequence to copy an FP value
271 // `val' to an integer value `dest' by copying to memory and back.
272 // See the previous function for information about return values.
275 UltraSparcInstrInfo::CreateCodeToCopyFloatToInt(Function *F,
278 std::vector<MachineInstr*>& minstrVec,
279 std::vector<TmpInstruction*>& tempVec,
280 TargetMachine& target) const
282 assert((val->getType() ==Type::FloatTy || val->getType() ==Type::DoubleTy)
283 && "Source type must be float/double");
284 assert((dest->getType()->isIntegral() || dest->getType()->isPointerType())
285 && "Dest type must be integral");
287 MachineCodeForMethod& mcinfo = MachineCodeForMethod::get(F);
288 int offset = mcinfo.allocateLocalVar(target, val);
290 // Store instruction stores `val' to [%fp+offset].
291 // The store and load opCodes are based on the value being copied, and
292 // they use the integer type that matches the source type in size:
293 // On SparcV9: int for float, long for double.
295 Type* tmpType = (val->getType() == Type::FloatTy)? Type::IntTy
297 MachineInstr* store=new MachineInstr(ChooseStoreInstruction(val->getType()));
298 store->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister, val);
299 store->SetMachineOperandReg(1, target.getRegInfo().getFramePointer());
300 store->SetMachineOperandConst(2,MachineOperand::MO_SignExtendedImmed,offset);
301 minstrVec.push_back(store);
303 // Load instruction loads [%fp+offset] to `dest'.
305 MachineInstr* load = new MachineInstr(ChooseLoadInstruction(tmpType));
306 load->SetMachineOperandReg(0, target.getRegInfo().getFramePointer());
307 load->SetMachineOperandConst(1, MachineOperand::MO_SignExtendedImmed, offset);
308 load->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister, dest);
309 minstrVec.push_back(load);