1 //===-- SparcV9InstrInfo.cpp ------------------------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
12 #include "llvm/Constants.h"
13 #include "llvm/DerivedTypes.h"
14 #include "llvm/Function.h"
15 #include "llvm/iTerminators.h"
16 #include "llvm/CodeGen/InstrSelection.h"
17 #include "llvm/CodeGen/MachineConstantPool.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/CodeGen/MachineFunctionInfo.h"
20 #include "llvm/CodeGen/MachineCodeForInstruction.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "SparcV9Internals.h"
23 #include "SparcV9InstrSelectionSupport.h"
24 #include "SparcV9InstrInfo.h"
28 static const uint32_t MAXLO = (1 << 10) - 1; // set bits set by %lo(*)
29 static const uint32_t MAXSIMM = (1 << 12) - 1; // set bits in simm13 field of OR
31 //---------------------------------------------------------------------------
32 // Function ConvertConstantToIntType
34 // Function to get the value of an integral constant in the form
35 // that must be put into the machine register. The specified constant is
36 // interpreted as (i.e., converted if necessary to) the specified destination
37 // type. The result is always returned as an uint64_t, since the representation
38 // of int64_t and uint64_t are identical. The argument can be any known const.
40 // isValidConstant is set to true if a valid constant was found.
41 //---------------------------------------------------------------------------
44 SparcV9InstrInfo::ConvertConstantToIntType(const TargetMachine &target,
47 bool &isValidConstant) const
49 isValidConstant = false;
52 if (! destType->isIntegral() && ! isa<PointerType>(destType))
55 if (! isa<Constant>(V))
58 // ConstantPointerRef: no conversions needed: get value and return it
59 if (const ConstantPointerRef* CPR = dyn_cast<ConstantPointerRef>(V)) {
60 // A ConstantPointerRef is just a reference to GlobalValue.
61 isValidConstant = true; // may be overwritten by recursive call
62 return (CPR->isNullValue()? 0
63 : ConvertConstantToIntType(target, CPR->getValue(), destType,
67 // ConstantBool: no conversions needed: get value and return it
68 if (const ConstantBool *CB = dyn_cast<ConstantBool>(V)) {
69 isValidConstant = true;
70 return (uint64_t) CB->getValue();
73 // For other types of constants, some conversion may be needed.
74 // First, extract the constant operand according to its own type
75 if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(V))
76 switch(CE->getOpcode()) {
77 case Instruction::Cast: // recursively get the value as cast
78 C = ConvertConstantToIntType(target, CE->getOperand(0), CE->getType(),
81 default: // not simplifying other ConstantExprs
84 else if (const ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
85 isValidConstant = true;
86 C = CI->getRawValue();
88 else if (const ConstantFP *CFP = dyn_cast<ConstantFP>(V)) {
89 isValidConstant = true;
90 double fC = CFP->getValue();
91 C = (destType->isSigned()? (uint64_t) (int64_t) fC
95 // Now if a valid value was found, convert it to destType.
96 if (isValidConstant) {
97 unsigned opSize = target.getTargetData().getTypeSize(V->getType());
98 unsigned destSize = target.getTargetData().getTypeSize(destType);
99 uint64_t maskHi = (destSize < 8)? (1U << 8*destSize) - 1 : ~0;
100 assert(opSize <= 8 && destSize <= 8 && ">8-byte int type unexpected");
102 if (destType->isSigned()) {
103 if (opSize > destSize) // operand is larger than dest:
104 C = C & maskHi; // mask high bits
106 if (opSize > destSize ||
107 (opSize == destSize && ! V->getType()->isSigned()))
108 if (C & (1U << (8*destSize - 1)))
109 C = C | ~maskHi; // sign-extend from destSize to 64 bits
112 if (opSize > destSize || (V->getType()->isSigned() && destSize < 8)) {
113 // operand is larger than dest,
114 // OR both are equal but smaller than the full register size
115 // AND operand is signed, so it may have extra sign bits:
126 //----------------------------------------------------------------------------
127 // Function: CreateSETUWConst
129 // Set a 32-bit unsigned constant in the register `dest', using
130 // SETHI, OR in the worst case. This function correctly emulates
131 // the SETUW pseudo-op for SPARC v9 (if argument isSigned == false).
133 // The isSigned=true case is used to implement SETSW without duplicating code.
135 // Optimize some common cases:
136 // (1) Small value that fits in simm13 field of OR: don't need SETHI.
137 // (2) isSigned = true and C is a small negative signed value, i.e.,
138 // high bits are 1, and the remaining bits fit in simm13(OR).
139 //----------------------------------------------------------------------------
142 CreateSETUWConst(const TargetMachine& target, uint32_t C,
143 Instruction* dest, std::vector<MachineInstr*>& mvec,
144 bool isSigned = false)
146 MachineInstr *miSETHI = NULL, *miOR = NULL;
148 // In order to get efficient code, we should not generate the SETHI if
149 // all high bits are 1 (i.e., this is a small signed value that fits in
150 // the simm13 field of OR). So we check for and handle that case specially.
151 // NOTE: The value C = 0x80000000 is bad: sC < 0 *and* -sC < 0.
152 // In fact, sC == -sC, so we have to check for this explicitly.
153 int32_t sC = (int32_t) C;
154 bool smallNegValue =isSigned && sC < 0 && sC != -sC && -sC < (int32_t)MAXSIMM;
156 // Set the high 22 bits in dest if non-zero and simm13 field of OR not enough
157 if (!smallNegValue && (C & ~MAXLO) && C > MAXSIMM) {
158 miSETHI = BuildMI(V9::SETHI, 2).addZImm(C).addRegDef(dest);
159 miSETHI->setOperandHi32(0);
160 mvec.push_back(miSETHI);
163 // Set the low 10 or 12 bits in dest. This is necessary if no SETHI
164 // was generated, or if the low 10 bits are non-zero.
165 if (miSETHI==NULL || C & MAXLO) {
167 // unsigned value with high-order bits set using SETHI
168 miOR = BuildMI(V9::ORi,3).addReg(dest).addZImm(C).addRegDef(dest);
169 miOR->setOperandLo32(1);
171 // unsigned or small signed value that fits in simm13 field of OR
172 assert(smallNegValue || (C & ~MAXSIMM) == 0);
173 miOR = BuildMI(V9::ORi, 3).addMReg(target.getRegInfo()
175 .addSImm(sC).addRegDef(dest);
177 mvec.push_back(miOR);
180 assert((miSETHI || miOR) && "Oops, no code was generated!");
184 //----------------------------------------------------------------------------
185 // Function: CreateSETSWConst
187 // Set a 32-bit signed constant in the register `dest', with sign-extension
188 // to 64 bits. This uses SETHI, OR, SRA in the worst case.
189 // This function correctly emulates the SETSW pseudo-op for SPARC v9.
191 // Optimize the same cases as SETUWConst, plus:
192 // (1) SRA is not needed for positive or small negative values.
193 //----------------------------------------------------------------------------
196 CreateSETSWConst(const TargetMachine& target, int32_t C,
197 Instruction* dest, std::vector<MachineInstr*>& mvec)
199 // Set the low 32 bits of dest
200 CreateSETUWConst(target, (uint32_t) C, dest, mvec, /*isSigned*/true);
202 // Sign-extend to the high 32 bits if needed.
203 // NOTE: The value C = 0x80000000 is bad: -C == C and so -C is < MAXSIMM
204 if (C < 0 && (C == -C || -C > (int32_t) MAXSIMM))
205 mvec.push_back(BuildMI(V9::SRAi5,3).addReg(dest).addZImm(0).addRegDef(dest));
209 //----------------------------------------------------------------------------
210 // Function: CreateSETXConst
212 // Set a 64-bit signed or unsigned constant in the register `dest'.
213 // Use SETUWConst for each 32 bit word, plus a left-shift-by-32 in between.
214 // This function correctly emulates the SETX pseudo-op for SPARC v9.
216 // Optimize the same cases as SETUWConst for each 32 bit word.
217 //----------------------------------------------------------------------------
220 CreateSETXConst(const TargetMachine& target, uint64_t C,
221 Instruction* tmpReg, Instruction* dest,
222 std::vector<MachineInstr*>& mvec)
224 assert(C > (unsigned int) ~0 && "Use SETUW/SETSW for 32-bit values!");
228 // Code to set the upper 32 bits of the value in register `tmpReg'
229 CreateSETUWConst(target, (C >> 32), tmpReg, mvec);
231 // Shift tmpReg left by 32 bits
232 mvec.push_back(BuildMI(V9::SLLXi6, 3).addReg(tmpReg).addZImm(32)
235 // Code to set the low 32 bits of the value in register `dest'
236 CreateSETUWConst(target, C, dest, mvec);
238 // dest = OR(tmpReg, dest)
239 mvec.push_back(BuildMI(V9::ORr,3).addReg(dest).addReg(tmpReg).addRegDef(dest));
243 //----------------------------------------------------------------------------
244 // Function: CreateSETUWLabel
246 // Set a 32-bit constant (given by a symbolic label) in the register `dest'.
247 //----------------------------------------------------------------------------
250 CreateSETUWLabel(const TargetMachine& target, Value* val,
251 Instruction* dest, std::vector<MachineInstr*>& mvec)
255 // Set the high 22 bits in dest
256 MI = BuildMI(V9::SETHI, 2).addReg(val).addRegDef(dest);
257 MI->setOperandHi32(0);
260 // Set the low 10 bits in dest
261 MI = BuildMI(V9::ORr, 3).addReg(dest).addReg(val).addRegDef(dest);
262 MI->setOperandLo32(1);
267 //----------------------------------------------------------------------------
268 // Function: CreateSETXLabel
270 // Set a 64-bit constant (given by a symbolic label) in the register `dest'.
271 //----------------------------------------------------------------------------
274 CreateSETXLabel(const TargetMachine& target,
275 Value* val, Instruction* tmpReg, Instruction* dest,
276 std::vector<MachineInstr*>& mvec)
278 assert(isa<Constant>(val) || isa<GlobalValue>(val) &&
279 "I only know about constant values and global addresses");
283 MI = BuildMI(V9::SETHI, 2).addPCDisp(val).addRegDef(tmpReg);
284 MI->setOperandHi64(0);
287 MI = BuildMI(V9::ORi, 3).addReg(tmpReg).addPCDisp(val).addRegDef(tmpReg);
288 MI->setOperandLo64(1);
291 mvec.push_back(BuildMI(V9::SLLXi6, 3).addReg(tmpReg).addZImm(32)
293 MI = BuildMI(V9::SETHI, 2).addPCDisp(val).addRegDef(dest);
294 MI->setOperandHi32(0);
297 MI = BuildMI(V9::ORr, 3).addReg(dest).addReg(tmpReg).addRegDef(dest);
300 MI = BuildMI(V9::ORi, 3).addReg(dest).addPCDisp(val).addRegDef(dest);
301 MI->setOperandLo32(1);
306 //----------------------------------------------------------------------------
307 // Function: CreateUIntSetInstruction
309 // Create code to Set an unsigned constant in the register `dest'.
310 // Uses CreateSETUWConst, CreateSETSWConst or CreateSETXConst as needed.
311 // CreateSETSWConst is an optimization for the case that the unsigned value
312 // has all ones in the 33 high bits (so that sign-extension sets them all).
313 //----------------------------------------------------------------------------
316 CreateUIntSetInstruction(const TargetMachine& target,
317 uint64_t C, Instruction* dest,
318 std::vector<MachineInstr*>& mvec,
319 MachineCodeForInstruction& mcfi)
321 static const uint64_t lo32 = (uint32_t) ~0;
322 if (C <= lo32) // High 32 bits are 0. Set low 32 bits.
323 CreateSETUWConst(target, (uint32_t) C, dest, mvec);
324 else if ((C & ~lo32) == ~lo32 && (C & (1U << 31))) {
325 // All high 33 (not 32) bits are 1s: sign-extension will take care
326 // of high 32 bits, so use the sequence for signed int
327 CreateSETSWConst(target, (int32_t) C, dest, mvec);
328 } else if (C > lo32) {
329 // C does not fit in 32 bits
330 TmpInstruction* tmpReg = new TmpInstruction(mcfi, Type::IntTy);
331 CreateSETXConst(target, C, tmpReg, dest, mvec);
336 //----------------------------------------------------------------------------
337 // Function: CreateIntSetInstruction
339 // Create code to Set a signed constant in the register `dest'.
340 // Really the same as CreateUIntSetInstruction.
341 //----------------------------------------------------------------------------
344 CreateIntSetInstruction(const TargetMachine& target,
345 int64_t C, Instruction* dest,
346 std::vector<MachineInstr*>& mvec,
347 MachineCodeForInstruction& mcfi)
349 CreateUIntSetInstruction(target, (uint64_t) C, dest, mvec, mcfi);
353 //---------------------------------------------------------------------------
354 // Create a table of LLVM opcode -> max. immediate constant likely to
355 // be usable for that operation.
356 //---------------------------------------------------------------------------
358 // Entry == 0 ==> no immediate constant field exists at all.
359 // Entry > 0 ==> abs(immediate constant) <= Entry
361 std::vector<int> MaxConstantsTable(Instruction::OtherOpsEnd);
364 MaxConstantForInstr(unsigned llvmOpCode)
366 int modelOpCode = -1;
368 if (llvmOpCode >= Instruction::BinaryOpsBegin &&
369 llvmOpCode < Instruction::BinaryOpsEnd)
370 modelOpCode = V9::ADDi;
373 case Instruction::Ret: modelOpCode = V9::JMPLCALLi; break;
375 case Instruction::Malloc:
376 case Instruction::Alloca:
377 case Instruction::GetElementPtr:
378 case Instruction::PHI:
379 case Instruction::Cast:
380 case Instruction::Call: modelOpCode = V9::ADDi; break;
382 case Instruction::Shl:
383 case Instruction::Shr: modelOpCode = V9::SLLXi6; break;
388 return (modelOpCode < 0)? 0: SparcV9MachineInstrDesc[modelOpCode].maxImmedConst;
392 InitializeMaxConstantsTable()
395 assert(MaxConstantsTable.size() == Instruction::OtherOpsEnd &&
396 "assignments below will be illegal!");
397 for (op = Instruction::TermOpsBegin; op < Instruction::TermOpsEnd; ++op)
398 MaxConstantsTable[op] = MaxConstantForInstr(op);
399 for (op = Instruction::BinaryOpsBegin; op < Instruction::BinaryOpsEnd; ++op)
400 MaxConstantsTable[op] = MaxConstantForInstr(op);
401 for (op = Instruction::MemoryOpsBegin; op < Instruction::MemoryOpsEnd; ++op)
402 MaxConstantsTable[op] = MaxConstantForInstr(op);
403 for (op = Instruction::OtherOpsBegin; op < Instruction::OtherOpsEnd; ++op)
404 MaxConstantsTable[op] = MaxConstantForInstr(op);
408 //---------------------------------------------------------------------------
409 // class SparcV9InstrInfo
412 // Information about individual instructions.
413 // Most information is stored in the SparcV9MachineInstrDesc array above.
414 // Other information is computed on demand, and most such functions
415 // default to member functions in base class TargetInstrInfo.
416 //---------------------------------------------------------------------------
418 SparcV9InstrInfo::SparcV9InstrInfo()
419 : TargetInstrInfo(SparcV9MachineInstrDesc, V9::NUM_TOTAL_OPCODES) {
420 InitializeMaxConstantsTable();
424 SparcV9InstrInfo::ConstantMayNotFitInImmedField(const Constant* CV,
425 const Instruction* I) const
427 if (I->getOpcode() >= MaxConstantsTable.size()) // user-defined op (or bug!)
430 if (isa<ConstantPointerNull>(CV)) // can always use %g0
433 if (isa<SwitchInst>(I)) // Switch instructions will be lowered!
436 if (const ConstantInt* CI = dyn_cast<ConstantInt>(CV))
437 return labs((int64_t)CI->getRawValue()) > MaxConstantsTable[I->getOpcode()];
439 if (isa<ConstantBool>(CV))
440 return 1 > MaxConstantsTable[I->getOpcode()];
446 // Create an instruction sequence to put the constant `val' into
447 // the virtual register `dest'. `val' may be a Constant or a
448 // GlobalValue, viz., the constant address of a global variable or function.
449 // The generated instructions are returned in `mvec'.
450 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
451 // Any stack space required is allocated via MachineFunction.
454 SparcV9InstrInfo::CreateCodeToLoadConst(const TargetMachine& target,
458 std::vector<MachineInstr*>& mvec,
459 MachineCodeForInstruction& mcfi) const
461 assert(isa<Constant>(val) || isa<GlobalValue>(val) &&
462 "I only know about constant values and global addresses");
464 // Use a "set" instruction for known constants or symbolic constants (labels)
465 // that can go in an integer reg.
466 // We have to use a "load" instruction for all other constants,
467 // in particular, floating point constants.
469 const Type* valType = val->getType();
471 // A ConstantPointerRef is just a reference to GlobalValue.
472 while (isa<ConstantPointerRef>(val))
473 val = cast<ConstantPointerRef>(val)->getValue();
475 if (isa<GlobalValue>(val)) {
476 TmpInstruction* tmpReg =
477 new TmpInstruction(mcfi, PointerType::get(val->getType()), val);
478 CreateSETXLabel(target, val, tmpReg, dest, mvec);
483 uint64_t C = ConvertConstantToIntType(target, val, dest->getType(), isValid);
485 if (dest->getType()->isSigned())
486 CreateUIntSetInstruction(target, C, dest, mvec, mcfi);
488 CreateIntSetInstruction(target, (int64_t) C, dest, mvec, mcfi);
491 // Make an instruction sequence to load the constant, viz:
492 // SETX <addr-of-constant>, tmpReg, addrReg
493 // LOAD /*addr*/ addrReg, /*offset*/ 0, dest
495 // First, create a tmp register to be used by the SETX sequence.
496 TmpInstruction* tmpReg =
497 new TmpInstruction(mcfi, PointerType::get(val->getType()));
499 // Create another TmpInstruction for the address register
500 TmpInstruction* addrReg =
501 new TmpInstruction(mcfi, PointerType::get(val->getType()));
503 // Get the constant pool index for this constant
504 MachineConstantPool *CP = MachineFunction::get(F).getConstantPool();
505 Constant *C = cast<Constant>(val);
506 unsigned CPI = CP->getConstantPoolIndex(C);
508 // Put the address of the constant into a register
511 MI = BuildMI(V9::SETHI, 2).addConstantPoolIndex(CPI).addRegDef(tmpReg);
512 MI->setOperandHi64(0);
515 MI = BuildMI(V9::ORi, 3).addReg(tmpReg).addConstantPoolIndex(CPI)
517 MI->setOperandLo64(1);
520 mvec.push_back(BuildMI(V9::SLLXi6, 3).addReg(tmpReg).addZImm(32)
522 MI = BuildMI(V9::SETHI, 2).addConstantPoolIndex(CPI).addRegDef(addrReg);
523 MI->setOperandHi32(0);
526 MI = BuildMI(V9::ORr, 3).addReg(addrReg).addReg(tmpReg).addRegDef(addrReg);
529 MI = BuildMI(V9::ORi, 3).addReg(addrReg).addConstantPoolIndex(CPI)
531 MI->setOperandLo32(1);
534 // Now load the constant from out ConstantPool label
535 unsigned Opcode = ChooseLoadInstruction(val->getType());
536 Opcode = convertOpcodeFromRegToImm(Opcode);
537 mvec.push_back(BuildMI(Opcode, 3)
538 .addReg(addrReg).addSImm((int64_t)0).addRegDef(dest));
543 // Create an instruction sequence to copy an integer register `val'
544 // to a floating point register `dest' by copying to memory and back.
545 // val must be an integral type. dest must be a Float or Double.
546 // The generated instructions are returned in `mvec'.
547 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
548 // Any stack space required is allocated via MachineFunction.
551 SparcV9InstrInfo::CreateCodeToCopyIntToFloat(const TargetMachine& target,
555 std::vector<MachineInstr*>& mvec,
556 MachineCodeForInstruction& mcfi) const
558 assert((val->getType()->isIntegral() || isa<PointerType>(val->getType()))
559 && "Source type must be integral (integer or bool) or pointer");
560 assert(dest->getType()->isFloatingPoint()
561 && "Dest type must be float/double");
563 // Get a stack slot to use for the copy
564 int offset = MachineFunction::get(F).getInfo()->allocateLocalVar(val);
566 // Get the size of the source value being copied.
567 size_t srcSize = target.getTargetData().getTypeSize(val->getType());
569 // Store instruction stores `val' to [%fp+offset].
570 // The store and load opCodes are based on the size of the source value.
571 // If the value is smaller than 32 bits, we must sign- or zero-extend it
572 // to 32 bits since the load-float will load 32 bits.
573 // Note that the store instruction is the same for signed and unsigned ints.
574 const Type* storeType = (srcSize <= 4)? Type::IntTy : Type::LongTy;
575 Value* storeVal = val;
576 if (srcSize < target.getTargetData().getTypeSize(Type::FloatTy)) {
577 // sign- or zero-extend respectively
578 storeVal = new TmpInstruction(mcfi, storeType, val);
579 if (val->getType()->isSigned())
580 CreateSignExtensionInstructions(target, F, val, storeVal, 8*srcSize,
583 CreateZeroExtensionInstructions(target, F, val, storeVal, 8*srcSize,
587 unsigned FPReg = target.getRegInfo().getFramePointer();
588 unsigned StoreOpcode = ChooseStoreInstruction(storeType);
589 StoreOpcode = convertOpcodeFromRegToImm(StoreOpcode);
590 mvec.push_back(BuildMI(StoreOpcode, 3)
591 .addReg(storeVal).addMReg(FPReg).addSImm(offset));
593 // Load instruction loads [%fp+offset] to `dest'.
594 // The type of the load opCode is the floating point type that matches the
595 // stored type in size:
596 // On SparcV9: float for int or smaller, double for long.
598 const Type* loadType = (srcSize <= 4)? Type::FloatTy : Type::DoubleTy;
599 unsigned LoadOpcode = ChooseLoadInstruction(loadType);
600 LoadOpcode = convertOpcodeFromRegToImm(LoadOpcode);
601 mvec.push_back(BuildMI(LoadOpcode, 3)
602 .addMReg(FPReg).addSImm(offset).addRegDef(dest));
605 // Similarly, create an instruction sequence to copy an FP register
606 // `val' to an integer register `dest' by copying to memory and back.
607 // The generated instructions are returned in `mvec'.
608 // Any temp. virtual registers (TmpInstruction) created are recorded in mcfi.
609 // Temporary stack space required is allocated via MachineFunction.
612 SparcV9InstrInfo::CreateCodeToCopyFloatToInt(const TargetMachine& target,
616 std::vector<MachineInstr*>& mvec,
617 MachineCodeForInstruction& mcfi) const
619 const Type* opTy = val->getType();
620 const Type* destTy = dest->getType();
622 assert(opTy->isFloatingPoint() && "Source type must be float/double");
623 assert((destTy->isIntegral() || isa<PointerType>(destTy))
624 && "Dest type must be integer, bool or pointer");
626 // FIXME: For now, we allocate permanent space because the stack frame
627 // manager does not allow locals to be allocated (e.g., for alloca) after
628 // a temp is allocated!
630 int offset = MachineFunction::get(F).getInfo()->allocateLocalVar(val);
632 unsigned FPReg = target.getRegInfo().getFramePointer();
634 // Store instruction stores `val' to [%fp+offset].
635 // The store opCode is based only the source value being copied.
637 unsigned StoreOpcode = ChooseStoreInstruction(opTy);
638 StoreOpcode = convertOpcodeFromRegToImm(StoreOpcode);
639 mvec.push_back(BuildMI(StoreOpcode, 3)
640 .addReg(val).addMReg(FPReg).addSImm(offset));
642 // Load instruction loads [%fp+offset] to `dest'.
643 // The type of the load opCode is the integer type that matches the
644 // source type in size:
645 // On SparcV9: int for float, long for double.
646 // Note that we *must* use signed loads even for unsigned dest types, to
647 // ensure correct sign-extension for UByte, UShort or UInt:
649 const Type* loadTy = (opTy == Type::FloatTy)? Type::IntTy : Type::LongTy;
650 unsigned LoadOpcode = ChooseLoadInstruction(loadTy);
651 LoadOpcode = convertOpcodeFromRegToImm(LoadOpcode);
652 mvec.push_back(BuildMI(LoadOpcode, 3).addMReg(FPReg)
653 .addSImm(offset).addRegDef(dest));
657 // Create instruction(s) to copy src to dest, for arbitrary types
658 // The generated instructions are returned in `mvec'.
659 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
660 // Any stack space required is allocated via MachineFunction.
663 SparcV9InstrInfo::CreateCopyInstructionsByType(const TargetMachine& target,
667 std::vector<MachineInstr*>& mvec,
668 MachineCodeForInstruction& mcfi) const
670 bool loadConstantToReg = false;
672 const Type* resultType = dest->getType();
674 MachineOpCode opCode = ChooseAddInstructionByType(resultType);
675 if (opCode == V9::INVALID_OPCODE) {
676 assert(0 && "Unsupported result type in CreateCopyInstructionsByType()");
680 // if `src' is a constant that doesn't fit in the immed field or if it is
681 // a global variable (i.e., a constant address), generate a load
682 // instruction instead of an add
684 if (isa<Constant>(src)) {
685 unsigned int machineRegNum;
687 MachineOperand::MachineOperandType opType =
688 ChooseRegOrImmed(src, opCode, target, /*canUseImmed*/ true,
689 machineRegNum, immedValue);
691 if (opType == MachineOperand::MO_VirtualRegister)
692 loadConstantToReg = true;
694 else if (isa<GlobalValue>(src))
695 loadConstantToReg = true;
697 if (loadConstantToReg) {
698 // `src' is constant and cannot fit in immed field for the ADD
699 // Insert instructions to "load" the constant into a register
700 target.getInstrInfo().CreateCodeToLoadConst(target, F, src, dest,
703 // Create a reg-to-reg copy instruction for the given type:
704 // -- For FP values, create a FMOVS or FMOVD instruction
705 // -- For non-FP values, create an add-with-0 instruction (opCode as above)
706 // Make `src' the second operand, in case it is a small constant!
709 if (resultType->isFloatingPoint())
710 MI = (BuildMI(resultType == Type::FloatTy? V9::FMOVS : V9::FMOVD, 2)
711 .addReg(src).addRegDef(dest));
713 const Type* Ty =isa<PointerType>(resultType)? Type::ULongTy :resultType;
714 MI = (BuildMI(opCode, 3)
715 .addSImm((int64_t) 0).addReg(src).addRegDef(dest));
722 // Helper function for sign-extension and zero-extension.
723 // For SPARC v9, we sign-extend the given operand using SLL; SRA/SRL.
725 CreateBitExtensionInstructions(bool signExtend,
726 const TargetMachine& target,
730 unsigned int numLowBits,
731 std::vector<MachineInstr*>& mvec,
732 MachineCodeForInstruction& mcfi)
736 assert(numLowBits <= 32 && "Otherwise, nothing should be done here!");
738 if (numLowBits < 32) {
739 // SLL is needed since operand size is < 32 bits.
740 TmpInstruction *tmpI = new TmpInstruction(mcfi, destVal->getType(),
741 srcVal, destVal, "make32");
742 mvec.push_back(BuildMI(V9::SLLXi6, 3).addReg(srcVal)
743 .addZImm(32-numLowBits).addRegDef(tmpI));
747 mvec.push_back(BuildMI(signExtend? V9::SRAi5 : V9::SRLi5, 3)
748 .addReg(srcVal).addZImm(32-numLowBits).addRegDef(destVal));
752 // Create instruction sequence to produce a sign-extended register value
753 // from an arbitrary-sized integer value (sized in bits, not bytes).
754 // The generated instructions are returned in `mvec'.
755 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
756 // Any stack space required is allocated via MachineFunction.
759 SparcV9InstrInfo::CreateSignExtensionInstructions(
760 const TargetMachine& target,
764 unsigned int numLowBits,
765 std::vector<MachineInstr*>& mvec,
766 MachineCodeForInstruction& mcfi) const
768 CreateBitExtensionInstructions(/*signExtend*/ true, target, F, srcVal,
769 destVal, numLowBits, mvec, mcfi);
773 // Create instruction sequence to produce a zero-extended register value
774 // from an arbitrary-sized integer value (sized in bits, not bytes).
775 // For SPARC v9, we sign-extend the given operand using SLL; SRL.
776 // The generated instructions are returned in `mvec'.
777 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
778 // Any stack space required is allocated via MachineFunction.
781 SparcV9InstrInfo::CreateZeroExtensionInstructions(
782 const TargetMachine& target,
786 unsigned int numLowBits,
787 std::vector<MachineInstr*>& mvec,
788 MachineCodeForInstruction& mcfi) const
790 CreateBitExtensionInstructions(/*signExtend*/ false, target, F, srcVal,
791 destVal, numLowBits, mvec, mcfi);
794 } // End llvm namespace