1 //===-- SparcInstrInfo.cpp ------------------------------------------------===//
3 //===----------------------------------------------------------------------===//
5 #include "SparcInternals.h"
6 #include "SparcInstrSelectionSupport.h"
7 #include "llvm/CodeGen/InstrSelection.h"
8 #include "llvm/CodeGen/InstrSelectionSupport.h"
9 #include "llvm/CodeGen/MachineFunction.h"
10 #include "llvm/CodeGen/MachineFunctionInfo.h"
11 #include "llvm/CodeGen/MachineCodeForInstruction.h"
12 #include "llvm/CodeGen/MachineInstrBuilder.h"
13 #include "llvm/Function.h"
14 #include "llvm/Constants.h"
15 #include "llvm/DerivedTypes.h"
18 static const uint32_t MAXLO = (1 << 10) - 1; // set bits set by %lo(*)
19 static const uint32_t MAXSIMM = (1 << 12) - 1; // set bits in simm13 field of OR
22 //---------------------------------------------------------------------------
23 // Function GetConstantValueAsUnsignedInt
24 // Function GetConstantValueAsSignedInt
26 // Convenience functions to get the value of an integral constant, for an
27 // appropriate integer or non-integer type that can be held in a signed
28 // or unsigned integer respectively. The type of the argument must be
30 // Signed or unsigned integer
34 // isValidConstant is set to true if a valid constant was found.
35 //---------------------------------------------------------------------------
38 GetConstantValueAsUnsignedInt(const Value *V,
39 bool &isValidConstant)
41 isValidConstant = true;
44 if (const ConstantBool *CB = dyn_cast<ConstantBool>(V))
45 return (int64_t)CB->getValue();
46 else if (const ConstantSInt *CS = dyn_cast<ConstantSInt>(V))
47 return (uint64_t)CS->getValue();
48 else if (const ConstantUInt *CU = dyn_cast<ConstantUInt>(V))
49 return CU->getValue();
51 isValidConstant = false;
56 GetConstantValueAsSignedInt(const Value *V, bool &isValidConstant)
58 uint64_t C = GetConstantValueAsUnsignedInt(V, isValidConstant);
59 if (isValidConstant) {
60 if (V->getType()->isSigned() || C < INT64_MAX) // safe to cast to signed
63 isValidConstant = false;
69 //----------------------------------------------------------------------------
70 // Function: CreateSETUWConst
72 // Set a 32-bit unsigned constant in the register `dest', using
73 // SETHI, OR in the worst case. This function correctly emulates
74 // the SETUW pseudo-op for SPARC v9 (if argument isSigned == false).
76 // The isSigned=true case is used to implement SETSW without duplicating code.
78 // Optimize some common cases:
79 // (1) Small value that fits in simm13 field of OR: don't need SETHI.
80 // (2) isSigned = true and C is a small negative signed value, i.e.,
81 // high bits are 1, and the remaining bits fit in simm13(OR).
82 //----------------------------------------------------------------------------
85 CreateSETUWConst(const TargetMachine& target, uint32_t C,
86 Instruction* dest, std::vector<MachineInstr*>& mvec,
87 bool isSigned = false)
89 MachineInstr *miSETHI = NULL, *miOR = NULL;
91 // In order to get efficient code, we should not generate the SETHI if
92 // all high bits are 1 (i.e., this is a small signed value that fits in
93 // the simm13 field of OR). So we check for and handle that case specially.
94 // NOTE: The value C = 0x80000000 is bad: sC < 0 *and* -sC < 0.
95 // In fact, sC == -sC, so we have to check for this explicitly.
96 int32_t sC = (int32_t) C;
97 bool smallNegValue =isSigned && sC < 0 && sC != -sC && -sC < (int32_t)MAXSIMM;
99 // Set the high 22 bits in dest if non-zero and simm13 field of OR not enough
100 if (!smallNegValue && (C & ~MAXLO) && C > MAXSIMM) {
101 miSETHI = BuildMI(V9::SETHI, 2).addZImm(C).addRegDef(dest);
102 miSETHI->setOperandHi32(0);
103 mvec.push_back(miSETHI);
106 // Set the low 10 or 12 bits in dest. This is necessary if no SETHI
107 // was generated, or if the low 10 bits are non-zero.
108 if (miSETHI==NULL || C & MAXLO) {
110 // unsigned value with high-order bits set using SETHI
111 miOR = BuildMI(V9::OR,3).addReg(dest).addZImm(C).addRegDef(dest);
112 miOR->setOperandLo32(1);
114 // unsigned or small signed value that fits in simm13 field of OR
115 assert(smallNegValue || (C & ~MAXSIMM) == 0);
116 miOR = BuildMI(V9::OR, 3).addMReg(target.getRegInfo()
118 .addSImm(sC).addRegDef(dest);
120 mvec.push_back(miOR);
123 assert((miSETHI || miOR) && "Oops, no code was generated!");
127 //----------------------------------------------------------------------------
128 // Function: CreateSETSWConst
130 // Set a 32-bit signed constant in the register `dest', with sign-extension
131 // to 64 bits. This uses SETHI, OR, SRA in the worst case.
132 // This function correctly emulates the SETSW pseudo-op for SPARC v9.
134 // Optimize the same cases as SETUWConst, plus:
135 // (1) SRA is not needed for positive or small negative values.
136 //----------------------------------------------------------------------------
139 CreateSETSWConst(const TargetMachine& target, int32_t C,
140 Instruction* dest, std::vector<MachineInstr*>& mvec)
142 // Set the low 32 bits of dest
143 CreateSETUWConst(target, (uint32_t) C, dest, mvec, /*isSigned*/true);
145 // Sign-extend to the high 32 bits if needed.
146 // NOTE: The value C = 0x80000000 is bad: -C == C and so -C is < MAXSIMM
147 if (C < 0 && (C == -C || -C > (int32_t) MAXSIMM))
148 mvec.push_back(BuildMI(V9::SRA, 3).addReg(dest).addZImm(0).addRegDef(dest));
152 //----------------------------------------------------------------------------
153 // Function: CreateSETXConst
155 // Set a 64-bit signed or unsigned constant in the register `dest'.
156 // Use SETUWConst for each 32 bit word, plus a left-shift-by-32 in between.
157 // This function correctly emulates the SETX pseudo-op for SPARC v9.
159 // Optimize the same cases as SETUWConst for each 32 bit word.
160 //----------------------------------------------------------------------------
163 CreateSETXConst(const TargetMachine& target, uint64_t C,
164 Instruction* tmpReg, Instruction* dest,
165 std::vector<MachineInstr*>& mvec)
167 assert(C > (unsigned int) ~0 && "Use SETUW/SETSW for 32-bit values!");
171 // Code to set the upper 32 bits of the value in register `tmpReg'
172 CreateSETUWConst(target, (C >> 32), tmpReg, mvec);
174 // Shift tmpReg left by 32 bits
175 mvec.push_back(BuildMI(V9::SLLX, 3).addReg(tmpReg).addZImm(32)
178 // Code to set the low 32 bits of the value in register `dest'
179 CreateSETUWConst(target, C, dest, mvec);
181 // dest = OR(tmpReg, dest)
182 mvec.push_back(BuildMI(V9::OR,3).addReg(dest).addReg(tmpReg).addRegDef(dest));
186 //----------------------------------------------------------------------------
187 // Function: CreateSETUWLabel
189 // Set a 32-bit constant (given by a symbolic label) in the register `dest'.
190 //----------------------------------------------------------------------------
193 CreateSETUWLabel(const TargetMachine& target, Value* val,
194 Instruction* dest, std::vector<MachineInstr*>& mvec)
198 // Set the high 22 bits in dest
199 MI = BuildMI(V9::SETHI, 2).addReg(val).addRegDef(dest);
200 MI->setOperandHi32(0);
203 // Set the low 10 bits in dest
204 MI = BuildMI(V9::OR, 3).addReg(dest).addReg(val).addRegDef(dest);
205 MI->setOperandLo32(1);
210 //----------------------------------------------------------------------------
211 // Function: CreateSETXLabel
213 // Set a 64-bit constant (given by a symbolic label) in the register `dest'.
214 //----------------------------------------------------------------------------
217 CreateSETXLabel(const TargetMachine& target,
218 Value* val, Instruction* tmpReg, Instruction* dest,
219 std::vector<MachineInstr*>& mvec)
221 assert(isa<Constant>(val) || isa<GlobalValue>(val) &&
222 "I only know about constant values and global addresses");
226 MI = BuildMI(V9::SETHI, 2).addPCDisp(val).addRegDef(tmpReg);
227 MI->setOperandHi64(0);
230 MI = BuildMI(V9::OR, 3).addReg(tmpReg).addPCDisp(val).addRegDef(tmpReg);
231 MI->setOperandLo64(1);
234 mvec.push_back(BuildMI(V9::SLLX, 3).addReg(tmpReg).addZImm(32)
236 MI = BuildMI(V9::SETHI, 2).addPCDisp(val).addRegDef(dest);
237 MI->setOperandHi32(0);
240 MI = BuildMI(V9::OR, 3).addReg(dest).addReg(tmpReg).addRegDef(dest);
243 MI = BuildMI(V9::OR, 3).addReg(dest).addPCDisp(val).addRegDef(dest);
244 MI->setOperandLo32(1);
249 //----------------------------------------------------------------------------
250 // Function: CreateUIntSetInstruction
252 // Create code to Set an unsigned constant in the register `dest'.
253 // Uses CreateSETUWConst, CreateSETSWConst or CreateSETXConst as needed.
254 // CreateSETSWConst is an optimization for the case that the unsigned value
255 // has all ones in the 33 high bits (so that sign-extension sets them all).
256 //----------------------------------------------------------------------------
259 CreateUIntSetInstruction(const TargetMachine& target,
260 uint64_t C, Instruction* dest,
261 std::vector<MachineInstr*>& mvec,
262 MachineCodeForInstruction& mcfi)
264 static const uint64_t lo32 = (uint32_t) ~0;
265 if (C <= lo32) // High 32 bits are 0. Set low 32 bits.
266 CreateSETUWConst(target, (uint32_t) C, dest, mvec);
267 else if ((C & ~lo32) == ~lo32 && (C & (1 << 31))) {
268 // All high 33 (not 32) bits are 1s: sign-extension will take care
269 // of high 32 bits, so use the sequence for signed int
270 CreateSETSWConst(target, (int32_t) C, dest, mvec);
271 } else if (C > lo32) {
272 // C does not fit in 32 bits
273 TmpInstruction* tmpReg = new TmpInstruction(Type::IntTy);
274 mcfi.addTemp(tmpReg);
275 CreateSETXConst(target, C, tmpReg, dest, mvec);
280 //----------------------------------------------------------------------------
281 // Function: CreateIntSetInstruction
283 // Create code to Set a signed constant in the register `dest'.
284 // Really the same as CreateUIntSetInstruction.
285 //----------------------------------------------------------------------------
288 CreateIntSetInstruction(const TargetMachine& target,
289 int64_t C, Instruction* dest,
290 std::vector<MachineInstr*>& mvec,
291 MachineCodeForInstruction& mcfi)
293 CreateUIntSetInstruction(target, (uint64_t) C, dest, mvec, mcfi);
297 //---------------------------------------------------------------------------
298 // Create a table of LLVM opcode -> max. immediate constant likely to
299 // be usable for that operation.
300 //---------------------------------------------------------------------------
302 // Entry == 0 ==> no immediate constant field exists at all.
303 // Entry > 0 ==> abs(immediate constant) <= Entry
305 std::vector<int> MaxConstantsTable(Instruction::OtherOpsEnd);
308 MaxConstantForInstr(unsigned llvmOpCode)
310 int modelOpCode = -1;
312 if (llvmOpCode >= Instruction::BinaryOpsBegin &&
313 llvmOpCode < Instruction::BinaryOpsEnd)
314 modelOpCode = V9::ADD;
317 case Instruction::Ret: modelOpCode = V9::JMPLCALL; break;
319 case Instruction::Malloc:
320 case Instruction::Alloca:
321 case Instruction::GetElementPtr:
322 case Instruction::PHINode:
323 case Instruction::Cast:
324 case Instruction::Call: modelOpCode = V9::ADD; break;
326 case Instruction::Shl:
327 case Instruction::Shr: modelOpCode = V9::SLLX; break;
332 return (modelOpCode < 0)? 0: SparcMachineInstrDesc[modelOpCode].maxImmedConst;
336 InitializeMaxConstantsTable()
339 assert(MaxConstantsTable.size() == Instruction::OtherOpsEnd &&
340 "assignments below will be illegal!");
341 for (op = Instruction::TermOpsBegin; op < Instruction::TermOpsEnd; ++op)
342 MaxConstantsTable[op] = MaxConstantForInstr(op);
343 for (op = Instruction::BinaryOpsBegin; op < Instruction::BinaryOpsEnd; ++op)
344 MaxConstantsTable[op] = MaxConstantForInstr(op);
345 for (op = Instruction::MemoryOpsBegin; op < Instruction::MemoryOpsEnd; ++op)
346 MaxConstantsTable[op] = MaxConstantForInstr(op);
347 for (op = Instruction::OtherOpsBegin; op < Instruction::OtherOpsEnd; ++op)
348 MaxConstantsTable[op] = MaxConstantForInstr(op);
352 //---------------------------------------------------------------------------
353 // class UltraSparcInstrInfo
356 // Information about individual instructions.
357 // Most information is stored in the SparcMachineInstrDesc array above.
358 // Other information is computed on demand, and most such functions
359 // default to member functions in base class TargetInstrInfo.
360 //---------------------------------------------------------------------------
363 UltraSparcInstrInfo::UltraSparcInstrInfo()
364 : TargetInstrInfo(SparcMachineInstrDesc,
365 /*descSize = */ V9::NUM_TOTAL_OPCODES,
366 /*numRealOpCodes = */ V9::NUM_REAL_OPCODES)
368 InitializeMaxConstantsTable();
372 UltraSparcInstrInfo::ConstantMayNotFitInImmedField(const Constant* CV,
373 const Instruction* I) const
375 if (I->getOpcode() >= MaxConstantsTable.size()) // user-defined op (or bug!)
378 if (isa<ConstantPointerNull>(CV)) // can always use %g0
381 if (const ConstantUInt* U = dyn_cast<ConstantUInt>(CV))
382 /* Large unsigned longs may really just be small negative signed longs */
383 return (labs((int64_t) U->getValue()) > MaxConstantsTable[I->getOpcode()]);
385 if (const ConstantSInt* S = dyn_cast<ConstantSInt>(CV))
386 return (labs(S->getValue()) > MaxConstantsTable[I->getOpcode()]);
388 if (isa<ConstantBool>(CV))
389 return (1 > MaxConstantsTable[I->getOpcode()]);
395 // Create an instruction sequence to put the constant `val' into
396 // the virtual register `dest'. `val' may be a Constant or a
397 // GlobalValue, viz., the constant address of a global variable or function.
398 // The generated instructions are returned in `mvec'.
399 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
400 // Any stack space required is allocated via MachineFunction.
403 UltraSparcInstrInfo::CreateCodeToLoadConst(const TargetMachine& target,
407 std::vector<MachineInstr*>& mvec,
408 MachineCodeForInstruction& mcfi) const
410 assert(isa<Constant>(val) || isa<GlobalValue>(val) &&
411 "I only know about constant values and global addresses");
413 // Use a "set" instruction for known constants or symbolic constants (labels)
414 // that can go in an integer reg.
415 // We have to use a "load" instruction for all other constants,
416 // in particular, floating point constants.
418 const Type* valType = val->getType();
420 // Unfortunate special case: a ConstantPointerRef is just a
421 // reference to GlobalValue.
422 if (isa<ConstantPointerRef>(val))
423 val = cast<ConstantPointerRef>(val)->getValue();
425 if (isa<GlobalValue>(val)) {
426 TmpInstruction* tmpReg =
427 new TmpInstruction(PointerType::get(val->getType()), val);
428 mcfi.addTemp(tmpReg);
429 CreateSETXLabel(target, val, tmpReg, dest, mvec);
430 } else if (valType->isIntegral()) {
431 bool isValidConstant;
432 unsigned opSize = target.getTargetData().getTypeSize(val->getType());
433 unsigned destSize = target.getTargetData().getTypeSize(dest->getType());
435 if (! dest->getType()->isSigned()) {
436 uint64_t C = GetConstantValueAsUnsignedInt(val, isValidConstant);
437 assert(isValidConstant && "Unrecognized constant");
439 if (opSize > destSize || (val->getType()->isSigned() && destSize < 8)) {
440 // operand is larger than dest,
441 // OR both are equal but smaller than the full register size
442 // AND operand is signed, so it may have extra sign bits:
444 C = C & ((1U << 8*destSize) - 1);
446 CreateUIntSetInstruction(target, C, dest, mvec, mcfi);
448 int64_t C = GetConstantValueAsSignedInt(val, isValidConstant);
449 assert(isValidConstant && "Unrecognized constant");
451 if (opSize > destSize)
452 // operand is larger than dest: mask high bits
453 C = C & ((1U << 8*destSize) - 1);
455 if (opSize > destSize ||
456 (opSize == destSize && !val->getType()->isSigned()))
457 // sign-extend from destSize to 64 bits
458 C = ((C & (1U << (8*destSize - 1)))
459 ? C | ~((1U << 8*destSize) - 1)
462 CreateIntSetInstruction(target, C, dest, mvec, mcfi);
465 // Make an instruction sequence to load the constant, viz:
466 // SETX <addr-of-constant>, tmpReg, addrReg
467 // LOAD /*addr*/ addrReg, /*offset*/ 0, dest
469 // First, create a tmp register to be used by the SETX sequence.
470 TmpInstruction* tmpReg =
471 new TmpInstruction(PointerType::get(val->getType()), val);
472 mcfi.addTemp(tmpReg);
474 // Create another TmpInstruction for the address register
475 TmpInstruction* addrReg =
476 new TmpInstruction(PointerType::get(val->getType()), val);
477 mcfi.addTemp(addrReg);
479 // Put the address (a symbolic name) into a register
480 CreateSETXLabel(target, val, tmpReg, addrReg, mvec);
482 // Generate the load instruction
483 int64_t zeroOffset = 0; // to avoid ambiguity with (Value*) 0
484 unsigned Opcode = ChooseLoadInstruction(val->getType());
485 mvec.push_back(BuildMI(Opcode, 3).addReg(addrReg).
486 addSImm(zeroOffset).addRegDef(dest));
488 // Make sure constant is emitted to constant pool in assembly code.
489 MachineFunction::get(F).getInfo()->addToConstantPool(cast<Constant>(val));
494 // Create an instruction sequence to copy an integer register `val'
495 // to a floating point register `dest' by copying to memory and back.
496 // val must be an integral type. dest must be a Float or Double.
497 // The generated instructions are returned in `mvec'.
498 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
499 // Any stack space required is allocated via MachineFunction.
502 UltraSparcInstrInfo::CreateCodeToCopyIntToFloat(const TargetMachine& target,
506 std::vector<MachineInstr*>& mvec,
507 MachineCodeForInstruction& mcfi) const
509 assert((val->getType()->isIntegral() || isa<PointerType>(val->getType()))
510 && "Source type must be integral (integer or bool) or pointer");
511 assert(dest->getType()->isFloatingPoint()
512 && "Dest type must be float/double");
514 // Get a stack slot to use for the copy
515 int offset = MachineFunction::get(F).getInfo()->allocateLocalVar(val);
517 // Get the size of the source value being copied.
518 size_t srcSize = target.getTargetData().getTypeSize(val->getType());
520 // Store instruction stores `val' to [%fp+offset].
521 // The store and load opCodes are based on the size of the source value.
522 // If the value is smaller than 32 bits, we must sign- or zero-extend it
523 // to 32 bits since the load-float will load 32 bits.
524 // Note that the store instruction is the same for signed and unsigned ints.
525 const Type* storeType = (srcSize <= 4)? Type::IntTy : Type::LongTy;
526 Value* storeVal = val;
527 if (srcSize < target.getTargetData().getTypeSize(Type::FloatTy)) {
528 // sign- or zero-extend respectively
529 storeVal = new TmpInstruction(storeType, val);
530 if (val->getType()->isSigned())
531 CreateSignExtensionInstructions(target, F, val, storeVal, 8*srcSize,
534 CreateZeroExtensionInstructions(target, F, val, storeVal, 8*srcSize,
538 unsigned FPReg = target.getRegInfo().getFramePointer();
539 mvec.push_back(BuildMI(ChooseStoreInstruction(storeType), 3)
540 .addReg(storeVal).addMReg(FPReg).addSImm(offset));
542 // Load instruction loads [%fp+offset] to `dest'.
543 // The type of the load opCode is the floating point type that matches the
544 // stored type in size:
545 // On SparcV9: float for int or smaller, double for long.
547 const Type* loadType = (srcSize <= 4)? Type::FloatTy : Type::DoubleTy;
548 mvec.push_back(BuildMI(ChooseLoadInstruction(loadType), 3)
549 .addMReg(FPReg).addSImm(offset).addRegDef(dest));
552 // Similarly, create an instruction sequence to copy an FP register
553 // `val' to an integer register `dest' by copying to memory and back.
554 // The generated instructions are returned in `mvec'.
555 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
556 // Any stack space required is allocated via MachineFunction.
559 UltraSparcInstrInfo::CreateCodeToCopyFloatToInt(const TargetMachine& target,
563 std::vector<MachineInstr*>& mvec,
564 MachineCodeForInstruction& mcfi) const
566 const Type* opTy = val->getType();
567 const Type* destTy = dest->getType();
569 assert(opTy->isFloatingPoint() && "Source type must be float/double");
570 assert((destTy->isIntegral() || isa<PointerType>(destTy))
571 && "Dest type must be integer, bool or pointer");
573 int offset = MachineFunction::get(F).getInfo()->allocateLocalVar(val);
575 unsigned FPReg = target.getRegInfo().getFramePointer();
577 // Store instruction stores `val' to [%fp+offset].
578 // The store opCode is based only the source value being copied.
580 mvec.push_back(BuildMI(ChooseStoreInstruction(opTy), 3)
581 .addReg(val).addMReg(FPReg).addSImm(offset));
583 // Load instruction loads [%fp+offset] to `dest'.
584 // The type of the load opCode is the integer type that matches the
585 // source type in size:
586 // On SparcV9: int for float, long for double.
587 // Note that we *must* use signed loads even for unsigned dest types, to
588 // ensure correct sign-extension for UByte, UShort or UInt:
590 const Type* loadTy = (opTy == Type::FloatTy)? Type::IntTy : Type::LongTy;
591 mvec.push_back(BuildMI(ChooseLoadInstruction(loadTy), 3).addMReg(FPReg)
592 .addSImm(offset).addRegDef(dest));
596 // Create instruction(s) to copy src to dest, for arbitrary types
597 // The generated instructions are returned in `mvec'.
598 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
599 // Any stack space required is allocated via MachineFunction.
602 UltraSparcInstrInfo::CreateCopyInstructionsByType(const TargetMachine& target,
606 std::vector<MachineInstr*>& mvec,
607 MachineCodeForInstruction& mcfi) const
609 bool loadConstantToReg = false;
611 const Type* resultType = dest->getType();
613 MachineOpCode opCode = ChooseAddInstructionByType(resultType);
614 if (opCode == V9::INVALID_OPCODE) {
615 assert(0 && "Unsupported result type in CreateCopyInstructionsByType()");
619 // if `src' is a constant that doesn't fit in the immed field or if it is
620 // a global variable (i.e., a constant address), generate a load
621 // instruction instead of an add
623 if (isa<Constant>(src)) {
624 unsigned int machineRegNum;
626 MachineOperand::MachineOperandType opType =
627 ChooseRegOrImmed(src, opCode, target, /*canUseImmed*/ true,
628 machineRegNum, immedValue);
630 if (opType == MachineOperand::MO_VirtualRegister)
631 loadConstantToReg = true;
633 else if (isa<GlobalValue>(src))
634 loadConstantToReg = true;
636 if (loadConstantToReg) {
637 // `src' is constant and cannot fit in immed field for the ADD
638 // Insert instructions to "load" the constant into a register
639 target.getInstrInfo().CreateCodeToLoadConst(target, F, src, dest,
642 // Create an add-with-0 instruction of the appropriate type.
643 // Make `src' the second operand, in case it is a constant
644 // Use (unsigned long) 0 for a NULL pointer value.
646 const Type* Ty =isa<PointerType>(resultType) ? Type::ULongTy : resultType;
648 BuildMI(opCode, 3).addReg(Constant::getNullValue(Ty))
649 .addReg(src).addRegDef(dest);
655 // Helper function for sign-extension and zero-extension.
656 // For SPARC v9, we sign-extend the given operand using SLL; SRA/SRL.
658 CreateBitExtensionInstructions(bool signExtend,
659 const TargetMachine& target,
663 unsigned int numLowBits,
664 std::vector<MachineInstr*>& mvec,
665 MachineCodeForInstruction& mcfi)
669 assert(numLowBits <= 32 && "Otherwise, nothing should be done here!");
671 if (numLowBits < 32) {
672 // SLL is needed since operand size is < 32 bits.
673 TmpInstruction *tmpI = new TmpInstruction(destVal->getType(),
674 srcVal, destVal, "make32");
676 mvec.push_back(BuildMI(V9::SLLX, 3).addReg(srcVal)
677 .addZImm(32-numLowBits).addRegDef(tmpI));
681 mvec.push_back(BuildMI(signExtend? V9::SRA : V9::SRL, 3)
682 .addReg(srcVal).addZImm(32-numLowBits).addRegDef(destVal));
686 // Create instruction sequence to produce a sign-extended register value
687 // from an arbitrary-sized integer value (sized in bits, not bytes).
688 // The generated instructions are returned in `mvec'.
689 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
690 // Any stack space required is allocated via MachineFunction.
693 UltraSparcInstrInfo::CreateSignExtensionInstructions(
694 const TargetMachine& target,
698 unsigned int numLowBits,
699 std::vector<MachineInstr*>& mvec,
700 MachineCodeForInstruction& mcfi) const
702 CreateBitExtensionInstructions(/*signExtend*/ true, target, F, srcVal,
703 destVal, numLowBits, mvec, mcfi);
707 // Create instruction sequence to produce a zero-extended register value
708 // from an arbitrary-sized integer value (sized in bits, not bytes).
709 // For SPARC v9, we sign-extend the given operand using SLL; SRL.
710 // The generated instructions are returned in `mvec'.
711 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
712 // Any stack space required is allocated via MachineFunction.
715 UltraSparcInstrInfo::CreateZeroExtensionInstructions(
716 const TargetMachine& target,
720 unsigned int numLowBits,
721 std::vector<MachineInstr*>& mvec,
722 MachineCodeForInstruction& mcfi) const
724 CreateBitExtensionInstructions(/*signExtend*/ false, target, F, srcVal,
725 destVal, numLowBits, mvec, mcfi);