1 //===-- SparcV9InstrInfo.cpp - SparcV9 Instr. Selection Support Methods ---===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains various methods of the class SparcV9InstrInfo, many of
11 // which appear to build canned sequences of MachineInstrs, and are
12 // used in instruction selection.
14 //===----------------------------------------------------------------------===//
16 #include "llvm/Constants.h"
17 #include "llvm/DerivedTypes.h"
18 #include "llvm/Function.h"
19 #include "llvm/iTerminators.h"
20 #include "llvm/CodeGen/InstrSelection.h"
21 #include "llvm/CodeGen/MachineConstantPool.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/MachineFunctionInfo.h"
24 #include "llvm/CodeGen/MachineCodeForInstruction.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "SparcV9Internals.h"
27 #include "SparcV9InstrSelectionSupport.h"
28 #include "SparcV9InstrInfo.h"
32 static const uint32_t MAXLO = (1 << 10) - 1; // set bits set by %lo(*)
33 static const uint32_t MAXSIMM = (1 << 12) - 1; // set bits in simm13 field of OR
35 //---------------------------------------------------------------------------
36 // Function ConvertConstantToIntType
38 // Function to get the value of an integral constant in the form
39 // that must be put into the machine register. The specified constant is
40 // interpreted as (i.e., converted if necessary to) the specified destination
41 // type. The result is always returned as an uint64_t, since the representation
42 // of int64_t and uint64_t are identical. The argument can be any known const.
44 // isValidConstant is set to true if a valid constant was found.
45 //---------------------------------------------------------------------------
48 SparcV9InstrInfo::ConvertConstantToIntType(const TargetMachine &target,
51 bool &isValidConstant) const
53 isValidConstant = false;
56 if (! destType->isIntegral() && ! isa<PointerType>(destType))
59 if (! isa<Constant>(V))
62 // ConstantPointerRef: no conversions needed: get value and return it
63 if (const ConstantPointerRef* CPR = dyn_cast<ConstantPointerRef>(V)) {
64 // A ConstantPointerRef is just a reference to GlobalValue.
65 isValidConstant = true; // may be overwritten by recursive call
66 return (CPR->isNullValue()? 0
67 : ConvertConstantToIntType(target, CPR->getValue(), destType,
71 // ConstantBool: no conversions needed: get value and return it
72 if (const ConstantBool *CB = dyn_cast<ConstantBool>(V)) {
73 isValidConstant = true;
74 return (uint64_t) CB->getValue();
77 // For other types of constants, some conversion may be needed.
78 // First, extract the constant operand according to its own type
79 if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(V))
80 switch(CE->getOpcode()) {
81 case Instruction::Cast: // recursively get the value as cast
82 C = ConvertConstantToIntType(target, CE->getOperand(0), CE->getType(),
85 default: // not simplifying other ConstantExprs
88 else if (const ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
89 isValidConstant = true;
90 C = CI->getRawValue();
92 else if (const ConstantFP *CFP = dyn_cast<ConstantFP>(V)) {
93 isValidConstant = true;
94 double fC = CFP->getValue();
95 C = (destType->isSigned()? (uint64_t) (int64_t) fC
99 // Now if a valid value was found, convert it to destType.
100 if (isValidConstant) {
101 unsigned opSize = target.getTargetData().getTypeSize(V->getType());
102 unsigned destSize = target.getTargetData().getTypeSize(destType);
103 uint64_t maskHi = (destSize < 8)? (1U << 8*destSize) - 1 : ~0;
104 assert(opSize <= 8 && destSize <= 8 && ">8-byte int type unexpected");
106 if (destType->isSigned()) {
107 if (opSize > destSize) // operand is larger than dest:
108 C = C & maskHi; // mask high bits
110 if (opSize > destSize ||
111 (opSize == destSize && ! V->getType()->isSigned()))
112 if (C & (1U << (8*destSize - 1)))
113 C = C | ~maskHi; // sign-extend from destSize to 64 bits
116 if (opSize > destSize || (V->getType()->isSigned() && destSize < 8)) {
117 // operand is larger than dest,
118 // OR both are equal but smaller than the full register size
119 // AND operand is signed, so it may have extra sign bits:
130 //----------------------------------------------------------------------------
131 // Function: CreateSETUWConst
133 // Set a 32-bit unsigned constant in the register `dest', using
134 // SETHI, OR in the worst case. This function correctly emulates
135 // the SETUW pseudo-op for SPARC v9 (if argument isSigned == false).
137 // The isSigned=true case is used to implement SETSW without duplicating code.
139 // Optimize some common cases:
140 // (1) Small value that fits in simm13 field of OR: don't need SETHI.
141 // (2) isSigned = true and C is a small negative signed value, i.e.,
142 // high bits are 1, and the remaining bits fit in simm13(OR).
143 //----------------------------------------------------------------------------
146 CreateSETUWConst(const TargetMachine& target, uint32_t C,
147 Instruction* dest, std::vector<MachineInstr*>& mvec,
148 bool isSigned = false)
150 MachineInstr *miSETHI = NULL, *miOR = NULL;
152 // In order to get efficient code, we should not generate the SETHI if
153 // all high bits are 1 (i.e., this is a small signed value that fits in
154 // the simm13 field of OR). So we check for and handle that case specially.
155 // NOTE: The value C = 0x80000000 is bad: sC < 0 *and* -sC < 0.
156 // In fact, sC == -sC, so we have to check for this explicitly.
157 int32_t sC = (int32_t) C;
158 bool smallNegValue =isSigned && sC < 0 && sC != -sC && -sC < (int32_t)MAXSIMM;
160 // Set the high 22 bits in dest if non-zero and simm13 field of OR not enough
161 if (!smallNegValue && (C & ~MAXLO) && C > MAXSIMM) {
162 miSETHI = BuildMI(V9::SETHI, 2).addZImm(C).addRegDef(dest);
163 miSETHI->setOperandHi32(0);
164 mvec.push_back(miSETHI);
167 // Set the low 10 or 12 bits in dest. This is necessary if no SETHI
168 // was generated, or if the low 10 bits are non-zero.
169 if (miSETHI==NULL || C & MAXLO) {
171 // unsigned value with high-order bits set using SETHI
172 miOR = BuildMI(V9::ORi,3).addReg(dest).addZImm(C).addRegDef(dest);
173 miOR->setOperandLo32(1);
175 // unsigned or small signed value that fits in simm13 field of OR
176 assert(smallNegValue || (C & ~MAXSIMM) == 0);
177 miOR = BuildMI(V9::ORi, 3).addMReg(target.getRegInfo()
179 .addSImm(sC).addRegDef(dest);
181 mvec.push_back(miOR);
184 assert((miSETHI || miOR) && "Oops, no code was generated!");
188 //----------------------------------------------------------------------------
189 // Function: CreateSETSWConst
191 // Set a 32-bit signed constant in the register `dest', with sign-extension
192 // to 64 bits. This uses SETHI, OR, SRA in the worst case.
193 // This function correctly emulates the SETSW pseudo-op for SPARC v9.
195 // Optimize the same cases as SETUWConst, plus:
196 // (1) SRA is not needed for positive or small negative values.
197 //----------------------------------------------------------------------------
200 CreateSETSWConst(const TargetMachine& target, int32_t C,
201 Instruction* dest, std::vector<MachineInstr*>& mvec)
203 // Set the low 32 bits of dest
204 CreateSETUWConst(target, (uint32_t) C, dest, mvec, /*isSigned*/true);
206 // Sign-extend to the high 32 bits if needed.
207 // NOTE: The value C = 0x80000000 is bad: -C == C and so -C is < MAXSIMM
208 if (C < 0 && (C == -C || -C > (int32_t) MAXSIMM))
209 mvec.push_back(BuildMI(V9::SRAi5,3).addReg(dest).addZImm(0).addRegDef(dest));
213 //----------------------------------------------------------------------------
214 // Function: CreateSETXConst
216 // Set a 64-bit signed or unsigned constant in the register `dest'.
217 // Use SETUWConst for each 32 bit word, plus a left-shift-by-32 in between.
218 // This function correctly emulates the SETX pseudo-op for SPARC v9.
220 // Optimize the same cases as SETUWConst for each 32 bit word.
221 //----------------------------------------------------------------------------
224 CreateSETXConst(const TargetMachine& target, uint64_t C,
225 Instruction* tmpReg, Instruction* dest,
226 std::vector<MachineInstr*>& mvec)
228 assert(C > (unsigned int) ~0 && "Use SETUW/SETSW for 32-bit values!");
232 // Code to set the upper 32 bits of the value in register `tmpReg'
233 CreateSETUWConst(target, (C >> 32), tmpReg, mvec);
235 // Shift tmpReg left by 32 bits
236 mvec.push_back(BuildMI(V9::SLLXi6, 3).addReg(tmpReg).addZImm(32)
239 // Code to set the low 32 bits of the value in register `dest'
240 CreateSETUWConst(target, C, dest, mvec);
242 // dest = OR(tmpReg, dest)
243 mvec.push_back(BuildMI(V9::ORr,3).addReg(dest).addReg(tmpReg).addRegDef(dest));
247 //----------------------------------------------------------------------------
248 // Function: CreateSETUWLabel
250 // Set a 32-bit constant (given by a symbolic label) in the register `dest'.
251 //----------------------------------------------------------------------------
254 CreateSETUWLabel(const TargetMachine& target, Value* val,
255 Instruction* dest, std::vector<MachineInstr*>& mvec)
259 // Set the high 22 bits in dest
260 MI = BuildMI(V9::SETHI, 2).addReg(val).addRegDef(dest);
261 MI->setOperandHi32(0);
264 // Set the low 10 bits in dest
265 MI = BuildMI(V9::ORr, 3).addReg(dest).addReg(val).addRegDef(dest);
266 MI->setOperandLo32(1);
271 //----------------------------------------------------------------------------
272 // Function: CreateSETXLabel
274 // Set a 64-bit constant (given by a symbolic label) in the register `dest'.
275 //----------------------------------------------------------------------------
278 CreateSETXLabel(const TargetMachine& target,
279 Value* val, Instruction* tmpReg, Instruction* dest,
280 std::vector<MachineInstr*>& mvec)
282 assert(isa<Constant>(val) || isa<GlobalValue>(val) &&
283 "I only know about constant values and global addresses");
287 MI = BuildMI(V9::SETHI, 2).addPCDisp(val).addRegDef(tmpReg);
288 MI->setOperandHi64(0);
291 MI = BuildMI(V9::ORi, 3).addReg(tmpReg).addPCDisp(val).addRegDef(tmpReg);
292 MI->setOperandLo64(1);
295 mvec.push_back(BuildMI(V9::SLLXi6, 3).addReg(tmpReg).addZImm(32)
297 MI = BuildMI(V9::SETHI, 2).addPCDisp(val).addRegDef(dest);
298 MI->setOperandHi32(0);
301 MI = BuildMI(V9::ORr, 3).addReg(dest).addReg(tmpReg).addRegDef(dest);
304 MI = BuildMI(V9::ORi, 3).addReg(dest).addPCDisp(val).addRegDef(dest);
305 MI->setOperandLo32(1);
310 //----------------------------------------------------------------------------
311 // Function: CreateUIntSetInstruction
313 // Create code to Set an unsigned constant in the register `dest'.
314 // Uses CreateSETUWConst, CreateSETSWConst or CreateSETXConst as needed.
315 // CreateSETSWConst is an optimization for the case that the unsigned value
316 // has all ones in the 33 high bits (so that sign-extension sets them all).
317 //----------------------------------------------------------------------------
320 CreateUIntSetInstruction(const TargetMachine& target,
321 uint64_t C, Instruction* dest,
322 std::vector<MachineInstr*>& mvec,
323 MachineCodeForInstruction& mcfi)
325 static const uint64_t lo32 = (uint32_t) ~0;
326 if (C <= lo32) // High 32 bits are 0. Set low 32 bits.
327 CreateSETUWConst(target, (uint32_t) C, dest, mvec);
328 else if ((C & ~lo32) == ~lo32 && (C & (1U << 31))) {
329 // All high 33 (not 32) bits are 1s: sign-extension will take care
330 // of high 32 bits, so use the sequence for signed int
331 CreateSETSWConst(target, (int32_t) C, dest, mvec);
332 } else if (C > lo32) {
333 // C does not fit in 32 bits
334 TmpInstruction* tmpReg = new TmpInstruction(mcfi, Type::IntTy);
335 CreateSETXConst(target, C, tmpReg, dest, mvec);
340 //----------------------------------------------------------------------------
341 // Function: CreateIntSetInstruction
343 // Create code to Set a signed constant in the register `dest'.
344 // Really the same as CreateUIntSetInstruction.
345 //----------------------------------------------------------------------------
348 CreateIntSetInstruction(const TargetMachine& target,
349 int64_t C, Instruction* dest,
350 std::vector<MachineInstr*>& mvec,
351 MachineCodeForInstruction& mcfi)
353 CreateUIntSetInstruction(target, (uint64_t) C, dest, mvec, mcfi);
357 //---------------------------------------------------------------------------
358 // Create a table of LLVM opcode -> max. immediate constant likely to
359 // be usable for that operation.
360 //---------------------------------------------------------------------------
362 // Entry == 0 ==> no immediate constant field exists at all.
363 // Entry > 0 ==> abs(immediate constant) <= Entry
365 std::vector<int> MaxConstantsTable(Instruction::OtherOpsEnd);
368 MaxConstantForInstr(unsigned llvmOpCode)
370 int modelOpCode = -1;
372 if (llvmOpCode >= Instruction::BinaryOpsBegin &&
373 llvmOpCode < Instruction::BinaryOpsEnd)
374 modelOpCode = V9::ADDi;
377 case Instruction::Ret: modelOpCode = V9::JMPLCALLi; break;
379 case Instruction::Malloc:
380 case Instruction::Alloca:
381 case Instruction::GetElementPtr:
382 case Instruction::PHI:
383 case Instruction::Cast:
384 case Instruction::Call: modelOpCode = V9::ADDi; break;
386 case Instruction::Shl:
387 case Instruction::Shr: modelOpCode = V9::SLLXi6; break;
392 return (modelOpCode < 0)? 0: SparcV9MachineInstrDesc[modelOpCode].maxImmedConst;
396 InitializeMaxConstantsTable()
399 assert(MaxConstantsTable.size() == Instruction::OtherOpsEnd &&
400 "assignments below will be illegal!");
401 for (op = Instruction::TermOpsBegin; op < Instruction::TermOpsEnd; ++op)
402 MaxConstantsTable[op] = MaxConstantForInstr(op);
403 for (op = Instruction::BinaryOpsBegin; op < Instruction::BinaryOpsEnd; ++op)
404 MaxConstantsTable[op] = MaxConstantForInstr(op);
405 for (op = Instruction::MemoryOpsBegin; op < Instruction::MemoryOpsEnd; ++op)
406 MaxConstantsTable[op] = MaxConstantForInstr(op);
407 for (op = Instruction::OtherOpsBegin; op < Instruction::OtherOpsEnd; ++op)
408 MaxConstantsTable[op] = MaxConstantForInstr(op);
412 //---------------------------------------------------------------------------
413 // class SparcV9InstrInfo
416 // Information about individual instructions.
417 // Most information is stored in the SparcV9MachineInstrDesc array above.
418 // Other information is computed on demand, and most such functions
419 // default to member functions in base class TargetInstrInfo.
420 //---------------------------------------------------------------------------
422 SparcV9InstrInfo::SparcV9InstrInfo()
423 : TargetInstrInfo(SparcV9MachineInstrDesc, V9::NUM_TOTAL_OPCODES) {
424 InitializeMaxConstantsTable();
428 SparcV9InstrInfo::ConstantMayNotFitInImmedField(const Constant* CV,
429 const Instruction* I) const
431 if (I->getOpcode() >= MaxConstantsTable.size()) // user-defined op (or bug!)
434 if (isa<ConstantPointerNull>(CV)) // can always use %g0
437 if (isa<SwitchInst>(I)) // Switch instructions will be lowered!
440 if (const ConstantInt* CI = dyn_cast<ConstantInt>(CV))
441 return labs((int64_t)CI->getRawValue()) > MaxConstantsTable[I->getOpcode()];
443 if (isa<ConstantBool>(CV))
444 return 1 > MaxConstantsTable[I->getOpcode()];
450 // Create an instruction sequence to put the constant `val' into
451 // the virtual register `dest'. `val' may be a Constant or a
452 // GlobalValue, viz., the constant address of a global variable or function.
453 // The generated instructions are returned in `mvec'.
454 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
455 // Any stack space required is allocated via MachineFunction.
458 SparcV9InstrInfo::CreateCodeToLoadConst(const TargetMachine& target,
462 std::vector<MachineInstr*>& mvec,
463 MachineCodeForInstruction& mcfi) const
465 assert(isa<Constant>(val) || isa<GlobalValue>(val) &&
466 "I only know about constant values and global addresses");
468 // Use a "set" instruction for known constants or symbolic constants (labels)
469 // that can go in an integer reg.
470 // We have to use a "load" instruction for all other constants,
471 // in particular, floating point constants.
473 const Type* valType = val->getType();
475 // A ConstantPointerRef is just a reference to GlobalValue.
476 while (isa<ConstantPointerRef>(val))
477 val = cast<ConstantPointerRef>(val)->getValue();
479 if (isa<GlobalValue>(val)) {
480 TmpInstruction* tmpReg =
481 new TmpInstruction(mcfi, PointerType::get(val->getType()), val);
482 CreateSETXLabel(target, val, tmpReg, dest, mvec);
487 uint64_t C = ConvertConstantToIntType(target, val, dest->getType(), isValid);
489 if (dest->getType()->isSigned())
490 CreateUIntSetInstruction(target, C, dest, mvec, mcfi);
492 CreateIntSetInstruction(target, (int64_t) C, dest, mvec, mcfi);
495 // Make an instruction sequence to load the constant, viz:
496 // SETX <addr-of-constant>, tmpReg, addrReg
497 // LOAD /*addr*/ addrReg, /*offset*/ 0, dest
499 // First, create a tmp register to be used by the SETX sequence.
500 TmpInstruction* tmpReg =
501 new TmpInstruction(mcfi, PointerType::get(val->getType()));
503 // Create another TmpInstruction for the address register
504 TmpInstruction* addrReg =
505 new TmpInstruction(mcfi, PointerType::get(val->getType()));
507 // Get the constant pool index for this constant
508 MachineConstantPool *CP = MachineFunction::get(F).getConstantPool();
509 Constant *C = cast<Constant>(val);
510 unsigned CPI = CP->getConstantPoolIndex(C);
512 // Put the address of the constant into a register
515 MI = BuildMI(V9::SETHI, 2).addConstantPoolIndex(CPI).addRegDef(tmpReg);
516 MI->setOperandHi64(0);
519 MI = BuildMI(V9::ORi, 3).addReg(tmpReg).addConstantPoolIndex(CPI)
521 MI->setOperandLo64(1);
524 mvec.push_back(BuildMI(V9::SLLXi6, 3).addReg(tmpReg).addZImm(32)
526 MI = BuildMI(V9::SETHI, 2).addConstantPoolIndex(CPI).addRegDef(addrReg);
527 MI->setOperandHi32(0);
530 MI = BuildMI(V9::ORr, 3).addReg(addrReg).addReg(tmpReg).addRegDef(addrReg);
533 MI = BuildMI(V9::ORi, 3).addReg(addrReg).addConstantPoolIndex(CPI)
535 MI->setOperandLo32(1);
538 // Now load the constant from out ConstantPool label
539 unsigned Opcode = ChooseLoadInstruction(val->getType());
540 Opcode = convertOpcodeFromRegToImm(Opcode);
541 mvec.push_back(BuildMI(Opcode, 3)
542 .addReg(addrReg).addSImm((int64_t)0).addRegDef(dest));
547 // Create an instruction sequence to copy an integer register `val'
548 // to a floating point register `dest' by copying to memory and back.
549 // val must be an integral type. dest must be a Float or Double.
550 // The generated instructions are returned in `mvec'.
551 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
552 // Any stack space required is allocated via MachineFunction.
555 SparcV9InstrInfo::CreateCodeToCopyIntToFloat(const TargetMachine& target,
559 std::vector<MachineInstr*>& mvec,
560 MachineCodeForInstruction& mcfi) const
562 assert((val->getType()->isIntegral() || isa<PointerType>(val->getType()))
563 && "Source type must be integral (integer or bool) or pointer");
564 assert(dest->getType()->isFloatingPoint()
565 && "Dest type must be float/double");
567 // Get a stack slot to use for the copy
568 int offset = MachineFunction::get(F).getInfo()->allocateLocalVar(val);
570 // Get the size of the source value being copied.
571 size_t srcSize = target.getTargetData().getTypeSize(val->getType());
573 // Store instruction stores `val' to [%fp+offset].
574 // The store and load opCodes are based on the size of the source value.
575 // If the value is smaller than 32 bits, we must sign- or zero-extend it
576 // to 32 bits since the load-float will load 32 bits.
577 // Note that the store instruction is the same for signed and unsigned ints.
578 const Type* storeType = (srcSize <= 4)? Type::IntTy : Type::LongTy;
579 Value* storeVal = val;
580 if (srcSize < target.getTargetData().getTypeSize(Type::FloatTy)) {
581 // sign- or zero-extend respectively
582 storeVal = new TmpInstruction(mcfi, storeType, val);
583 if (val->getType()->isSigned())
584 CreateSignExtensionInstructions(target, F, val, storeVal, 8*srcSize,
587 CreateZeroExtensionInstructions(target, F, val, storeVal, 8*srcSize,
591 unsigned FPReg = target.getRegInfo().getFramePointer();
592 unsigned StoreOpcode = ChooseStoreInstruction(storeType);
593 StoreOpcode = convertOpcodeFromRegToImm(StoreOpcode);
594 mvec.push_back(BuildMI(StoreOpcode, 3)
595 .addReg(storeVal).addMReg(FPReg).addSImm(offset));
597 // Load instruction loads [%fp+offset] to `dest'.
598 // The type of the load opCode is the floating point type that matches the
599 // stored type in size:
600 // On SparcV9: float for int or smaller, double for long.
602 const Type* loadType = (srcSize <= 4)? Type::FloatTy : Type::DoubleTy;
603 unsigned LoadOpcode = ChooseLoadInstruction(loadType);
604 LoadOpcode = convertOpcodeFromRegToImm(LoadOpcode);
605 mvec.push_back(BuildMI(LoadOpcode, 3)
606 .addMReg(FPReg).addSImm(offset).addRegDef(dest));
609 // Similarly, create an instruction sequence to copy an FP register
610 // `val' to an integer register `dest' by copying to memory and back.
611 // The generated instructions are returned in `mvec'.
612 // Any temp. virtual registers (TmpInstruction) created are recorded in mcfi.
613 // Temporary stack space required is allocated via MachineFunction.
616 SparcV9InstrInfo::CreateCodeToCopyFloatToInt(const TargetMachine& target,
620 std::vector<MachineInstr*>& mvec,
621 MachineCodeForInstruction& mcfi) const
623 const Type* opTy = val->getType();
624 const Type* destTy = dest->getType();
626 assert(opTy->isFloatingPoint() && "Source type must be float/double");
627 assert((destTy->isIntegral() || isa<PointerType>(destTy))
628 && "Dest type must be integer, bool or pointer");
630 // FIXME: For now, we allocate permanent space because the stack frame
631 // manager does not allow locals to be allocated (e.g., for alloca) after
632 // a temp is allocated!
634 int offset = MachineFunction::get(F).getInfo()->allocateLocalVar(val);
636 unsigned FPReg = target.getRegInfo().getFramePointer();
638 // Store instruction stores `val' to [%fp+offset].
639 // The store opCode is based only the source value being copied.
641 unsigned StoreOpcode = ChooseStoreInstruction(opTy);
642 StoreOpcode = convertOpcodeFromRegToImm(StoreOpcode);
643 mvec.push_back(BuildMI(StoreOpcode, 3)
644 .addReg(val).addMReg(FPReg).addSImm(offset));
646 // Load instruction loads [%fp+offset] to `dest'.
647 // The type of the load opCode is the integer type that matches the
648 // source type in size:
649 // On SparcV9: int for float, long for double.
650 // Note that we *must* use signed loads even for unsigned dest types, to
651 // ensure correct sign-extension for UByte, UShort or UInt:
653 const Type* loadTy = (opTy == Type::FloatTy)? Type::IntTy : Type::LongTy;
654 unsigned LoadOpcode = ChooseLoadInstruction(loadTy);
655 LoadOpcode = convertOpcodeFromRegToImm(LoadOpcode);
656 mvec.push_back(BuildMI(LoadOpcode, 3).addMReg(FPReg)
657 .addSImm(offset).addRegDef(dest));
661 // Create instruction(s) to copy src to dest, for arbitrary types
662 // The generated instructions are returned in `mvec'.
663 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
664 // Any stack space required is allocated via MachineFunction.
667 SparcV9InstrInfo::CreateCopyInstructionsByType(const TargetMachine& target,
671 std::vector<MachineInstr*>& mvec,
672 MachineCodeForInstruction& mcfi) const
674 bool loadConstantToReg = false;
676 const Type* resultType = dest->getType();
678 MachineOpCode opCode = ChooseAddInstructionByType(resultType);
679 if (opCode == V9::INVALID_OPCODE) {
680 assert(0 && "Unsupported result type in CreateCopyInstructionsByType()");
684 // if `src' is a constant that doesn't fit in the immed field or if it is
685 // a global variable (i.e., a constant address), generate a load
686 // instruction instead of an add
688 if (isa<Constant>(src)) {
689 unsigned int machineRegNum;
691 MachineOperand::MachineOperandType opType =
692 ChooseRegOrImmed(src, opCode, target, /*canUseImmed*/ true,
693 machineRegNum, immedValue);
695 if (opType == MachineOperand::MO_VirtualRegister)
696 loadConstantToReg = true;
698 else if (isa<GlobalValue>(src))
699 loadConstantToReg = true;
701 if (loadConstantToReg) {
702 // `src' is constant and cannot fit in immed field for the ADD
703 // Insert instructions to "load" the constant into a register
704 target.getInstrInfo().CreateCodeToLoadConst(target, F, src, dest,
707 // Create a reg-to-reg copy instruction for the given type:
708 // -- For FP values, create a FMOVS or FMOVD instruction
709 // -- For non-FP values, create an add-with-0 instruction (opCode as above)
710 // Make `src' the second operand, in case it is a small constant!
713 if (resultType->isFloatingPoint())
714 MI = (BuildMI(resultType == Type::FloatTy? V9::FMOVS : V9::FMOVD, 2)
715 .addReg(src).addRegDef(dest));
717 const Type* Ty =isa<PointerType>(resultType)? Type::ULongTy :resultType;
718 MI = (BuildMI(opCode, 3)
719 .addSImm((int64_t) 0).addReg(src).addRegDef(dest));
726 // Helper function for sign-extension and zero-extension.
727 // For SPARC v9, we sign-extend the given operand using SLL; SRA/SRL.
729 CreateBitExtensionInstructions(bool signExtend,
730 const TargetMachine& target,
734 unsigned int numLowBits,
735 std::vector<MachineInstr*>& mvec,
736 MachineCodeForInstruction& mcfi)
740 assert(numLowBits <= 32 && "Otherwise, nothing should be done here!");
742 if (numLowBits < 32) {
743 // SLL is needed since operand size is < 32 bits.
744 TmpInstruction *tmpI = new TmpInstruction(mcfi, destVal->getType(),
745 srcVal, destVal, "make32");
746 mvec.push_back(BuildMI(V9::SLLXi6, 3).addReg(srcVal)
747 .addZImm(32-numLowBits).addRegDef(tmpI));
751 mvec.push_back(BuildMI(signExtend? V9::SRAi5 : V9::SRLi5, 3)
752 .addReg(srcVal).addZImm(32-numLowBits).addRegDef(destVal));
756 // Create instruction sequence to produce a sign-extended register value
757 // from an arbitrary-sized integer value (sized in bits, not bytes).
758 // The generated instructions are returned in `mvec'.
759 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
760 // Any stack space required is allocated via MachineFunction.
763 SparcV9InstrInfo::CreateSignExtensionInstructions(
764 const TargetMachine& target,
768 unsigned int numLowBits,
769 std::vector<MachineInstr*>& mvec,
770 MachineCodeForInstruction& mcfi) const
772 CreateBitExtensionInstructions(/*signExtend*/ true, target, F, srcVal,
773 destVal, numLowBits, mvec, mcfi);
777 // Create instruction sequence to produce a zero-extended register value
778 // from an arbitrary-sized integer value (sized in bits, not bytes).
779 // For SPARC v9, we sign-extend the given operand using SLL; SRL.
780 // The generated instructions are returned in `mvec'.
781 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
782 // Any stack space required is allocated via MachineFunction.
785 SparcV9InstrInfo::CreateZeroExtensionInstructions(
786 const TargetMachine& target,
790 unsigned int numLowBits,
791 std::vector<MachineInstr*>& mvec,
792 MachineCodeForInstruction& mcfi) const
794 CreateBitExtensionInstructions(/*signExtend*/ false, target, F, srcVal,
795 destVal, numLowBits, mvec, mcfi);
798 } // End llvm namespace