1 //===-- SparcInstrInfo.cpp ------------------------------------------------===//
3 //===----------------------------------------------------------------------===//
5 #include "SparcInternals.h"
6 #include "SparcInstrSelectionSupport.h"
7 #include "llvm/CodeGen/InstrSelection.h"
8 #include "llvm/CodeGen/InstrSelectionSupport.h"
9 #include "llvm/CodeGen/MachineCodeForMethod.h"
10 #include "llvm/CodeGen/MachineCodeForInstruction.h"
11 #include "llvm/Function.h"
12 #include "llvm/Constants.h"
13 #include "llvm/DerivedTypes.h"
16 static const uint32_t MAXLO = (1 << 10) - 1; // set bits set by %lo(*)
17 static const uint32_t MAXSIMM = (1 << 12) - 1; // set bits in simm13 field of OR
20 //----------------------------------------------------------------------------
21 // Function: CreateSETUWConst
23 // Set a 32-bit unsigned constant in the register `dest', using
24 // SETHI, OR in the worst case. This function correctly emulates
25 // the SETUW pseudo-op for SPARC v9 (if argument isSigned == false).
27 // The isSigned=true case is used to implement SETSW without duplicating code.
29 // Optimize some common cases:
30 // (1) Small value that fits in simm13 field of OR: don't need SETHI.
31 // (2) isSigned = true and C is a small negative signed value, i.e.,
32 // high bits are 1, and the remaining bits fit in simm13(OR).
33 //----------------------------------------------------------------------------
36 CreateSETUWConst(const TargetMachine& target, uint32_t C,
37 Instruction* dest, vector<MachineInstr*>& mvec,
38 bool isSigned = false)
40 MachineInstr *miSETHI = NULL, *miOR = NULL;
42 // In order to get efficient code, we should not generate the SETHI if
43 // all high bits are 1 (i.e., this is a small signed value that fits in
44 // the simm13 field of OR). So we check for and handle that case specially.
45 // NOTE: The value C = 0x80000000 is bad: sC < 0 *and* -sC < 0.
46 // In fact, sC == -sC, so we have to check for this explicitly.
47 int32_t sC = (int32_t) C;
48 bool smallNegValue =isSigned && sC < 0 && sC != -sC && -sC < (int32_t)MAXSIMM;
50 // Set the high 22 bits in dest if non-zero and simm13 field of OR not enough
51 if (!smallNegValue && (C & ~MAXLO) && C > MAXSIMM)
53 miSETHI = Create2OperandInstr_UImmed(SETHI, C, dest);
54 miSETHI->setOperandHi32(0);
55 mvec.push_back(miSETHI);
58 // Set the low 10 or 12 bits in dest. This is necessary if no SETHI
59 // was generated, or if the low 10 bits are non-zero.
60 if (miSETHI==NULL || C & MAXLO)
63 { // unsigned value with high-order bits set using SETHI
64 miOR = Create3OperandInstr_UImmed(OR, dest, C, dest);
65 miOR->setOperandLo32(1);
68 { // unsigned or small signed value that fits in simm13 field of OR
69 assert(smallNegValue || (C & ~MAXSIMM) == 0);
70 miOR = new MachineInstr(OR);
71 miOR->SetMachineOperandReg(0, target.getRegInfo().getZeroRegNum());
72 miOR->SetMachineOperandConst(1, MachineOperand::MO_SignExtendedImmed,
74 miOR->SetMachineOperandVal(2,MachineOperand::MO_VirtualRegister,dest);
79 assert((miSETHI || miOR) && "Oops, no code was generated!");
83 //----------------------------------------------------------------------------
84 // Function: CreateSETSWConst
86 // Set a 32-bit signed constant in the register `dest', with sign-extension
87 // to 64 bits. This uses SETHI, OR, SRA in the worst case.
88 // This function correctly emulates the SETSW pseudo-op for SPARC v9.
90 // Optimize the same cases as SETUWConst, plus:
91 // (1) SRA is not needed for positive or small negative values.
92 //----------------------------------------------------------------------------
95 CreateSETSWConst(const TargetMachine& target, int32_t C,
96 Instruction* dest, vector<MachineInstr*>& mvec)
100 // Set the low 32 bits of dest
101 CreateSETUWConst(target, (uint32_t) C, dest, mvec, /*isSigned*/true);
103 // Sign-extend to the high 32 bits if needed
104 if (C < 0 && (-C) > (int32_t) MAXSIMM)
106 MI = Create3OperandInstr_UImmed(SRA, dest, 0, dest);
112 //----------------------------------------------------------------------------
113 // Function: CreateSETXConst
115 // Set a 64-bit signed or unsigned constant in the register `dest'.
116 // Use SETUWConst for each 32 bit word, plus a left-shift-by-32 in between.
117 // This function correctly emulates the SETX pseudo-op for SPARC v9.
119 // Optimize the same cases as SETUWConst for each 32 bit word.
120 //----------------------------------------------------------------------------
123 CreateSETXConst(const TargetMachine& target, uint64_t C,
124 Instruction* tmpReg, Instruction* dest,
125 vector<MachineInstr*>& mvec)
127 assert(C > (unsigned int) ~0 && "Use SETUW/SETSW for 32-bit values!");
131 // Code to set the upper 32 bits of the value in register `tmpReg'
132 CreateSETUWConst(target, (C >> 32), tmpReg, mvec);
134 // Shift tmpReg left by 32 bits
135 MI = Create3OperandInstr_UImmed(SLLX, tmpReg, 32, tmpReg);
138 // Code to set the low 32 bits of the value in register `dest'
139 CreateSETUWConst(target, C, dest, mvec);
141 // dest = OR(tmpReg, dest)
142 MI = Create3OperandInstr(OR, dest, tmpReg, dest);
147 //----------------------------------------------------------------------------
148 // Function: CreateSETUWLabel
150 // Set a 32-bit constant (given by a symbolic label) in the register `dest'.
151 //----------------------------------------------------------------------------
154 CreateSETUWLabel(const TargetMachine& target, Value* val,
155 Instruction* dest, vector<MachineInstr*>& mvec)
159 // Set the high 22 bits in dest
160 MI = Create2OperandInstr(SETHI, val, dest);
161 MI->setOperandHi32(0);
164 // Set the low 10 bits in dest
165 MI = Create3OperandInstr(OR, dest, val, dest);
166 MI->setOperandLo32(1);
171 //----------------------------------------------------------------------------
172 // Function: CreateSETXLabel
174 // Set a 64-bit constant (given by a symbolic label) in the register `dest'.
175 //----------------------------------------------------------------------------
178 CreateSETXLabel(const TargetMachine& target,
179 Value* val, Instruction* tmpReg, Instruction* dest,
180 vector<MachineInstr*>& mvec)
182 assert(isa<Constant>(val) || isa<GlobalValue>(val) &&
183 "I only know about constant values and global addresses");
187 MI = Create2OperandInstr_Addr(SETHI, val, tmpReg);
188 MI->setOperandHi64(0);
191 MI = Create3OperandInstr_Addr(OR, tmpReg, val, tmpReg);
192 MI->setOperandLo64(1);
195 MI = Create3OperandInstr_UImmed(SLLX, tmpReg, 32, tmpReg);
198 MI = Create2OperandInstr_Addr(SETHI, val, dest);
199 MI->setOperandHi32(0);
202 MI = Create3OperandInstr(OR, dest, tmpReg, dest);
205 MI = Create3OperandInstr_Addr(OR, dest, val, dest);
206 MI->setOperandLo32(1);
211 //----------------------------------------------------------------------------
212 // Function: CreateUIntSetInstruction
214 // Create code to Set an unsigned constant in the register `dest'.
215 // Uses CreateSETUWConst, CreateSETSWConst or CreateSETXConst as needed.
216 // CreateSETSWConst is an optimization for the case that the unsigned value
217 // has all ones in the 33 high bits (so that sign-extension sets them all).
218 //----------------------------------------------------------------------------
221 CreateUIntSetInstruction(const TargetMachine& target,
222 uint64_t C, Instruction* dest,
223 std::vector<MachineInstr*>& mvec,
224 MachineCodeForInstruction& mcfi)
226 static const uint64_t lo32 = (uint32_t) ~0;
227 if (C <= lo32) // High 32 bits are 0. Set low 32 bits.
228 CreateSETUWConst(target, (uint32_t) C, dest, mvec);
229 else if ((C & ~lo32) == ~lo32 && (C & (1 << 31)))
230 { // All high 33 (not 32) bits are 1s: sign-extension will take care
231 // of high 32 bits, so use the sequence for signed int
232 CreateSETSWConst(target, (int32_t) C, dest, mvec);
235 { // C does not fit in 32 bits
236 TmpInstruction* tmpReg = new TmpInstruction(Type::IntTy);
237 mcfi.addTemp(tmpReg);
238 CreateSETXConst(target, C, tmpReg, dest, mvec);
243 //----------------------------------------------------------------------------
244 // Function: CreateIntSetInstruction
246 // Create code to Set a signed constant in the register `dest'.
247 // Really the same as CreateUIntSetInstruction.
248 //----------------------------------------------------------------------------
251 CreateIntSetInstruction(const TargetMachine& target,
252 int64_t C, Instruction* dest,
253 std::vector<MachineInstr*>& mvec,
254 MachineCodeForInstruction& mcfi)
256 CreateUIntSetInstruction(target, (uint64_t) C, dest, mvec, mcfi);
260 //---------------------------------------------------------------------------
261 // class UltraSparcInstrInfo
264 // Information about individual instructions.
265 // Most information is stored in the SparcMachineInstrDesc array above.
266 // Other information is computed on demand, and most such functions
267 // default to member functions in base class MachineInstrInfo.
268 //---------------------------------------------------------------------------
271 UltraSparcInstrInfo::UltraSparcInstrInfo(const TargetMachine& tgt)
272 : MachineInstrInfo(tgt, SparcMachineInstrDesc,
273 /*descSize = */ NUM_TOTAL_OPCODES,
274 /*numRealOpCodes = */ NUM_REAL_OPCODES)
279 // Create an instruction sequence to put the constant `val' into
280 // the virtual register `dest'. `val' may be a Constant or a
281 // GlobalValue, viz., the constant address of a global variable or function.
282 // The generated instructions are returned in `mvec'.
283 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
284 // Any stack space required is allocated via MachineCodeForMethod.
287 UltraSparcInstrInfo::CreateCodeToLoadConst(const TargetMachine& target,
291 vector<MachineInstr*>& mvec,
292 MachineCodeForInstruction& mcfi) const
294 assert(isa<Constant>(val) || isa<GlobalValue>(val) &&
295 "I only know about constant values and global addresses");
297 // Use a "set" instruction for known constants or symbolic constants (labels)
298 // that can go in an integer reg.
299 // We have to use a "load" instruction for all other constants,
300 // in particular, floating point constants.
302 const Type* valType = val->getType();
304 if (isa<GlobalValue>(val))
306 TmpInstruction* tmpReg =
307 new TmpInstruction(PointerType::get(val->getType()), val);
308 mcfi.addTemp(tmpReg);
309 CreateSETXLabel(target, val, tmpReg, dest, mvec);
311 else if (valType->isIntegral())
313 bool isValidConstant;
314 unsigned opSize = target.DataLayout.getTypeSize(val->getType());
315 unsigned destSize = target.DataLayout.getTypeSize(dest->getType());
317 if (! dest->getType()->isSigned())
319 uint64_t C = GetConstantValueAsUnsignedInt(val, isValidConstant);
320 assert(isValidConstant && "Unrecognized constant");
322 if (opSize > destSize ||
323 (val->getType()->isSigned()
324 && destSize < target.DataLayout.getIntegerRegize()))
325 { // operand is larger than dest,
326 // OR both are equal but smaller than the full register size
327 // AND operand is signed, so it may have extra sign bits:
329 C = C & ((1U << 8*destSize) - 1);
331 CreateUIntSetInstruction(target, C, dest, mvec, mcfi);
335 int64_t C = GetConstantValueAsSignedInt(val, isValidConstant);
336 assert(isValidConstant && "Unrecognized constant");
338 if (opSize > destSize)
339 // operand is larger than dest: mask high bits
340 C = C & ((1U << 8*destSize) - 1);
342 if (opSize > destSize ||
343 (opSize == destSize && !val->getType()->isSigned()))
344 // sign-extend from destSize to 64 bits
345 C = ((C & (1U << (8*destSize - 1)))
346 ? C | ~((1U << 8*destSize) - 1)
349 CreateIntSetInstruction(target, C, dest, mvec, mcfi);
354 // Make an instruction sequence to load the constant, viz:
355 // SETX <addr-of-constant>, tmpReg, addrReg
356 // LOAD /*addr*/ addrReg, /*offset*/ 0, dest
358 // First, create a tmp register to be used by the SETX sequence.
359 TmpInstruction* tmpReg =
360 new TmpInstruction(PointerType::get(val->getType()), val);
361 mcfi.addTemp(tmpReg);
363 // Create another TmpInstruction for the address register
364 TmpInstruction* addrReg =
365 new TmpInstruction(PointerType::get(val->getType()), val);
366 mcfi.addTemp(addrReg);
368 // Put the address (a symbolic name) into a register
369 CreateSETXLabel(target, val, tmpReg, addrReg, mvec);
371 // Generate the load instruction
372 int64_t zeroOffset = 0; // to avoid ambiguity with (Value*) 0
374 Create3OperandInstr_SImmed(ChooseLoadInstruction(val->getType()),
375 addrReg, zeroOffset, dest);
378 // Make sure constant is emitted to constant pool in assembly code.
379 MachineCodeForMethod::get(F).addToConstantPool(cast<Constant>(val));
384 // Create an instruction sequence to copy an integer register `val'
385 // to a floating point register `dest' by copying to memory and back.
386 // val must be an integral type. dest must be a Float or Double.
387 // The generated instructions are returned in `mvec'.
388 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
389 // Any stack space required is allocated via MachineCodeForMethod.
392 UltraSparcInstrInfo::CreateCodeToCopyIntToFloat(const TargetMachine& target,
396 vector<MachineInstr*>& mvec,
397 MachineCodeForInstruction& mcfi) const
399 assert((val->getType()->isIntegral() || isa<PointerType>(val->getType()))
400 && "Source type must be integral (integer or bool) or pointer");
401 assert(dest->getType()->isFloatingPoint()
402 && "Dest type must be float/double");
404 // Get a stack slot to use for the copy
405 int offset = MachineCodeForMethod::get(F).allocateLocalVar(target, val);
407 // Get the size of the source value being copied.
408 size_t srcSize = target.DataLayout.getTypeSize(val->getType());
410 // Store instruction stores `val' to [%fp+offset].
411 // The store and load opCodes are based on the size of the source value.
412 // If the value is smaller than 32 bits, we must sign- or zero-extend it
413 // to 32 bits since the load-float will load 32 bits.
414 // Note that the store instruction is the same for signed and unsigned ints.
415 const Type* storeType = (srcSize <= 4)? Type::IntTy : Type::LongTy;
416 Value* storeVal = val;
417 if (srcSize < target.DataLayout.getTypeSize(Type::FloatTy))
418 { // sign- or zero-extend respectively
419 storeVal = new TmpInstruction(storeType, val);
420 if (val->getType()->isSigned())
421 CreateSignExtensionInstructions(target, F, val, 8*srcSize, storeVal,
424 CreateZeroExtensionInstructions(target, F, val, 8*srcSize, storeVal,
427 MachineInstr* store=new MachineInstr(ChooseStoreInstruction(storeType));
428 store->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister, storeVal);
429 store->SetMachineOperandReg(1, target.getRegInfo().getFramePointer());
430 store->SetMachineOperandConst(2,MachineOperand::MO_SignExtendedImmed,offset);
431 mvec.push_back(store);
433 // Load instruction loads [%fp+offset] to `dest'.
434 // The type of the load opCode is the floating point type that matches the
435 // stored type in size:
436 // On SparcV9: float for int or smaller, double for long.
438 const Type* loadType = (srcSize <= 4)? Type::FloatTy : Type::DoubleTy;
439 MachineInstr* load = new MachineInstr(ChooseLoadInstruction(loadType));
440 load->SetMachineOperandReg(0, target.getRegInfo().getFramePointer());
441 load->SetMachineOperandConst(1, MachineOperand::MO_SignExtendedImmed,offset);
442 load->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister, dest);
443 mvec.push_back(load);
446 // Similarly, create an instruction sequence to copy an FP register
447 // `val' to an integer register `dest' by copying to memory and back.
448 // The generated instructions are returned in `mvec'.
449 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
450 // Any stack space required is allocated via MachineCodeForMethod.
453 UltraSparcInstrInfo::CreateCodeToCopyFloatToInt(const TargetMachine& target,
457 vector<MachineInstr*>& mvec,
458 MachineCodeForInstruction& mcfi) const
460 const Type* opTy = val->getType();
461 const Type* destTy = dest->getType();
463 assert(opTy->isFloatingPoint() && "Source type must be float/double");
464 assert((destTy->isIntegral() || isa<PointerType>(destTy))
465 && "Dest type must be integer, bool or pointer");
467 int offset = MachineCodeForMethod::get(F).allocateLocalVar(target, val);
469 // Store instruction stores `val' to [%fp+offset].
470 // The store opCode is based only the source value being copied.
472 MachineInstr* store=new MachineInstr(ChooseStoreInstruction(opTy));
473 store->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister, val);
474 store->SetMachineOperandReg(1, target.getRegInfo().getFramePointer());
475 store->SetMachineOperandConst(2,MachineOperand::MO_SignExtendedImmed,offset);
476 mvec.push_back(store);
478 // Load instruction loads [%fp+offset] to `dest'.
479 // The type of the load opCode is the integer type that matches the
480 // source type in size:
481 // On SparcV9: int for float, long for double.
482 // Note that we *must* use signed loads even for unsigned dest types, to
483 // ensure correct sign-extension for UByte, UShort or UInt:
485 const Type* loadTy = (opTy == Type::FloatTy)? Type::IntTy : Type::LongTy;
486 MachineInstr* load = new MachineInstr(ChooseLoadInstruction(loadTy));
487 load->SetMachineOperandReg(0, target.getRegInfo().getFramePointer());
488 load->SetMachineOperandConst(1, MachineOperand::MO_SignExtendedImmed,offset);
489 load->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister, dest);
490 mvec.push_back(load);
494 // Create instruction(s) to copy src to dest, for arbitrary types
495 // The generated instructions are returned in `mvec'.
496 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
497 // Any stack space required is allocated via MachineCodeForMethod.
500 UltraSparcInstrInfo::CreateCopyInstructionsByType(const TargetMachine& target,
504 vector<MachineInstr*>& mvec,
505 MachineCodeForInstruction& mcfi) const
507 bool loadConstantToReg = false;
509 const Type* resultType = dest->getType();
511 MachineOpCode opCode = ChooseAddInstructionByType(resultType);
512 if (opCode == INVALID_OPCODE)
514 assert(0 && "Unsupported result type in CreateCopyInstructionsByType()");
518 // if `src' is a constant that doesn't fit in the immed field or if it is
519 // a global variable (i.e., a constant address), generate a load
520 // instruction instead of an add
522 if (isa<Constant>(src))
524 unsigned int machineRegNum;
526 MachineOperand::MachineOperandType opType =
527 ChooseRegOrImmed(src, opCode, target, /*canUseImmed*/ true,
528 machineRegNum, immedValue);
530 if (opType == MachineOperand::MO_VirtualRegister)
531 loadConstantToReg = true;
533 else if (isa<GlobalValue>(src))
534 loadConstantToReg = true;
536 if (loadConstantToReg)
537 { // `src' is constant and cannot fit in immed field for the ADD
538 // Insert instructions to "load" the constant into a register
539 target.getInstrInfo().CreateCodeToLoadConst(target, F, src, dest,
543 { // Create an add-with-0 instruction of the appropriate type.
544 // Make `src' the second operand, in case it is a constant
545 // Use (unsigned long) 0 for a NULL pointer value.
547 const Type* zeroValueType =
548 isa<PointerType>(resultType) ? Type::ULongTy : resultType;
549 MachineInstr* minstr =
550 Create3OperandInstr(opCode, Constant::getNullValue(zeroValueType),
552 mvec.push_back(minstr);
557 // Helper function for sign-extension and zero-extension.
558 // For SPARC v9, we sign-extend the given operand using SLL; SRA/SRL.
560 CreateBitExtensionInstructions(bool signExtend,
561 const TargetMachine& target,
564 unsigned int srcSizeInBits,
566 vector<MachineInstr*>& mvec,
567 MachineCodeForInstruction& mcfi)
570 assert(srcSizeInBits <= 32 &&
571 "Hmmm... 32 < srcSizeInBits < 64 unexpected but could be handled.");
573 if (srcSizeInBits < 32)
574 { // SLL is needed since operand size is < 32 bits.
575 TmpInstruction *tmpI = new TmpInstruction(dest->getType(),
576 srcVal, dest,"make32");
578 M = Create3OperandInstr_UImmed(SLLX, srcVal, 32-srcSizeInBits, tmpI);
583 M = Create3OperandInstr_UImmed(signExtend? SRA : SRL,
584 srcVal, 32-srcSizeInBits, dest);
589 // Create instruction sequence to produce a sign-extended register value
590 // from an arbitrary-sized integer value (sized in bits, not bytes).
591 // The generated instructions are returned in `mvec'.
592 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
593 // Any stack space required is allocated via MachineCodeForMethod.
596 UltraSparcInstrInfo::CreateSignExtensionInstructions(
597 const TargetMachine& target,
600 unsigned int srcSizeInBits,
602 vector<MachineInstr*>& mvec,
603 MachineCodeForInstruction& mcfi) const
605 CreateBitExtensionInstructions(/*signExtend*/ true, target, F, srcVal,
606 srcSizeInBits, dest, mvec, mcfi);
610 // Create instruction sequence to produce a zero-extended register value
611 // from an arbitrary-sized integer value (sized in bits, not bytes).
612 // For SPARC v9, we sign-extend the given operand using SLL; SRL.
613 // The generated instructions are returned in `mvec'.
614 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
615 // Any stack space required is allocated via MachineCodeForMethod.
618 UltraSparcInstrInfo::CreateZeroExtensionInstructions(
619 const TargetMachine& target,
622 unsigned int srcSizeInBits,
624 vector<MachineInstr*>& mvec,
625 MachineCodeForInstruction& mcfi) const
627 CreateBitExtensionInstructions(/*signExtend*/ false, target, F, srcVal,
628 srcSizeInBits, dest, mvec, mcfi);