1 //===-- SparcInstrInfo.cpp ------------------------------------------------===//
3 //===----------------------------------------------------------------------===//
5 #include "SparcInternals.h"
6 #include "SparcInstrSelectionSupport.h"
7 #include "llvm/CodeGen/InstrSelection.h"
8 #include "llvm/CodeGen/InstrSelectionSupport.h"
9 #include "llvm/CodeGen/MachineCodeForMethod.h"
10 #include "llvm/CodeGen/MachineCodeForInstruction.h"
11 #include "llvm/Function.h"
12 #include "llvm/Constants.h"
13 #include "llvm/DerivedTypes.h"
16 static const uint32_t MAXLO = (1 << 10) - 1; // set bits set by %lo(*)
17 static const uint32_t MAXSIMM = (1 << 12) - 1; // set bits in simm13 field of OR
20 // Set a 32-bit unsigned constant in the register `dest'.
23 CreateSETUWConst(const TargetMachine& target, uint32_t C,
24 Instruction* dest, vector<MachineInstr*>& mvec)
26 MachineInstr *miSETHI = NULL, *miOR = NULL;
28 // In order to get efficient code, we should not generate the SETHI if
29 // all high bits are 1 (i.e., this is a small signed value that fits in
30 // the simm13 field of OR). So we check for and handle that case specially.
31 // NOTE: The value C = 0x80000000 is bad: sC < 0 *and* -sC < 0.
32 // In fact, sC == -sC, so we have to check for this explicitly.
33 int32_t sC = (int32_t) C;
34 bool smallSignedValue = sC < 0 && sC != -sC && -sC < (int32_t) MAXSIMM;
36 // Set the high 22 bits in dest if non-zero and simm13 field of OR not enough
37 if (!smallSignedValue && (C & ~MAXLO) && C > MAXSIMM)
39 miSETHI = Create2OperandInstr_UImmed(SETHI, C, dest);
40 miSETHI->setOperandHi32(0);
41 mvec.push_back(miSETHI);
44 // Set the low 10 or 12 bits in dest. This is necessary if no SETHI
45 // was generated, or if the low 10 bits are non-zero.
46 if (miSETHI==NULL || C & MAXLO)
49 { // unsigned value with high-order bits set using SETHI
50 miOR = Create3OperandInstr_UImmed(OR, dest, C, dest);
51 miOR->setOperandLo32(1);
54 { // unsigned or small signed value that fits in simm13 field of OR
55 assert(smallSignedValue || (C & ~MAXSIMM) == 0);
56 miOR = new MachineInstr(OR);
57 miOR->SetMachineOperandReg(0, target.getRegInfo().getZeroRegNum());
58 miOR->SetMachineOperandConst(1, MachineOperand::MO_SignExtendedImmed,
60 miOR->SetMachineOperandVal(2,MachineOperand::MO_VirtualRegister,dest);
65 assert((miSETHI || miOR) && "Oops, no code was generated!");
68 // Set a 32-bit constant (given by a symbolic label) in the register `dest'.
69 // Not needed for SPARC v9 but useful to make the two SETX functions similar
71 CreateSETUWLabel(const TargetMachine& target, Value* val,
72 Instruction* dest, vector<MachineInstr*>& mvec)
76 // Set the high 22 bits in dest
77 MI = Create2OperandInstr(SETHI, val, dest);
78 MI->setOperandHi32(0);
81 // Set the low 10 bits in dest
82 MI = Create3OperandInstr(OR, dest, val, dest);
83 MI->setOperandLo32(1);
88 // Set a 32-bit signed constant in the register `dest',
89 // with sign-extension to 64 bits.
91 CreateSETSWConst(const TargetMachine& target, int32_t C,
92 Instruction* dest, vector<MachineInstr*>& mvec)
96 // Set the low 32 bits of dest
97 CreateSETUWConst(target, (uint32_t) C, dest, mvec);
99 // Sign-extend to the high 32 bits if needed
100 if (C < 0 && (-C) > (int32_t) MAXSIMM)
102 MI = Create3OperandInstr_UImmed(SRA, dest, 0, dest);
108 // Set a 64-bit signed or unsigned constant in the register `dest'.
110 CreateSETXConst(const TargetMachine& target, uint64_t C,
111 Instruction* tmpReg, Instruction* dest,
112 vector<MachineInstr*>& mvec)
114 assert(C > (unsigned int) ~0 && "Use SETUW/SETSW for 32-bit values!");
118 // Code to set the upper 32 bits of the value in register `tmpReg'
119 CreateSETUWConst(target, (C >> 32), tmpReg, mvec);
121 // Shift tmpReg left by 32 bits
122 MI = Create3OperandInstr_UImmed(SLLX, tmpReg, 32, tmpReg);
125 // Code to set the low 32 bits of the value in register `dest'
126 CreateSETUWConst(target, C, dest, mvec);
128 // dest = OR(tmpReg, dest)
129 MI = Create3OperandInstr(OR, dest, tmpReg, dest);
134 // Set a 64-bit constant (given by a symbolic label) in the register `dest'.
136 CreateSETXLabel(const TargetMachine& target,
137 Value* val, Instruction* tmpReg, Instruction* dest,
138 vector<MachineInstr*>& mvec)
140 assert(isa<Constant>(val) || isa<GlobalValue>(val) &&
141 "I only know about constant values and global addresses");
145 MI = Create2OperandInstr_Addr(SETHI, val, tmpReg);
146 MI->setOperandHi64(0);
149 MI = Create3OperandInstr_Addr(OR, tmpReg, val, tmpReg);
150 MI->setOperandLo64(1);
153 MI = Create3OperandInstr_UImmed(SLLX, tmpReg, 32, tmpReg);
156 MI = Create2OperandInstr_Addr(SETHI, val, dest);
157 MI->setOperandHi32(0);
160 MI = Create3OperandInstr(OR, dest, tmpReg, dest);
163 MI = Create3OperandInstr_Addr(OR, dest, val, dest);
164 MI->setOperandLo32(1);
170 CreateIntSetInstruction(const TargetMachine& target,
171 int64_t C, Instruction* dest,
172 vector<MachineInstr*>& mvec,
173 MachineCodeForInstruction& mcfi)
175 assert(dest->getType()->isSigned() && "Use CreateUIntSetInstruction()");
177 uint64_t absC = (C >= 0)? C : -C;
178 if (absC > (uint32_t) ~0)
179 { // C does not fit in 32 bits
180 TmpInstruction* tmpReg = new TmpInstruction(Type::IntTy);
181 mcfi.addTemp(tmpReg);
182 CreateSETXConst(target, (uint64_t) C, tmpReg, dest, mvec);
185 CreateSETSWConst(target, (int32_t) C, dest, mvec);
190 CreateUIntSetInstruction(const TargetMachine& target,
191 uint64_t C, Instruction* dest,
192 vector<MachineInstr*>& mvec,
193 MachineCodeForInstruction& mcfi)
195 assert(! dest->getType()->isSigned() && "Use CreateIntSetInstruction()");
198 if (C > (uint32_t) ~0)
199 { // C does not fit in 32 bits
200 assert(dest->getType() == Type::ULongTy && "Sign extension problems");
201 TmpInstruction *tmpReg = new TmpInstruction(Type::IntTy);
202 mcfi.addTemp(tmpReg);
203 CreateSETXConst(target, C, tmpReg, dest, mvec);
206 CreateSETUWConst(target, C, dest, mvec);
212 //---------------------------------------------------------------------------
213 // class UltraSparcInstrInfo
216 // Information about individual instructions.
217 // Most information is stored in the SparcMachineInstrDesc array above.
218 // Other information is computed on demand, and most such functions
219 // default to member functions in base class MachineInstrInfo.
220 //---------------------------------------------------------------------------
223 UltraSparcInstrInfo::UltraSparcInstrInfo(const TargetMachine& tgt)
224 : MachineInstrInfo(tgt, SparcMachineInstrDesc,
225 /*descSize = */ NUM_TOTAL_OPCODES,
226 /*numRealOpCodes = */ NUM_REAL_OPCODES)
231 // Create an instruction sequence to put the constant `val' into
232 // the virtual register `dest'. `val' may be a Constant or a
233 // GlobalValue, viz., the constant address of a global variable or function.
234 // The generated instructions are returned in `mvec'.
235 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
236 // Any stack space required is allocated via MachineCodeForMethod.
239 UltraSparcInstrInfo::CreateCodeToLoadConst(const TargetMachine& target,
243 vector<MachineInstr*>& mvec,
244 MachineCodeForInstruction& mcfi) const
246 assert(isa<Constant>(val) || isa<GlobalValue>(val) &&
247 "I only know about constant values and global addresses");
249 // Use a "set" instruction for known constants or symbolic constants (labels)
250 // that can go in an integer reg.
251 // We have to use a "load" instruction for all other constants,
252 // in particular, floating point constants.
254 const Type* valType = val->getType();
256 if (isa<GlobalValue>(val) || valType->isIntegral() || valType == Type::BoolTy)
258 if (isa<GlobalValue>(val))
260 TmpInstruction* tmpReg =
261 new TmpInstruction(PointerType::get(val->getType()), val);
262 mcfi.addTemp(tmpReg);
263 CreateSETXLabel(target, val, tmpReg, dest, mvec);
265 else if (! dest->getType()->isSigned())
267 bool isValidConstant;
268 uint64_t C = GetConstantValueAsUnsignedInt(val, isValidConstant);
269 assert(isValidConstant && "Unrecognized constant");
270 CreateUIntSetInstruction(target, C, dest, mvec, mcfi);
274 bool isValidConstant;
275 int64_t C = GetConstantValueAsSignedInt(val, isValidConstant);
276 assert(isValidConstant && "Unrecognized constant");
277 CreateIntSetInstruction(target, C, dest, mvec, mcfi);
282 // Make an instruction sequence to load the constant, viz:
283 // SETX <addr-of-constant>, tmpReg, addrReg
284 // LOAD /*addr*/ addrReg, /*offset*/ 0, dest
286 // First, create a tmp register to be used by the SETX sequence.
287 TmpInstruction* tmpReg =
288 new TmpInstruction(PointerType::get(val->getType()), val);
289 mcfi.addTemp(tmpReg);
291 // Create another TmpInstruction for the address register
292 TmpInstruction* addrReg =
293 new TmpInstruction(PointerType::get(val->getType()), val);
294 mcfi.addTemp(addrReg);
296 // Put the address (a symbolic name) into a register
297 CreateSETXLabel(target, val, tmpReg, addrReg, mvec);
299 // Generate the load instruction
300 int64_t zeroOffset = 0; // to avoid ambiguity with (Value*) 0
302 Create3OperandInstr_SImmed(ChooseLoadInstruction(val->getType()),
303 addrReg, zeroOffset, dest);
306 // Make sure constant is emitted to constant pool in assembly code.
307 MachineCodeForMethod::get(F).addToConstantPool(cast<Constant>(val));
312 // Create an instruction sequence to copy an integer value `val'
313 // to a floating point value `dest' by copying to memory and back.
314 // val must be an integral type. dest must be a Float or Double.
315 // The generated instructions are returned in `mvec'.
316 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
317 // Any stack space required is allocated via MachineCodeForMethod.
320 UltraSparcInstrInfo::CreateCodeToCopyIntToFloat(const TargetMachine& target,
324 vector<MachineInstr*>& mvec,
325 MachineCodeForInstruction& mcfi) const
327 assert((val->getType()->isIntegral() || isa<PointerType>(val->getType()))
328 && "Source type must be integral");
329 assert(dest->getType()->isFloatingPoint()
330 && "Dest type must be float/double");
332 int offset = MachineCodeForMethod::get(F).allocateLocalVar(target, val);
334 // Store instruction stores `val' to [%fp+offset].
335 // The store and load opCodes are based on the value being copied, and
336 // they use integer and float types that accomodate the
337 // larger of the source type and the destination type:
338 // On SparcV9: int for float, long for double.
339 // Note that the store instruction is the same for signed and unsigned ints.
340 Type* tmpType = (dest->getType() == Type::FloatTy)? Type::IntTy
342 MachineInstr* store = new MachineInstr(ChooseStoreInstruction(tmpType));
343 store->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister, val);
344 store->SetMachineOperandReg(1, target.getRegInfo().getFramePointer());
345 store->SetMachineOperandConst(2,MachineOperand::MO_SignExtendedImmed,offset);
346 mvec.push_back(store);
348 // Load instruction loads [%fp+offset] to `dest'.
350 MachineInstr* load =new MachineInstr(ChooseLoadInstruction(dest->getType()));
351 load->SetMachineOperandReg(0, target.getRegInfo().getFramePointer());
352 load->SetMachineOperandConst(1, MachineOperand::MO_SignExtendedImmed,offset);
353 load->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister, dest);
354 mvec.push_back(load);
358 // Similarly, create an instruction sequence to copy an FP value
359 // `val' to an integer value `dest' by copying to memory and back.
360 // The generated instructions are returned in `mvec'.
361 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
362 // Any stack space required is allocated via MachineCodeForMethod.
365 UltraSparcInstrInfo::CreateCodeToCopyFloatToInt(const TargetMachine& target,
369 vector<MachineInstr*>& mvec,
370 MachineCodeForInstruction& mcfi) const
372 const Type* opTy = val->getType();
373 const Type* destTy = dest->getType();
375 assert(opTy->isFloatingPoint() && "Source type must be float/double");
376 assert((destTy->isIntegral() || isa<PointerType>(destTy))
377 && "Dest type must be integral");
379 int offset = MachineCodeForMethod::get(F).allocateLocalVar(target, val);
381 // Store instruction stores `val' to [%fp+offset].
382 // The store opCode is based only the source value being copied.
384 MachineInstr* store=new MachineInstr(ChooseStoreInstruction(val->getType()));
385 store->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister, val);
386 store->SetMachineOperandReg(1, target.getRegInfo().getFramePointer());
387 store->SetMachineOperandConst(2,MachineOperand::MO_SignExtendedImmed,offset);
388 mvec.push_back(store);
390 // Load instruction loads [%fp+offset] to `dest'.
391 // The type of the load opCode is the integer type that matches the
392 // source type in size: (and the dest type in sign):
393 // On SparcV9: int for float, long for double.
394 // Note that we *must* use signed loads even for unsigned dest types, to
395 // ensure that we get the right sign-extension for smaller-than-64-bit
396 // unsigned dest. types (i.e., UByte, UShort or UInt):
397 const Type* loadTy = opTy == Type::FloatTy? Type::IntTy : Type::LongTy;
398 MachineInstr* load = new MachineInstr(ChooseLoadInstruction(loadTy));
399 load->SetMachineOperandReg(0, target.getRegInfo().getFramePointer());
400 load->SetMachineOperandConst(1, MachineOperand::MO_SignExtendedImmed,offset);
401 load->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister, dest);
402 mvec.push_back(load);
406 // Create instruction(s) to copy src to dest, for arbitrary types
407 // The generated instructions are returned in `mvec'.
408 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
409 // Any stack space required is allocated via MachineCodeForMethod.
412 UltraSparcInstrInfo::CreateCopyInstructionsByType(const TargetMachine& target,
416 vector<MachineInstr*>& mvec,
417 MachineCodeForInstruction& mcfi) const
419 bool loadConstantToReg = false;
421 const Type* resultType = dest->getType();
423 MachineOpCode opCode = ChooseAddInstructionByType(resultType);
424 if (opCode == INVALID_OPCODE)
426 assert(0 && "Unsupported result type in CreateCopyInstructionsByType()");
430 // if `src' is a constant that doesn't fit in the immed field or if it is
431 // a global variable (i.e., a constant address), generate a load
432 // instruction instead of an add
434 if (isa<Constant>(src))
436 unsigned int machineRegNum;
438 MachineOperand::MachineOperandType opType =
439 ChooseRegOrImmed(src, opCode, target, /*canUseImmed*/ true,
440 machineRegNum, immedValue);
442 if (opType == MachineOperand::MO_VirtualRegister)
443 loadConstantToReg = true;
445 else if (isa<GlobalValue>(src))
446 loadConstantToReg = true;
448 if (loadConstantToReg)
449 { // `src' is constant and cannot fit in immed field for the ADD
450 // Insert instructions to "load" the constant into a register
451 target.getInstrInfo().CreateCodeToLoadConst(target, F, src, dest,
455 { // Create an add-with-0 instruction of the appropriate type.
456 // Make `src' the second operand, in case it is a constant
457 // Use (unsigned long) 0 for a NULL pointer value.
459 const Type* zeroValueType =
460 isa<PointerType>(resultType) ? Type::ULongTy : resultType;
461 MachineInstr* minstr =
462 Create3OperandInstr(opCode, Constant::getNullValue(zeroValueType),
464 mvec.push_back(minstr);
469 // Create instruction sequence to produce a sign-extended register value
470 // from an arbitrary sized value (sized in bits, not bytes).
471 // For SPARC v9, we sign-extend the given unsigned operand using SLL; SRA.
472 // The generated instructions are returned in `mvec'.
473 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
474 // Any stack space required is allocated via MachineCodeForMethod.
477 UltraSparcInstrInfo::CreateSignExtensionInstructions(
478 const TargetMachine& target,
480 Value* unsignedSrcVal,
481 unsigned int srcSizeInBits,
483 vector<MachineInstr*>& mvec,
484 MachineCodeForInstruction& mcfi) const
487 assert(srcSizeInBits < 64 && "Sign extension unnecessary!");
488 assert(srcSizeInBits > 0 && srcSizeInBits <= 32
489 && "Hmmm... 32 < srcSizeInBits < 64 unexpected but could be handled here.");
491 if (srcSizeInBits < 32)
492 { // SLL is needed since operand size is < 32 bits.
493 TmpInstruction *tmpI = new TmpInstruction(dest->getType(),
494 unsignedSrcVal, dest,"make32");
496 M = Create3OperandInstr_UImmed(SLL,unsignedSrcVal,32-srcSizeInBits,tmpI);
498 unsignedSrcVal = tmpI;
501 M = Create3OperandInstr_UImmed(SRA, unsignedSrcVal, 32-srcSizeInBits, dest);