2 //***************************************************************************
9 // 10/15/01 - Vikram Adve - Created
10 //**************************************************************************/
13 #include "SparcInternals.h"
14 #include "SparcInstrSelectionSupport.h"
15 #include "llvm/Target/Sparc.h"
16 #include "llvm/CodeGen/InstrSelection.h"
17 #include "llvm/CodeGen/InstrSelectionSupport.h"
18 #include "llvm/CodeGen/MachineInstr.h"
19 #include "llvm/CodeGen/MachineCodeForMethod.h"
20 #include "llvm/Function.h"
21 #include "llvm/Constants.h"
22 #include "llvm/DerivedTypes.h"
25 //************************ Internal Functions ******************************/
28 static inline MachineInstr*
29 CreateIntSetInstruction(int64_t C, Value* dest,
30 std::vector<TmpInstruction*>& tempVec)
33 uint64_t absC = (C >= 0)? C : -C;
34 if (absC > (unsigned int) ~0)
35 { // C does not fit in 32 bits
36 TmpInstruction* tmpReg = new TmpInstruction(Type::IntTy);
37 tempVec.push_back(tmpReg);
39 minstr = new MachineInstr(SETX);
40 minstr->SetMachineOperandConst(0, MachineOperand::MO_SignExtendedImmed, C);
41 minstr->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister, tmpReg,
43 minstr->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister,dest);
47 minstr = new MachineInstr(SETSW);
48 minstr->SetMachineOperandConst(0,MachineOperand::MO_SignExtendedImmed,C);
49 minstr->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister,dest);
55 static inline MachineInstr*
56 CreateUIntSetInstruction(uint64_t C, Value* dest,
57 std::vector<TmpInstruction*>& tempVec)
60 if (C > (unsigned int) ~0)
61 { // C does not fit in 32 bits
62 assert(dest->getType() == Type::ULongTy && "Sign extension problems");
63 TmpInstruction *tmpReg = new TmpInstruction(Type::IntTy);
64 tempVec.push_back(tmpReg);
66 minstr = new MachineInstr(SETX);
67 minstr->SetMachineOperandConst(0,MachineOperand::MO_SignExtendedImmed,C);
68 minstr->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister,
69 tmpReg, /*isdef*/ true);
70 minstr->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister,dest);
72 else if (dest->getType() == Type::ULongTy)
74 minstr = new MachineInstr(SETUW);
75 minstr->SetMachineOperandConst(0, MachineOperand::MO_UnextendedImmed, C);
76 minstr->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister,dest);
79 { // cast to signed type of the right length and use signed op (SETSW)
80 // to get correct sign extension
82 minstr = new MachineInstr(SETSW);
83 minstr->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister,dest);
85 switch (dest->getType()->getPrimitiveID())
88 minstr->SetMachineOperandConst(0,
89 MachineOperand::MO_SignExtendedImmed,
92 case Type::UShortTyID:
93 minstr->SetMachineOperandConst(0,
94 MachineOperand::MO_SignExtendedImmed,
98 minstr->SetMachineOperandConst(0,
99 MachineOperand::MO_SignExtendedImmed,
103 assert(0 && "Unexpected unsigned type");
111 //************************* External Classes *******************************/
113 //---------------------------------------------------------------------------
114 // class UltraSparcInstrInfo
117 // Information about individual instructions.
118 // Most information is stored in the SparcMachineInstrDesc array above.
119 // Other information is computed on demand, and most such functions
120 // default to member functions in base class MachineInstrInfo.
121 //---------------------------------------------------------------------------
124 UltraSparcInstrInfo::UltraSparcInstrInfo(const TargetMachine& tgt)
125 : MachineInstrInfo(tgt, SparcMachineInstrDesc,
126 /*descSize = */ NUM_TOTAL_OPCODES,
127 /*numRealOpCodes = */ NUM_REAL_OPCODES)
132 // Create an instruction sequence to put the constant `val' into
133 // the virtual register `dest'. `val' may be a Constant or a
134 // GlobalValue, viz., the constant address of a global variable or function.
135 // The generated instructions are returned in `minstrVec'.
136 // Any temp. registers (TmpInstruction) created are returned in `tempVec'.
139 UltraSparcInstrInfo::CreateCodeToLoadConst(Function *F, Value* val,
141 std::vector<MachineInstr*>&minstrVec,
142 std::vector<TmpInstruction*>& tempVec) const
144 MachineInstr* minstr;
146 assert(isa<Constant>(val) || isa<GlobalValue>(val) &&
147 "I only know about constant values and global addresses");
149 // Use a "set" instruction for known constants that can go in an integer reg.
150 // Use a "load" instruction for all other constants, in particular,
151 // floating point constants and addresses of globals.
153 const Type* valType = val->getType();
155 if (valType->isIntegral() || valType == Type::BoolTy)
157 if (ConstantUInt* uval = dyn_cast<ConstantUInt>(val))
159 uint64_t C = uval->getValue();
160 minstr = CreateUIntSetInstruction(C, dest, tempVec);
164 bool isValidConstant;
165 int64_t C = GetConstantValueAsSignedInt(val, isValidConstant);
166 assert(isValidConstant && "Unrecognized constant");
167 minstr = CreateIntSetInstruction(C, dest, tempVec);
169 minstrVec.push_back(minstr);
173 // Make an instruction sequence to load the constant, viz:
174 // SETX <addr-of-constant>, tmpReg, addrReg
175 // LOAD /*addr*/ addrReg, /*offset*/ 0, dest
176 // Only the SETX is needed if `val' is a GlobalValue, i.e,. it is
177 // itself a constant address. Otherwise, both are needed.
180 int64_t zeroOffset = 0; // to avoid ambiguity with (Value*) 0
182 TmpInstruction* tmpReg =
183 new TmpInstruction(PointerType::get(val->getType()), val);
184 tempVec.push_back(tmpReg);
186 if (isa<Constant>(val))
188 // Create another TmpInstruction for the hidden integer register
189 TmpInstruction* addrReg =
190 new TmpInstruction(PointerType::get(val->getType()), val);
191 tempVec.push_back(addrReg);
197 minstr = new MachineInstr(SETX);
198 minstr->SetMachineOperandVal(0, MachineOperand::MO_PCRelativeDisp, val);
199 minstr->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister,tmpReg,
201 minstr->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister,
203 minstrVec.push_back(minstr);
205 if (isa<Constant>(val))
207 // Make sure constant is emitted to constant pool in assembly code.
208 MachineCodeForMethod& mcinfo = MachineCodeForMethod::get(F);
209 mcinfo.addToConstantPool(cast<Constant>(val));
211 // Generate the load instruction
212 minstr = new MachineInstr(ChooseLoadInstruction(val->getType()));
213 minstr->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister,
215 minstr->SetMachineOperandConst(1,MachineOperand::MO_SignExtendedImmed,
217 minstr->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister,
219 minstrVec.push_back(minstr);
225 // Create an instruction sequence to copy an integer value `val'
226 // to a floating point value `dest' by copying to memory and back.
227 // val must be an integral type. dest must be a Float or Double.
228 // The generated instructions are returned in `minstrVec'.
229 // Any temp. registers (TmpInstruction) created are returned in `tempVec'.
232 UltraSparcInstrInfo::CreateCodeToCopyIntToFloat(Function *F,
235 std::vector<MachineInstr*>& minstrVec,
236 std::vector<TmpInstruction*>& tempVec,
237 TargetMachine& target) const
239 assert((val->getType()->isIntegral() || val->getType()->isPointerType())
240 && "Source type must be integral");
241 assert((dest->getType() == Type::FloatTy || dest->getType() == Type::DoubleTy)
242 && "Dest type must be float/double");
244 MachineCodeForMethod& mcinfo = MachineCodeForMethod::get(F);
245 int offset = mcinfo.allocateLocalVar(target, val);
247 // Store instruction stores `val' to [%fp+offset].
248 // The store and load opCodes are based on the value being copied, and
249 // they use integer and float types that accomodate the
250 // larger of the source type and the destination type:
251 // On SparcV9: int for float, long for double.
253 Type* tmpType = (dest->getType() == Type::FloatTy)? Type::IntTy
255 MachineInstr* store = new MachineInstr(ChooseStoreInstruction(tmpType));
256 store->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister, val);
257 store->SetMachineOperandReg(1, target.getRegInfo().getFramePointer());
258 store->SetMachineOperandConst(2,MachineOperand::MO_SignExtendedImmed, offset);
259 minstrVec.push_back(store);
261 // Load instruction loads [%fp+offset] to `dest'.
263 MachineInstr* load =new MachineInstr(ChooseLoadInstruction(dest->getType()));
264 load->SetMachineOperandReg(0, target.getRegInfo().getFramePointer());
265 load->SetMachineOperandConst(1, MachineOperand::MO_SignExtendedImmed,offset);
266 load->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister, dest);
267 minstrVec.push_back(load);
271 // Similarly, create an instruction sequence to copy an FP value
272 // `val' to an integer value `dest' by copying to memory and back.
273 // See the previous function for information about return values.
276 UltraSparcInstrInfo::CreateCodeToCopyFloatToInt(Function *F,
279 std::vector<MachineInstr*>& minstrVec,
280 std::vector<TmpInstruction*>& tempVec,
281 TargetMachine& target) const
283 assert((val->getType() ==Type::FloatTy || val->getType() ==Type::DoubleTy)
284 && "Source type must be float/double");
285 assert((dest->getType()->isIntegral() || dest->getType()->isPointerType())
286 && "Dest type must be integral");
288 MachineCodeForMethod& mcinfo = MachineCodeForMethod::get(F);
289 int offset = mcinfo.allocateLocalVar(target, val);
291 // Store instruction stores `val' to [%fp+offset].
292 // The store and load opCodes are based on the value being copied, and
293 // they use the integer type that matches the source type in size:
294 // On SparcV9: int for float, long for double.
296 Type* tmpType = (val->getType() == Type::FloatTy)? Type::IntTy
298 MachineInstr* store=new MachineInstr(ChooseStoreInstruction(val->getType()));
299 store->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister, val);
300 store->SetMachineOperandReg(1, target.getRegInfo().getFramePointer());
301 store->SetMachineOperandConst(2,MachineOperand::MO_SignExtendedImmed,offset);
302 minstrVec.push_back(store);
304 // Load instruction loads [%fp+offset] to `dest'.
306 MachineInstr* load = new MachineInstr(ChooseLoadInstruction(tmpType));
307 load->SetMachineOperandReg(0, target.getRegInfo().getFramePointer());
308 load->SetMachineOperandConst(1, MachineOperand::MO_SignExtendedImmed, offset);
309 load->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister, dest);
310 minstrVec.push_back(load);