1 //***************************************************************************
8 // 10/15/01 - Vikram Adve - Created
9 //**************************************************************************/
12 #include "SparcInternals.h"
13 #include "SparcInstrSelectionSupport.h"
14 #include "llvm/Target/Sparc.h"
15 #include "llvm/CodeGen/InstrSelection.h"
16 #include "llvm/CodeGen/InstrSelectionSupport.h"
17 #include "llvm/CodeGen/MachineCodeForMethod.h"
18 #include "llvm/CodeGen/MachineCodeForInstruction.h"
19 #include "llvm/Function.h"
20 #include "llvm/BasicBlock.h"
21 #include "llvm/Instruction.h"
22 #include "llvm/Constants.h"
23 #include "llvm/DerivedTypes.h"
26 //************************ Internal Functions ******************************/
28 static const uint32_t MAXLO = (1 << 10) - 1; // set bits set by %lo(*)
29 static const uint32_t MAXSIMM = (1 << 12) - 1; // set bits in simm13 field of OR
32 // Set a 32-bit unsigned constant in the register `dest'.
35 CreateSETUWConst(const TargetMachine& target, uint32_t C,
36 Instruction* dest, std::vector<MachineInstr*>& mvec)
38 MachineInstr *miSETHI = NULL, *miOR = NULL;
40 // In order to get efficient code, we should not generate the SETHI if
41 // all high bits are 1 (i.e., this is a small signed value that fits in
42 // the simm13 field of OR). So we check for and handle that case specially.
43 // NOTE: The value C = 0x80000000 is bad: sC < 0 *and* -sC < 0.
44 // In fact, sC == -sC, so we have to check for this explicitly.
45 int32_t sC = (int32_t) C;
46 bool smallSignedValue = sC < 0 && sC != -sC && -sC < (int32_t) MAXSIMM;
48 // Set the high 22 bits in dest if non-zero and simm13 field of OR not enough
49 if (!smallSignedValue && (C & ~MAXLO) && C > MAXSIMM)
51 miSETHI = Create2OperandInstr_UImmed(SETHI, C, dest);
52 miSETHI->setOperandHi32(0);
53 mvec.push_back(miSETHI);
56 // Set the low 10 or 12 bits in dest. This is necessary if no SETHI
57 // was generated, or if the low 10 bits are non-zero.
58 if (miSETHI==NULL || C & MAXLO)
61 { // unsigned value with high-order bits set using SETHI
62 miOR = Create3OperandInstr_UImmed(OR, dest, C, dest);
63 miOR->setOperandLo32(1);
66 { // unsigned or small signed value that fits in simm13 field of OR
67 assert(smallSignedValue || (C & ~MAXSIMM) == 0);
68 miOR = new MachineInstr(OR);
69 miOR->SetMachineOperandReg(0, target.getRegInfo().getZeroRegNum());
70 miOR->SetMachineOperandConst(1, MachineOperand::MO_SignExtendedImmed,
72 miOR->SetMachineOperandVal(2,MachineOperand::MO_VirtualRegister,dest);
77 assert((miSETHI || miOR) && "Oops, no code was generated!");
80 // Set a 32-bit constant (given by a symbolic label) in the register `dest'.
81 // Not needed for SPARC v9 but useful to make the two SETX functions similar
83 CreateSETUWLabel(const TargetMachine& target, Value* val,
84 Instruction* dest, std::vector<MachineInstr*>& mvec)
88 // Set the high 22 bits in dest
89 MI = Create2OperandInstr(SETHI, val, dest);
90 MI->setOperandHi32(0);
93 // Set the low 10 bits in dest
94 MI = Create3OperandInstr(OR, dest, val, dest);
95 MI->setOperandLo32(1);
100 // Set a 32-bit signed constant in the register `dest',
101 // with sign-extension to 64 bits.
103 CreateSETSWConst(const TargetMachine& target, int32_t C,
104 Instruction* dest, std::vector<MachineInstr*>& mvec)
108 // Set the low 32 bits of dest
109 CreateSETUWConst(target, (uint32_t) C, dest, mvec);
111 // Sign-extend to the high 32 bits if needed
112 if (C < 0 && (-C) > (int32_t) MAXSIMM)
114 MI = Create3OperandInstr_UImmed(SRA, dest, 0, dest);
120 // Set a 64-bit signed or unsigned constant in the register `dest'.
122 CreateSETXConst(const TargetMachine& target, uint64_t C,
123 Instruction* tmpReg, Instruction* dest,
124 std::vector<MachineInstr*>& mvec)
126 assert(C > (unsigned int) ~0 && "Use SETUW/SETSW for 32-bit values!");
130 // Code to set the upper 32 bits of the value in register `tmpReg'
131 CreateSETUWConst(target, (C >> 32), tmpReg, mvec);
133 // Shift tmpReg left by 32 bits
134 MI = Create3OperandInstr_UImmed(SLLX, tmpReg, 32, tmpReg);
137 // Code to set the low 32 bits of the value in register `dest'
138 CreateSETUWConst(target, C, dest, mvec);
140 // dest = OR(tmpReg, dest)
141 MI = Create3OperandInstr(OR, dest, tmpReg, dest);
146 // Set a 64-bit constant (given by a symbolic label) in the register `dest'.
148 CreateSETXLabel(const TargetMachine& target,
149 Value* val, Instruction* tmpReg, Instruction* dest,
150 std::vector<MachineInstr*>& mvec)
152 assert(isa<Constant>(val) || isa<GlobalValue>(val) &&
153 "I only know about constant values and global addresses");
157 MI = Create2OperandInstr_Addr(SETHI, val, tmpReg);
158 MI->setOperandHi64(0);
161 MI = Create3OperandInstr_Addr(OR, tmpReg, val, tmpReg);
162 MI->setOperandLo64(1);
165 MI = Create3OperandInstr_UImmed(SLLX, tmpReg, 32, tmpReg);
168 MI = Create2OperandInstr_Addr(SETHI, val, dest);
169 MI->setOperandHi32(0);
172 MI = Create3OperandInstr(OR, dest, tmpReg, dest);
175 MI = Create3OperandInstr_Addr(OR, dest, val, dest);
176 MI->setOperandLo32(1);
182 CreateIntSetInstruction(const TargetMachine& target,
183 int64_t C, Instruction* dest,
184 std::vector<MachineInstr*>& mvec,
185 MachineCodeForInstruction& mcfi)
187 assert(dest->getType()->isSigned() && "Use CreateUIntSetInstruction()");
189 uint64_t absC = (C >= 0)? C : -C;
190 if (absC > (unsigned int) ~0)
191 { // C does not fit in 32 bits
192 TmpInstruction* tmpReg = new TmpInstruction(Type::IntTy);
193 mcfi.addTemp(tmpReg);
194 CreateSETXConst(target, (uint64_t) C, tmpReg, dest, mvec);
197 CreateSETSWConst(target, (int32_t) C, dest, mvec);
202 CreateUIntSetInstruction(const TargetMachine& target,
203 uint64_t C, Instruction* dest,
204 std::vector<MachineInstr*>& mvec,
205 MachineCodeForInstruction& mcfi)
207 assert(! dest->getType()->isSigned() && "Use CreateIntSetInstruction()");
210 if (C > (unsigned int) ~0)
211 { // C does not fit in 32 bits
212 assert(dest->getType() == Type::ULongTy && "Sign extension problems");
213 TmpInstruction *tmpReg = new TmpInstruction(Type::IntTy);
214 mcfi.addTemp(tmpReg);
215 CreateSETXConst(target, C, tmpReg, dest, mvec);
219 #undef SIGN_EXTEND_FOR_UNSIGNED_DEST
220 #ifdef SIGN_EXTEND_FOR_UNSIGNED_DEST
221 // If dest is smaller than the standard integer reg. size
222 // and the high-order bit of dest will be 1, then we have to
223 // extend the sign-bit into upper bits of the dest register.
225 unsigned destSize = target.DataLayout.getTypeSize(dest->getType());
226 if (destSize < target.DataLayout.getIntegerRegize())
228 assert(destSize <= 4 && "Unexpected type size of 5-7 bytes");
229 uint32_t signBit = C & (1 << (8*destSize-1));
231 { // Sign-bit is 1 so convert C to a sign-extended 64-bit value
232 // and use CreateSETSWConst. CreateSETSWConst will correctly
233 // generate efficient code for small signed values.
234 int32_t simmC = C | ~(signBit-1);
235 CreateSETSWConst(target, simmC, dest, mvec);
239 #endif /*SIGN_EXTEND_FOR_UNSIGNED_DEST*/
241 CreateSETUWConst(target, C, dest, mvec);
246 //************************* External Classes *******************************/
248 //---------------------------------------------------------------------------
249 // class UltraSparcInstrInfo
252 // Information about individual instructions.
253 // Most information is stored in the SparcMachineInstrDesc array above.
254 // Other information is computed on demand, and most such functions
255 // default to member functions in base class MachineInstrInfo.
256 //---------------------------------------------------------------------------
259 UltraSparcInstrInfo::UltraSparcInstrInfo(const TargetMachine& tgt)
260 : MachineInstrInfo(tgt, SparcMachineInstrDesc,
261 /*descSize = */ NUM_TOTAL_OPCODES,
262 /*numRealOpCodes = */ NUM_REAL_OPCODES)
267 // Create an instruction sequence to put the constant `val' into
268 // the virtual register `dest'. `val' may be a Constant or a
269 // GlobalValue, viz., the constant address of a global variable or function.
270 // The generated instructions are returned in `mvec'.
271 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
272 // Any stack space required is allocated via MachineCodeForMethod.
275 UltraSparcInstrInfo::CreateCodeToLoadConst(const TargetMachine& target,
279 std::vector<MachineInstr*>& mvec,
280 MachineCodeForInstruction& mcfi) const
282 assert(isa<Constant>(val) || isa<GlobalValue>(val) &&
283 "I only know about constant values and global addresses");
285 // Use a "set" instruction for known constants or symbolic constants (labels)
286 // that can go in an integer reg.
287 // We have to use a "load" instruction for all other constants,
288 // in particular, floating point constants.
290 const Type* valType = val->getType();
292 if (isa<GlobalValue>(val) || valType->isIntegral() || valType == Type::BoolTy)
294 if (isa<GlobalValue>(val))
296 TmpInstruction* tmpReg =
297 new TmpInstruction(PointerType::get(val->getType()), val);
298 mcfi.addTemp(tmpReg);
299 CreateSETXLabel(target, val, tmpReg, dest, mvec);
301 else if (! val->getType()->isSigned())
303 uint64_t C = cast<ConstantUInt>(val)->getValue();
304 CreateUIntSetInstruction(target, C, dest, mvec, mcfi);
308 bool isValidConstant;
309 int64_t C = GetConstantValueAsSignedInt(val, isValidConstant);
310 assert(isValidConstant && "Unrecognized constant");
311 CreateIntSetInstruction(target, C, dest, mvec, mcfi);
316 // Make an instruction sequence to load the constant, viz:
317 // SETX <addr-of-constant>, tmpReg, addrReg
318 // LOAD /*addr*/ addrReg, /*offset*/ 0, dest
320 // First, create a tmp register to be used by the SETX sequence.
321 TmpInstruction* tmpReg =
322 new TmpInstruction(PointerType::get(val->getType()), val);
323 mcfi.addTemp(tmpReg);
325 // Create another TmpInstruction for the address register
326 TmpInstruction* addrReg =
327 new TmpInstruction(PointerType::get(val->getType()), val);
328 mcfi.addTemp(addrReg);
330 // Put the address (a symbolic name) into a register
331 CreateSETXLabel(target, val, tmpReg, addrReg, mvec);
333 // Generate the load instruction
334 int64_t zeroOffset = 0; // to avoid ambiguity with (Value*) 0
336 Create3OperandInstr_SImmed(ChooseLoadInstruction(val->getType()),
337 addrReg, zeroOffset, dest);
340 // Make sure constant is emitted to constant pool in assembly code.
341 MachineCodeForMethod::get(F).addToConstantPool(cast<Constant>(val));
346 // Create an instruction sequence to copy an integer value `val'
347 // to a floating point value `dest' by copying to memory and back.
348 // val must be an integral type. dest must be a Float or Double.
349 // The generated instructions are returned in `mvec'.
350 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
351 // Any stack space required is allocated via MachineCodeForMethod.
354 UltraSparcInstrInfo::CreateCodeToCopyIntToFloat(const TargetMachine& target,
358 std::vector<MachineInstr*>& mvec,
359 MachineCodeForInstruction& mcfi) const
361 assert((val->getType()->isIntegral() || isa<PointerType>(val->getType()))
362 && "Source type must be integral");
363 assert(dest->getType()->isFloatingPoint()
364 && "Dest type must be float/double");
366 int offset = MachineCodeForMethod::get(F).allocateLocalVar(target, val);
368 // Store instruction stores `val' to [%fp+offset].
369 // The store and load opCodes are based on the value being copied, and
370 // they use integer and float types that accomodate the
371 // larger of the source type and the destination type:
372 // On SparcV9: int for float, long for double.
373 // Note that the store instruction is the same for signed and unsigned ints.
374 Type* tmpType = (dest->getType() == Type::FloatTy)? Type::IntTy
376 MachineInstr* store = new MachineInstr(ChooseStoreInstruction(tmpType));
377 store->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister, val);
378 store->SetMachineOperandReg(1, target.getRegInfo().getFramePointer());
379 store->SetMachineOperandConst(2,MachineOperand::MO_SignExtendedImmed,offset);
380 mvec.push_back(store);
382 // Load instruction loads [%fp+offset] to `dest'.
384 MachineInstr* load =new MachineInstr(ChooseLoadInstruction(dest->getType()));
385 load->SetMachineOperandReg(0, target.getRegInfo().getFramePointer());
386 load->SetMachineOperandConst(1, MachineOperand::MO_SignExtendedImmed,offset);
387 load->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister, dest);
388 mvec.push_back(load);
392 // Similarly, create an instruction sequence to copy an FP value
393 // `val' to an integer value `dest' by copying to memory and back.
394 // The generated instructions are returned in `mvec'.
395 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
396 // Any stack space required is allocated via MachineCodeForMethod.
399 UltraSparcInstrInfo::CreateCodeToCopyFloatToInt(const TargetMachine& target,
403 std::vector<MachineInstr*>& mvec,
404 MachineCodeForInstruction& mcfi) const
406 const Type* opTy = val->getType();
407 const Type* destTy = dest->getType();
409 assert(opTy->isFloatingPoint() && "Source type must be float/double");
410 assert((destTy->isIntegral() || isa<PointerType>(destTy))
411 && "Dest type must be integral");
413 int offset = MachineCodeForMethod::get(F).allocateLocalVar(target, val);
415 // Store instruction stores `val' to [%fp+offset].
416 // The store opCode is based only the source value being copied.
418 MachineInstr* store=new MachineInstr(ChooseStoreInstruction(val->getType()));
419 store->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister, val);
420 store->SetMachineOperandReg(1, target.getRegInfo().getFramePointer());
421 store->SetMachineOperandConst(2,MachineOperand::MO_SignExtendedImmed,offset);
422 mvec.push_back(store);
424 // Load instruction loads [%fp+offset] to `dest'.
425 // The type of the load opCode is the integer type that matches the
426 // source type in size: (and the dest type in sign):
427 // On SparcV9: int for float, long for double.
428 // Note that we *must* use signed loads even for unsigned dest types, to
429 // ensure that we get the right sign-extension for smaller-than-64-bit
430 // unsigned dest. types (i.e., UByte, UShort or UInt):
431 const Type* loadTy = opTy == Type::FloatTy? Type::IntTy : Type::LongTy;
432 MachineInstr* load = new MachineInstr(ChooseLoadInstruction(loadTy));
433 load->SetMachineOperandReg(0, target.getRegInfo().getFramePointer());
434 load->SetMachineOperandConst(1, MachineOperand::MO_SignExtendedImmed,offset);
435 load->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister, dest);
436 mvec.push_back(load);
440 // Create instruction(s) to copy src to dest, for arbitrary types
441 // The generated instructions are returned in `mvec'.
442 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
443 // Any stack space required is allocated via MachineCodeForMethod.
446 UltraSparcInstrInfo::CreateCopyInstructionsByType(const TargetMachine& target,
450 vector<MachineInstr*>& mvec,
451 MachineCodeForInstruction& mcfi) const
453 bool loadConstantToReg = false;
455 const Type* resultType = dest->getType();
457 MachineOpCode opCode = ChooseAddInstructionByType(resultType);
458 if (opCode == INVALID_OPCODE)
460 assert(0 && "Unsupported result type in CreateCopyInstructionsByType()");
464 // if `src' is a constant that doesn't fit in the immed field or if it is
465 // a global variable (i.e., a constant address), generate a load
466 // instruction instead of an add
468 if (isa<Constant>(src))
470 unsigned int machineRegNum;
472 MachineOperand::MachineOperandType opType =
473 ChooseRegOrImmed(src, opCode, target, /*canUseImmed*/ true,
474 machineRegNum, immedValue);
476 if (opType == MachineOperand::MO_VirtualRegister)
477 loadConstantToReg = true;
479 else if (isa<GlobalValue>(src))
480 loadConstantToReg = true;
482 if (loadConstantToReg)
483 { // `src' is constant and cannot fit in immed field for the ADD
484 // Insert instructions to "load" the constant into a register
485 target.getInstrInfo().CreateCodeToLoadConst(target, F, src, dest,
489 { // Create an add-with-0 instruction of the appropriate type.
490 // Make `src' the second operand, in case it is a constant
491 // Use (unsigned long) 0 for a NULL pointer value.
493 const Type* zeroValueType =
494 isa<PointerType>(resultType) ? Type::ULongTy : resultType;
495 MachineInstr* minstr =
496 Create3OperandInstr(opCode, Constant::getNullValue(zeroValueType),
498 mvec.push_back(minstr);
503 // Create instruction sequence to produce a sign-extended register value
504 // from an arbitrary sized value (sized in bits, not bytes).
505 // For SPARC v9, we sign-extend the given unsigned operand using SLL; SRA.
506 // The generated instructions are returned in `mvec'.
507 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
508 // Any stack space required is allocated via MachineCodeForMethod.
511 UltraSparcInstrInfo::CreateSignExtensionInstructions(
512 const TargetMachine& target,
514 Value* unsignedSrcVal,
515 unsigned int srcSizeInBits,
517 vector<MachineInstr*>& mvec,
518 MachineCodeForInstruction& mcfi) const
521 assert(srcSizeInBits < 64 && "Sign extension unnecessary!");
522 assert(srcSizeInBits > 0 && srcSizeInBits <= 32
523 && "Hmmm... 32 < srcSizeInBits < 64 unexpected but could be handled here.");
525 if (srcSizeInBits < 32)
526 { // SLL is needed since operand size is < 32 bits.
527 TmpInstruction *tmpI = new TmpInstruction(dest->getType(),
528 unsignedSrcVal, dest,"make32");
530 M = Create3OperandInstr_UImmed(SLL,unsignedSrcVal,32-srcSizeInBits,tmpI);
532 unsignedSrcVal = tmpI;
535 M = Create3OperandInstr_UImmed(SRA, unsignedSrcVal, 32-srcSizeInBits, dest);