1 //===-- SparcV9InstrInfo.h - Define TargetInstrInfo for SparcV9 -*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This class contains information about individual instructions.
11 // Also see the SparcV9MachineInstrDesc array, which can be found in
12 // SparcV9TargetMachine.cpp.
13 // Other information is computed on demand, and most such functions
14 // default to member functions in base class TargetInstrInfo.
16 //===----------------------------------------------------------------------===//
18 #ifndef SPARCV9INSTRINFO_H
19 #define SPARCV9INSTRINFO_H
21 #include "llvm/Target/TargetInstrInfo.h"
22 #include "llvm/CodeGen/MachineInstr.h"
23 #include "SparcV9Internals.h"
24 #include "SparcV9RegisterInfo.h"
28 /// SparcV9InstrInfo - TargetInstrInfo specialized for the SparcV9 target.
30 struct SparcV9InstrInfo : public TargetInstrInfo {
31 const SparcV9RegisterInfo RI;
34 : TargetInstrInfo(SparcV9MachineInstrDesc, V9::NUM_TOTAL_OPCODES) { }
36 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
37 /// such, whenever a client has an instance of instruction info, it should
38 /// always be able to get register info as well (through this method).
40 virtual const MRegisterInfo &getRegisterInfo() const { return RI; }
42 // All immediate constants are in position 1 except the
43 // store instructions and SETxx.
45 virtual int getImmedConstantPos(MachineOpCode opCode) const {
47 if (this->maxImmedConstant(opCode, ignore) != 0) {
49 assert(! this->isStore((MachineOpCode) V9::STBr - 1));
51 assert(! this->isStore((MachineOpCode) V9::STXFSRi + 1));
53 if (opCode == V9::SETSW || opCode == V9::SETUW ||
54 opCode == V9::SETX || opCode == V9::SETHI)
56 if (opCode >= V9::STBr && opCode <= V9::STXFSRi)
64 virtual bool hasResultInterlock(MachineOpCode opCode) const
66 // All UltraSPARC instructions have interlocks (note that delay slots
67 // are not considered here).
68 // However, instructions that use the result of an FCMP produce a
69 // 9-cycle stall if they are issued less than 3 cycles after the FCMP.
70 // Force the compiler to insert a software interlock (i.e., gap of
71 // 2 other groups, including NOPs if necessary).
72 return (opCode == V9::FCMPS || opCode == V9::FCMPD || opCode == V9::FCMPQ);
76 } // End llvm namespace