1 //===-- SparcV9InstrInfo.h - Define TargetInstrInfo for SparcV9 -*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This class contains information about individual instructions.
11 // Also see the SparcV9MachineInstrDesc array, which can be found in
12 // SparcV9TargetMachine.cpp.
13 // Other information is computed on demand, and most such functions
14 // default to member functions in base class TargetInstrInfo.
16 //===----------------------------------------------------------------------===//
18 #ifndef SPARCV9INSTRINFO_H
19 #define SPARCV9INSTRINFO_H
21 #include "llvm/Target/TargetInstrInfo.h"
22 #include "llvm/CodeGen/MachineInstr.h"
23 #include "SparcV9Internals.h"
24 #include "SparcV9RegisterInfo.h"
28 struct SparcV9InstrInfo : public TargetInstrInfo {
29 const SparcV9RegisterInfo RI;
33 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
34 /// such, whenever a client has an instance of instruction info, it should
35 /// always be able to get register info as well (through this method).
37 virtual const MRegisterInfo &getRegisterInfo() const { return RI; }
39 // All immediate constants are in position 1 except the
40 // store instructions and SETxx.
42 virtual int getImmedConstantPos(MachineOpCode opCode) const {
44 if (this->maxImmedConstant(opCode, ignore) != 0) {
46 assert(! this->isStore((MachineOpCode) V9::STBr - 1));
48 assert(! this->isStore((MachineOpCode) V9::STXFSRi + 1));
50 if (opCode == V9::SETSW || opCode == V9::SETUW ||
51 opCode == V9::SETX || opCode == V9::SETHI)
53 if (opCode >= V9::STBr && opCode <= V9::STXFSRi)
61 virtual bool hasResultInterlock(MachineOpCode opCode) const
63 // All UltraSPARC instructions have interlocks (note that delay slots
64 // are not considered here).
65 // However, instructions that use the result of an FCMP produce a
66 // 9-cycle stall if they are issued less than 3 cycles after the FCMP.
67 // Force the compiler to insert a software interlock (i.e., gap of
68 // 2 other groups, including NOPs if necessary).
69 return (opCode == V9::FCMPS || opCode == V9::FCMPD || opCode == V9::FCMPQ);
72 //-------------------------------------------------------------------------
73 // Queries about representation of LLVM quantities (e.g., constants)
74 //-------------------------------------------------------------------------
76 virtual bool ConstantMayNotFitInImmedField(const Constant* CV,
77 const Instruction* I) const;
79 //-------------------------------------------------------------------------
80 // Code generation support for creating individual machine instructions
81 //-------------------------------------------------------------------------
83 // Get certain common op codes for the current target. This and all the
84 // Create* methods below should be moved to a machine code generation class
86 virtual MachineOpCode getNOPOpCode() const { return V9::NOP; }
88 // Get the value of an integral constant in the form that must
89 // be put into the machine register. The specified constant is interpreted
90 // as (i.e., converted if necessary to) the specified destination type. The
91 // result is always returned as an uint64_t, since the representation of
92 // int64_t and uint64_t are identical. The argument can be any known const.
94 // isValidConstant is set to true if a valid constant was found.
96 virtual uint64_t ConvertConstantToIntType(const TargetMachine &target,
99 bool &isValidConstant) const;
101 // Create an instruction sequence to put the constant `val' into
102 // the virtual register `dest'. `val' may be a Constant or a
103 // GlobalValue, viz., the constant address of a global variable or function.
104 // The generated instructions are returned in `mvec'.
105 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
107 virtual void CreateCodeToLoadConst(const TargetMachine& target,
111 std::vector<MachineInstr*>& mvec,
112 MachineCodeForInstruction& mcfi) const;
114 // Create an instruction sequence to copy an integer value `val'
115 // to a floating point value `dest' by copying to memory and back.
116 // val must be an integral type. dest must be a Float or Double.
117 // The generated instructions are returned in `mvec'.
118 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
120 virtual void CreateCodeToCopyIntToFloat(const TargetMachine& target,
124 std::vector<MachineInstr*>& mvec,
125 MachineCodeForInstruction& mcfi) const;
127 // Similarly, create an instruction sequence to copy an FP value
128 // `val' to an integer value `dest' by copying to memory and back.
129 // The generated instructions are returned in `mvec'.
130 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
132 virtual void CreateCodeToCopyFloatToInt(const TargetMachine& target,
136 std::vector<MachineInstr*>& mvec,
137 MachineCodeForInstruction& mcfi) const;
139 // Create instruction(s) to copy src to dest, for arbitrary types
140 // The generated instructions are returned in `mvec'.
141 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
143 virtual void CreateCopyInstructionsByType(const TargetMachine& target,
147 std::vector<MachineInstr*>& mvec,
148 MachineCodeForInstruction& mcfi) const;
150 // Create instruction sequence to produce a sign-extended register value
151 // from an arbitrary sized value (sized in bits, not bytes).
152 // The generated instructions are appended to `mvec'.
153 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
155 virtual void CreateSignExtensionInstructions(const TargetMachine& target,
159 unsigned int numLowBits,
160 std::vector<MachineInstr*>& mvec,
161 MachineCodeForInstruction& mcfi) const;
163 // Create instruction sequence to produce a zero-extended register value
164 // from an arbitrary sized value (sized in bits, not bytes).
165 // The generated instructions are appended to `mvec'.
166 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
168 virtual void CreateZeroExtensionInstructions(const TargetMachine& target,
172 unsigned int numLowBits,
173 std::vector<MachineInstr*>& mvec,
174 MachineCodeForInstruction& mcfi) const;
177 } // End llvm namespace