1 //===-- SparcInstrSelection.cpp -------------------------------------------===//
3 // BURS instruction selection for SPARC V9 architecture.
5 //===----------------------------------------------------------------------===//
7 #include "SparcInternals.h"
8 #include "SparcInstrSelectionSupport.h"
9 #include "SparcRegClassInfo.h"
10 #include "llvm/CodeGen/InstrSelectionSupport.h"
11 #include "llvm/CodeGen/MachineInstr.h"
12 #include "llvm/CodeGen/MachineInstrAnnot.h"
13 #include "llvm/CodeGen/InstrForest.h"
14 #include "llvm/CodeGen/InstrSelection.h"
15 #include "llvm/CodeGen/MachineFunction.h"
16 #include "llvm/CodeGen/MachineCodeForInstruction.h"
17 #include "llvm/DerivedTypes.h"
18 #include "llvm/iTerminators.h"
19 #include "llvm/iMemory.h"
20 #include "llvm/iOther.h"
21 #include "llvm/Function.h"
22 #include "llvm/Constants.h"
23 #include "llvm/ConstantHandling.h"
24 #include "Support/MathExtras.h"
28 //************************ Internal Functions ******************************/
31 static inline MachineOpCode
32 ChooseBprInstruction(const InstructionNode* instrNode)
36 Instruction* setCCInstr =
37 ((InstructionNode*) instrNode->leftChild())->getInstruction();
39 switch(setCCInstr->getOpcode())
41 case Instruction::SetEQ: opCode = BRZ; break;
42 case Instruction::SetNE: opCode = BRNZ; break;
43 case Instruction::SetLE: opCode = BRLEZ; break;
44 case Instruction::SetGE: opCode = BRGEZ; break;
45 case Instruction::SetLT: opCode = BRLZ; break;
46 case Instruction::SetGT: opCode = BRGZ; break;
48 assert(0 && "Unrecognized VM instruction!");
49 opCode = INVALID_OPCODE;
57 static inline MachineOpCode
58 ChooseBpccInstruction(const InstructionNode* instrNode,
59 const BinaryOperator* setCCInstr)
61 MachineOpCode opCode = INVALID_OPCODE;
63 bool isSigned = setCCInstr->getOperand(0)->getType()->isSigned();
67 switch(setCCInstr->getOpcode())
69 case Instruction::SetEQ: opCode = BE; break;
70 case Instruction::SetNE: opCode = BNE; break;
71 case Instruction::SetLE: opCode = BLE; break;
72 case Instruction::SetGE: opCode = BGE; break;
73 case Instruction::SetLT: opCode = BL; break;
74 case Instruction::SetGT: opCode = BG; break;
76 assert(0 && "Unrecognized VM instruction!");
82 switch(setCCInstr->getOpcode())
84 case Instruction::SetEQ: opCode = BE; break;
85 case Instruction::SetNE: opCode = BNE; break;
86 case Instruction::SetLE: opCode = BLEU; break;
87 case Instruction::SetGE: opCode = BCC; break;
88 case Instruction::SetLT: opCode = BCS; break;
89 case Instruction::SetGT: opCode = BGU; break;
91 assert(0 && "Unrecognized VM instruction!");
99 static inline MachineOpCode
100 ChooseBFpccInstruction(const InstructionNode* instrNode,
101 const BinaryOperator* setCCInstr)
103 MachineOpCode opCode = INVALID_OPCODE;
105 switch(setCCInstr->getOpcode())
107 case Instruction::SetEQ: opCode = FBE; break;
108 case Instruction::SetNE: opCode = FBNE; break;
109 case Instruction::SetLE: opCode = FBLE; break;
110 case Instruction::SetGE: opCode = FBGE; break;
111 case Instruction::SetLT: opCode = FBL; break;
112 case Instruction::SetGT: opCode = FBG; break;
114 assert(0 && "Unrecognized VM instruction!");
122 // Create a unique TmpInstruction for a boolean value,
123 // representing the CC register used by a branch on that value.
124 // For now, hack this using a little static cache of TmpInstructions.
125 // Eventually the entire BURG instruction selection should be put
126 // into a separate class that can hold such information.
127 // The static cache is not too bad because the memory for these
128 // TmpInstructions will be freed along with the rest of the Function anyway.
130 static TmpInstruction*
131 GetTmpForCC(Value* boolVal, const Function *F, const Type* ccType)
133 typedef hash_map<const Value*, TmpInstruction*> BoolTmpCache;
134 static BoolTmpCache boolToTmpCache; // Map boolVal -> TmpInstruction*
135 static const Function *lastFunction = 0;// Use to flush cache between funcs
137 assert(boolVal->getType() == Type::BoolTy && "Weird but ok! Delete assert");
139 if (lastFunction != F)
142 boolToTmpCache.clear();
145 // Look for tmpI and create a new one otherwise. The new value is
146 // directly written to map using the ref returned by operator[].
147 TmpInstruction*& tmpI = boolToTmpCache[boolVal];
149 tmpI = new TmpInstruction(ccType, boolVal);
155 static inline MachineOpCode
156 ChooseBccInstruction(const InstructionNode* instrNode,
159 InstructionNode* setCCNode = (InstructionNode*) instrNode->leftChild();
160 assert(setCCNode->getOpLabel() == SetCCOp);
161 BinaryOperator* setCCInstr =cast<BinaryOperator>(setCCNode->getInstruction());
162 const Type* setCCType = setCCInstr->getOperand(0)->getType();
164 isFPBranch = setCCType->isFloatingPoint(); // Return value: don't delete!
167 return ChooseBFpccInstruction(instrNode, setCCInstr);
169 return ChooseBpccInstruction(instrNode, setCCInstr);
173 static inline MachineOpCode
174 ChooseMovFpccInstruction(const InstructionNode* instrNode)
176 MachineOpCode opCode = INVALID_OPCODE;
178 switch(instrNode->getInstruction()->getOpcode())
180 case Instruction::SetEQ: opCode = MOVFE; break;
181 case Instruction::SetNE: opCode = MOVFNE; break;
182 case Instruction::SetLE: opCode = MOVFLE; break;
183 case Instruction::SetGE: opCode = MOVFGE; break;
184 case Instruction::SetLT: opCode = MOVFL; break;
185 case Instruction::SetGT: opCode = MOVFG; break;
187 assert(0 && "Unrecognized VM instruction!");
195 // Assumes that SUBcc v1, v2 -> v3 has been executed.
196 // In most cases, we want to clear v3 and then follow it by instruction
198 // Set mustClearReg=false if v3 need not be cleared before conditional move.
199 // Set valueToMove=0 if we want to conditionally move 0 instead of 1
200 // (i.e., we want to test inverse of a condition)
201 // (The latter two cases do not seem to arise because SetNE needs nothing.)
204 ChooseMovpccAfterSub(const InstructionNode* instrNode,
208 MachineOpCode opCode = INVALID_OPCODE;
212 switch(instrNode->getInstruction()->getOpcode())
214 case Instruction::SetEQ: opCode = MOVE; break;
215 case Instruction::SetLE: opCode = MOVLE; break;
216 case Instruction::SetGE: opCode = MOVGE; break;
217 case Instruction::SetLT: opCode = MOVL; break;
218 case Instruction::SetGT: opCode = MOVG; break;
219 case Instruction::SetNE: assert(0 && "No move required!"); break;
220 default: assert(0 && "Unrecognized VM instr!"); break;
226 static inline MachineOpCode
227 ChooseConvertToFloatInstr(OpLabel vopCode, const Type* opType)
229 MachineOpCode opCode = INVALID_OPCODE;
234 if (opType == Type::SByteTy || opType == Type::ShortTy || opType == Type::IntTy)
236 else if (opType == Type::LongTy)
238 else if (opType == Type::DoubleTy)
240 else if (opType == Type::FloatTy)
243 assert(0 && "Cannot convert this type to FLOAT on SPARC");
247 // This is usually used in conjunction with CreateCodeToCopyIntToFloat().
248 // Both functions should treat the integer as a 32-bit value for types
249 // of 4 bytes or less, and as a 64-bit value otherwise.
250 if (opType == Type::SByteTy || opType == Type::UByteTy ||
251 opType == Type::ShortTy || opType == Type::UShortTy ||
252 opType == Type::IntTy || opType == Type::UIntTy)
254 else if (opType == Type::LongTy || opType == Type::ULongTy)
256 else if (opType == Type::FloatTy)
258 else if (opType == Type::DoubleTy)
261 assert(0 && "Cannot convert this type to DOUBLE on SPARC");
271 static inline MachineOpCode
272 ChooseConvertFPToIntInstr(Type::PrimitiveID tid, const Type* opType)
274 MachineOpCode opCode = INVALID_OPCODE;;
276 assert((opType == Type::FloatTy || opType == Type::DoubleTy)
277 && "This function should only be called for FLOAT or DOUBLE");
279 if (tid==Type::UIntTyID)
281 assert(tid != Type::UIntTyID && "FP-to-uint conversions must be expanded"
282 " into FP->long->uint for SPARC v9: SO RUN PRESELECTION PASS!");
284 else if (tid==Type::SByteTyID || tid==Type::ShortTyID || tid==Type::IntTyID ||
285 tid==Type::UByteTyID || tid==Type::UShortTyID)
287 opCode = (opType == Type::FloatTy)? FSTOI : FDTOI;
289 else if (tid==Type::LongTyID || tid==Type::ULongTyID)
291 opCode = (opType == Type::FloatTy)? FSTOX : FDTOX;
294 assert(0 && "Should not get here, Mo!");
300 CreateConvertFPToIntInstr(Type::PrimitiveID destTID,
301 Value* srcVal, Value* destVal)
303 MachineOpCode opCode = ChooseConvertFPToIntInstr(destTID, srcVal->getType());
304 assert(opCode != INVALID_OPCODE && "Expected to need conversion!");
306 MachineInstr* M = new MachineInstr(opCode);
307 M->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister, srcVal);
308 M->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister, destVal);
312 // CreateCodeToConvertFloatToInt: Convert FP value to signed or unsigned integer
313 // The FP value must be converted to the dest type in an FP register,
314 // and the result is then copied from FP to int register via memory.
316 // Since fdtoi converts to signed integers, any FP value V between MAXINT+1
317 // and MAXUNSIGNED (i.e., 2^31 <= V <= 2^32-1) would be converted incorrectly
318 // *only* when converting to an unsigned int. (Unsigned byte, short or long
319 // don't have this problem.)
320 // For unsigned int, we therefore have to generate the code sequence:
322 // if (V > (float) MAXINT) {
323 // unsigned result = (unsigned) (V - (float) MAXINT);
324 // result = result + (unsigned) MAXINT;
327 // result = (unsigned int) V;
330 CreateCodeToConvertFloatToInt(const TargetMachine& target,
333 std::vector<MachineInstr*>& mvec,
334 MachineCodeForInstruction& mcfi)
336 // Create a temporary to represent the FP register into which the
337 // int value will placed after conversion. The type of this temporary
338 // depends on the type of FP register to use: single-prec for a 32-bit
339 // int or smaller; double-prec for a 64-bit int.
341 size_t destSize = target.DataLayout.getTypeSize(destI->getType());
342 const Type* destTypeToUse = (destSize > 4)? Type::DoubleTy : Type::FloatTy;
343 TmpInstruction* destForCast = new TmpInstruction(destTypeToUse, opVal);
344 mcfi.addTemp(destForCast);
346 // Create the fp-to-int conversion code
347 MachineInstr* M =CreateConvertFPToIntInstr(destI->getType()->getPrimitiveID(),
351 // Create the fpreg-to-intreg copy code
352 target.getInstrInfo().
353 CreateCodeToCopyFloatToInt(target, destI->getParent()->getParent(),
354 destForCast, destI, mvec, mcfi);
358 static inline MachineOpCode
359 ChooseAddInstruction(const InstructionNode* instrNode)
361 return ChooseAddInstructionByType(instrNode->getInstruction()->getType());
365 static inline MachineInstr*
366 CreateMovFloatInstruction(const InstructionNode* instrNode,
367 const Type* resultType)
369 MachineInstr* minstr = new MachineInstr((resultType == Type::FloatTy)
371 minstr->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister,
372 instrNode->leftChild()->getValue());
373 minstr->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister,
374 instrNode->getValue());
378 static inline MachineInstr*
379 CreateAddConstInstruction(const InstructionNode* instrNode)
381 MachineInstr* minstr = NULL;
383 Value* constOp = ((InstrTreeNode*) instrNode->rightChild())->getValue();
384 assert(isa<Constant>(constOp));
386 // Cases worth optimizing are:
387 // (1) Add with 0 for float or double: use an FMOV of appropriate type,
388 // instead of an FADD (1 vs 3 cycles). There is no integer MOV.
390 if (ConstantFP *FPC = dyn_cast<ConstantFP>(constOp)) {
391 double dval = FPC->getValue();
393 minstr = CreateMovFloatInstruction(instrNode,
394 instrNode->getInstruction()->getType());
401 static inline MachineOpCode
402 ChooseSubInstructionByType(const Type* resultType)
404 MachineOpCode opCode = INVALID_OPCODE;
406 if (resultType->isInteger() || isa<PointerType>(resultType))
411 switch(resultType->getPrimitiveID())
413 case Type::FloatTyID: opCode = FSUBS; break;
414 case Type::DoubleTyID: opCode = FSUBD; break;
415 default: assert(0 && "Invalid type for SUB instruction"); break;
422 static inline MachineInstr*
423 CreateSubConstInstruction(const InstructionNode* instrNode)
425 MachineInstr* minstr = NULL;
427 Value* constOp = ((InstrTreeNode*) instrNode->rightChild())->getValue();
428 assert(isa<Constant>(constOp));
430 // Cases worth optimizing are:
431 // (1) Sub with 0 for float or double: use an FMOV of appropriate type,
432 // instead of an FSUB (1 vs 3 cycles). There is no integer MOV.
434 if (ConstantFP *FPC = dyn_cast<ConstantFP>(constOp)) {
435 double dval = FPC->getValue();
437 minstr = CreateMovFloatInstruction(instrNode,
438 instrNode->getInstruction()->getType());
445 static inline MachineOpCode
446 ChooseFcmpInstruction(const InstructionNode* instrNode)
448 MachineOpCode opCode = INVALID_OPCODE;
450 Value* operand = ((InstrTreeNode*) instrNode->leftChild())->getValue();
451 switch(operand->getType()->getPrimitiveID()) {
452 case Type::FloatTyID: opCode = FCMPS; break;
453 case Type::DoubleTyID: opCode = FCMPD; break;
454 default: assert(0 && "Invalid type for FCMP instruction"); break;
461 // Assumes that leftArg and rightArg are both cast instructions.
464 BothFloatToDouble(const InstructionNode* instrNode)
466 InstrTreeNode* leftArg = instrNode->leftChild();
467 InstrTreeNode* rightArg = instrNode->rightChild();
468 InstrTreeNode* leftArgArg = leftArg->leftChild();
469 InstrTreeNode* rightArgArg = rightArg->leftChild();
470 assert(leftArg->getValue()->getType() == rightArg->getValue()->getType());
472 // Check if both arguments are floats cast to double
473 return (leftArg->getValue()->getType() == Type::DoubleTy &&
474 leftArgArg->getValue()->getType() == Type::FloatTy &&
475 rightArgArg->getValue()->getType() == Type::FloatTy);
479 static inline MachineOpCode
480 ChooseMulInstructionByType(const Type* resultType)
482 MachineOpCode opCode = INVALID_OPCODE;
484 if (resultType->isInteger())
487 switch(resultType->getPrimitiveID())
489 case Type::FloatTyID: opCode = FMULS; break;
490 case Type::DoubleTyID: opCode = FMULD; break;
491 default: assert(0 && "Invalid type for MUL instruction"); break;
499 static inline MachineInstr*
500 CreateIntNegInstruction(const TargetMachine& target,
503 MachineInstr* minstr = new MachineInstr(SUB);
504 minstr->SetMachineOperandReg(0, target.getRegInfo().getZeroRegNum());
505 minstr->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister, vreg);
506 minstr->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister, vreg);
511 // Create instruction sequence for any shift operation.
512 // SLL or SLLX on an operand smaller than the integer reg. size (64bits)
513 // requires a second instruction for explicit sign-extension.
514 // Note that we only have to worry about a sign-bit appearing in the
515 // most significant bit of the operand after shifting (e.g., bit 32 of
516 // Int or bit 16 of Short), so we do not have to worry about results
517 // that are as large as a normal integer register.
520 CreateShiftInstructions(const TargetMachine& target,
522 MachineOpCode shiftOpCode,
524 Value* optArgVal2, /* Use optArgVal2 if not NULL */
525 unsigned int optShiftNum, /* else use optShiftNum */
526 Instruction* destVal,
527 vector<MachineInstr*>& mvec,
528 MachineCodeForInstruction& mcfi)
530 assert((optArgVal2 != NULL || optShiftNum <= 64) &&
531 "Large shift sizes unexpected, but can be handled below: "
532 "You need to check whether or not it fits in immed field below");
534 // If this is a logical left shift of a type smaller than the standard
535 // integer reg. size, we have to extend the sign-bit into upper bits
536 // of dest, so we need to put the result of the SLL into a temporary.
538 Value* shiftDest = destVal;
539 unsigned opSize = target.DataLayout.getTypeSize(argVal1->getType());
540 if ((shiftOpCode == SLL || shiftOpCode == SLLX)
541 && opSize < target.DataLayout.getIntegerRegize())
542 { // put SLL result into a temporary
543 shiftDest = new TmpInstruction(argVal1, optArgVal2, "sllTmp");
544 mcfi.addTemp(shiftDest);
547 MachineInstr* M = (optArgVal2 != NULL)
548 ? Create3OperandInstr(shiftOpCode, argVal1, optArgVal2, shiftDest)
549 : Create3OperandInstr_UImmed(shiftOpCode, argVal1, optShiftNum, shiftDest);
552 if (shiftDest != destVal)
553 { // extend the sign-bit of the result into all upper bits of dest
554 assert(8*opSize <= 32 && "Unexpected type size > 4 and < IntRegSize?");
555 target.getInstrInfo().
556 CreateSignExtensionInstructions(target, F, shiftDest, destVal,
557 8*opSize, mvec, mcfi);
562 // Does not create any instructions if we cannot exploit constant to
563 // create a cheaper instruction.
564 // This returns the approximate cost of the instructions generated,
565 // which is used to pick the cheapest when both operands are constant.
566 static inline unsigned int
567 CreateMulConstInstruction(const TargetMachine &target, Function* F,
568 Value* lval, Value* rval, Instruction* destVal,
569 vector<MachineInstr*>& mvec,
570 MachineCodeForInstruction& mcfi)
572 /* Use max. multiply cost, viz., cost of MULX */
573 unsigned int cost = target.getInstrInfo().minLatency(MULX);
574 unsigned int firstNewInstr = mvec.size();
576 Value* constOp = rval;
577 if (! isa<Constant>(constOp))
580 // Cases worth optimizing are:
581 // (1) Multiply by 0 or 1 for any type: replace with copy (ADD or FMOV)
582 // (2) Multiply by 2^x for integer types: replace with Shift
584 const Type* resultType = destVal->getType();
586 if (resultType->isInteger() || isa<PointerType>(resultType))
589 int64_t C = GetConstantValueAsSignedInt(constOp, isValidConst);
593 bool needNeg = false;
600 if (C == 0 || C == 1)
602 cost = target.getInstrInfo().minLatency(ADD);
603 MachineInstr* M = (C == 0)
604 ? Create3OperandInstr_Reg(ADD,
605 target.getRegInfo().getZeroRegNum(),
606 target.getRegInfo().getZeroRegNum(),
608 : Create3OperandInstr_Reg(ADD, lval,
609 target.getRegInfo().getZeroRegNum(),
613 else if (isPowerOf2(C, pow))
615 unsigned int opSize = target.DataLayout.getTypeSize(resultType);
616 MachineOpCode opCode = (opSize <= 32)? SLL : SLLX;
617 CreateShiftInstructions(target, F, opCode, lval, NULL, pow,
618 destVal, mvec, mcfi);
621 if (mvec.size() > 0 && needNeg)
622 { // insert <reg = SUB 0, reg> after the instr to flip the sign
623 MachineInstr* M = CreateIntNegInstruction(target, destVal);
630 if (ConstantFP *FPC = dyn_cast<ConstantFP>(constOp))
632 double dval = FPC->getValue();
635 MachineOpCode opCode = (dval < 0)
636 ? (resultType == Type::FloatTy? FNEGS : FNEGD)
637 : (resultType == Type::FloatTy? FMOVS : FMOVD);
638 MachineInstr* M = Create2OperandInstr(opCode, lval, destVal);
644 if (firstNewInstr < mvec.size())
647 for (unsigned int i=firstNewInstr; i < mvec.size(); ++i)
648 cost += target.getInstrInfo().minLatency(mvec[i]->getOpCode());
655 // Does not create any instructions if we cannot exploit constant to
656 // create a cheaper instruction.
659 CreateCheapestMulConstInstruction(const TargetMachine &target,
661 Value* lval, Value* rval,
662 Instruction* destVal,
663 vector<MachineInstr*>& mvec,
664 MachineCodeForInstruction& mcfi)
667 if (isa<Constant>(lval) && isa<Constant>(rval))
668 { // both operands are constant: evaluate and "set" in dest
669 Constant* P = ConstantFoldBinaryInstruction(Instruction::Mul,
670 cast<Constant>(lval), cast<Constant>(rval));
671 target.getInstrInfo().CreateCodeToLoadConst(target,F,P,destVal,mvec,mcfi);
673 else if (isa<Constant>(rval)) // rval is constant, but not lval
674 CreateMulConstInstruction(target, F, lval, rval, destVal, mvec, mcfi);
675 else if (isa<Constant>(lval)) // lval is constant, but not rval
676 CreateMulConstInstruction(target, F, lval, rval, destVal, mvec, mcfi);
678 // else neither is constant
682 // Return NULL if we cannot exploit constant to create a cheaper instruction
684 CreateMulInstruction(const TargetMachine &target, Function* F,
685 Value* lval, Value* rval, Instruction* destVal,
686 vector<MachineInstr*>& mvec,
687 MachineCodeForInstruction& mcfi,
688 MachineOpCode forceMulOp = INVALID_MACHINE_OPCODE)
690 unsigned int L = mvec.size();
691 CreateCheapestMulConstInstruction(target,F, lval, rval, destVal, mvec, mcfi);
692 if (mvec.size() == L)
693 { // no instructions were added so create MUL reg, reg, reg.
694 // Use FSMULD if both operands are actually floats cast to doubles.
695 // Otherwise, use the default opcode for the appropriate type.
696 MachineOpCode mulOp = ((forceMulOp != INVALID_MACHINE_OPCODE)
698 : ChooseMulInstructionByType(destVal->getType()));
699 MachineInstr* M = new MachineInstr(mulOp);
700 M->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister, lval);
701 M->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister, rval);
702 M->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister, destVal);
708 // Generate a divide instruction for Div or Rem.
709 // For Rem, this assumes that the operand type will be signed if the result
710 // type is signed. This is correct because they must have the same sign.
712 static inline MachineOpCode
713 ChooseDivInstruction(TargetMachine &target,
714 const InstructionNode* instrNode)
716 MachineOpCode opCode = INVALID_OPCODE;
718 const Type* resultType = instrNode->getInstruction()->getType();
720 if (resultType->isInteger())
721 opCode = resultType->isSigned()? SDIVX : UDIVX;
723 switch(resultType->getPrimitiveID())
725 case Type::FloatTyID: opCode = FDIVS; break;
726 case Type::DoubleTyID: opCode = FDIVD; break;
727 default: assert(0 && "Invalid type for DIV instruction"); break;
734 // Return NULL if we cannot exploit constant to create a cheaper instruction
736 CreateDivConstInstruction(TargetMachine &target,
737 const InstructionNode* instrNode,
738 vector<MachineInstr*>& mvec)
740 MachineInstr* minstr1 = NULL;
741 MachineInstr* minstr2 = NULL;
743 Value* constOp = ((InstrTreeNode*) instrNode->rightChild())->getValue();
744 if (! isa<Constant>(constOp))
747 // Cases worth optimizing are:
748 // (1) Divide by 1 for any type: replace with copy (ADD or FMOV)
749 // (2) Divide by 2^x for integer types: replace with SR[L or A]{X}
751 const Type* resultType = instrNode->getInstruction()->getType();
753 if (resultType->isInteger())
757 int64_t C = GetConstantValueAsSignedInt(constOp, isValidConst);
760 bool needNeg = false;
769 minstr1 = new MachineInstr(ADD);
770 minstr1->SetMachineOperandVal(0,
771 MachineOperand::MO_VirtualRegister,
772 instrNode->leftChild()->getValue());
773 minstr1->SetMachineOperandReg(1,
774 target.getRegInfo().getZeroRegNum());
776 else if (isPowerOf2(C, pow))
778 MachineOpCode opCode= ((resultType->isSigned())
779 ? (resultType==Type::LongTy)? SRAX : SRA
780 : (resultType==Type::LongTy)? SRLX : SRL);
781 minstr1 = new MachineInstr(opCode);
782 minstr1->SetMachineOperandVal(0,
783 MachineOperand::MO_VirtualRegister,
784 instrNode->leftChild()->getValue());
785 minstr1->SetMachineOperandConst(1,
786 MachineOperand::MO_UnextendedImmed,
790 if (minstr1 && needNeg)
791 { // insert <reg = SUB 0, reg> after the instr to flip the sign
792 minstr2 = CreateIntNegInstruction(target,
793 instrNode->getValue());
799 if (ConstantFP *FPC = dyn_cast<ConstantFP>(constOp))
801 double dval = FPC->getValue();
804 bool needNeg = (dval < 0);
806 MachineOpCode opCode = needNeg
807 ? (resultType == Type::FloatTy? FNEGS : FNEGD)
808 : (resultType == Type::FloatTy? FMOVS : FMOVD);
810 minstr1 = new MachineInstr(opCode);
811 minstr1->SetMachineOperandVal(0,
812 MachineOperand::MO_VirtualRegister,
813 instrNode->leftChild()->getValue());
819 minstr1->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister,
820 instrNode->getValue());
823 mvec.push_back(minstr1);
825 mvec.push_back(minstr2);
830 CreateCodeForVariableSizeAlloca(const TargetMachine& target,
833 Value* numElementsVal,
834 vector<MachineInstr*>& getMvec)
838 MachineCodeForInstruction& mcfi = MachineCodeForInstruction::get(result);
839 Function *F = result->getParent()->getParent();
841 // Enforce the alignment constraints on the stack pointer at
842 // compile time if the total size is a known constant.
843 if (isa<Constant>(numElementsVal))
846 int64_t numElem = GetConstantValueAsSignedInt(numElementsVal, isValid);
847 assert(isValid && "Unexpectedly large array dimension in alloca!");
848 int64_t total = numElem * tsize;
849 if (int extra= total % target.getFrameInfo().getStackFrameSizeAlignment())
850 total += target.getFrameInfo().getStackFrameSizeAlignment() - extra;
851 totalSizeVal = ConstantSInt::get(Type::IntTy, total);
855 // The size is not a constant. Generate code to compute it and
856 // code to pad the size for stack alignment.
857 // Create a Value to hold the (constant) element size
858 Value* tsizeVal = ConstantSInt::get(Type::IntTy, tsize);
860 // Create temporary values to hold the result of MUL, SLL, SRL
861 // THIS CASE IS INCOMPLETE AND WILL BE FIXED SHORTLY.
862 TmpInstruction* tmpProd = new TmpInstruction(numElementsVal, tsizeVal);
863 TmpInstruction* tmpSLL = new TmpInstruction(numElementsVal, tmpProd);
864 TmpInstruction* tmpSRL = new TmpInstruction(numElementsVal, tmpSLL);
865 mcfi.addTemp(tmpProd);
866 mcfi.addTemp(tmpSLL);
867 mcfi.addTemp(tmpSRL);
869 // Instruction 1: mul numElements, typeSize -> tmpProd
870 // This will optimize the MUL as far as possible.
871 CreateMulInstruction(target, F, numElementsVal, tsizeVal, tmpProd,getMvec,
872 mcfi, INVALID_MACHINE_OPCODE);
874 assert(0 && "Need to insert padding instructions here!");
876 totalSizeVal = tmpProd;
879 // Get the constant offset from SP for dynamically allocated storage
880 // and create a temporary Value to hold it.
881 MachineFunction& mcInfo = MachineFunction::get(F);
883 ConstantSInt* dynamicAreaOffset =
884 ConstantSInt::get(Type::IntTy,
885 target.getFrameInfo().getDynamicAreaOffset(mcInfo,growUp));
886 assert(! growUp && "Has SPARC v9 stack frame convention changed?");
888 // Instruction 2: sub %sp, totalSizeVal -> %sp
889 M = new MachineInstr(SUB);
890 M->SetMachineOperandReg(0, target.getRegInfo().getStackPointer());
891 M->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister, totalSizeVal);
892 M->SetMachineOperandReg(2, target.getRegInfo().getStackPointer());
893 getMvec.push_back(M);
895 // Instruction 3: add %sp, frameSizeBelowDynamicArea -> result
896 M = new MachineInstr(ADD);
897 M->SetMachineOperandReg(0, target.getRegInfo().getStackPointer());
898 M->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister, dynamicAreaOffset);
899 M->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister, result);
900 getMvec.push_back(M);
905 CreateCodeForFixedSizeAlloca(const TargetMachine& target,
908 unsigned int numElements,
909 vector<MachineInstr*>& getMvec)
911 assert(tsize > 0 && "Illegal (zero) type size for alloca");
912 assert(result && result->getParent() &&
913 "Result value is not part of a function?");
914 Function *F = result->getParent()->getParent();
915 MachineFunction &mcInfo = MachineFunction::get(F);
917 // Check if the offset would small enough to use as an immediate in
918 // load/stores (check LDX because all load/stores have the same-size immediate
919 // field). If not, put the variable in the dynamically sized area of the
921 unsigned int paddedSizeIgnored;
922 int offsetFromFP = mcInfo.computeOffsetforLocalVar(target, result,
924 tsize * numElements);
925 if (! target.getInstrInfo().constantFitsInImmedField(LDX, offsetFromFP))
927 CreateCodeForVariableSizeAlloca(target, result, tsize,
928 ConstantSInt::get(Type::IntTy,numElements),
933 // else offset fits in immediate field so go ahead and allocate it.
934 offsetFromFP = mcInfo.allocateLocalVar(target, result, tsize * numElements);
936 // Create a temporary Value to hold the constant offset.
937 // This is needed because it may not fit in the immediate field.
938 ConstantSInt* offsetVal = ConstantSInt::get(Type::IntTy, offsetFromFP);
940 // Instruction 1: add %fp, offsetFromFP -> result
941 MachineInstr* M = new MachineInstr(ADD);
942 M->SetMachineOperandReg(0, target.getRegInfo().getFramePointer());
943 M->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister, offsetVal);
944 M->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister, result);
946 getMvec.push_back(M);
950 //------------------------------------------------------------------------
951 // Function SetOperandsForMemInstr
953 // Choose addressing mode for the given load or store instruction.
954 // Use [reg+reg] if it is an indexed reference, and the index offset is
955 // not a constant or if it cannot fit in the offset field.
956 // Use [reg+offset] in all other cases.
958 // This assumes that all array refs are "lowered" to one of these forms:
959 // %x = load (subarray*) ptr, constant ; single constant offset
960 // %x = load (subarray*) ptr, offsetVal ; single non-constant offset
961 // Generally, this should happen via strength reduction + LICM.
962 // Also, strength reduction should take care of using the same register for
963 // the loop index variable and an array index, when that is profitable.
964 //------------------------------------------------------------------------
967 SetOperandsForMemInstr(vector<MachineInstr*>& mvec,
968 InstructionNode* vmInstrNode,
969 const TargetMachine& target)
971 Instruction* memInst = vmInstrNode->getInstruction();
972 vector<MachineInstr*>::iterator mvecI = mvec.end() - 1;
974 // Index vector, ptr value, and flag if all indices are const.
975 vector<Value*> idxVec;
976 bool allConstantIndices;
977 Value* ptrVal = GetMemInstArgs(vmInstrNode, idxVec, allConstantIndices);
979 // Now create the appropriate operands for the machine instruction.
980 // First, initialize so we default to storing the offset in a register.
981 int64_t smallConstOffset = 0;
982 Value* valueForRegOffset = NULL;
983 MachineOperand::MachineOperandType offsetOpType =
984 MachineOperand::MO_VirtualRegister;
986 // Check if there is an index vector and if so, compute the
987 // right offset for structures and for arrays
991 const PointerType* ptrType = cast<PointerType>(ptrVal->getType());
993 // If all indices are constant, compute the combined offset directly.
994 if (allConstantIndices)
996 // Compute the offset value using the index vector. Create a
997 // virtual reg. for it since it may not fit in the immed field.
998 uint64_t offset = target.DataLayout.getIndexedOffset(ptrType,idxVec);
999 valueForRegOffset = ConstantSInt::get(Type::LongTy, offset);
1003 // There is at least one non-constant offset. Therefore, this must
1004 // be an array ref, and must have been lowered to a single non-zero
1005 // offset. (An extra leading zero offset, if any, can be ignored.)
1006 // Generate code sequence to compute address from index.
1008 bool firstIdxIsZero =
1009 (idxVec[0] == Constant::getNullValue(idxVec[0]->getType()));
1010 assert(idxVec.size() == 1U + firstIdxIsZero
1011 && "Array refs must be lowered before Instruction Selection");
1013 Value* idxVal = idxVec[firstIdxIsZero];
1015 vector<MachineInstr*> mulVec;
1016 Instruction* addr = new TmpInstruction(Type::ULongTy, memInst);
1017 MachineCodeForInstruction::get(memInst).addTemp(addr);
1019 // Get the array type indexed by idxVal, and compute its element size.
1020 // The call to getTypeSize() will fail if size is not constant.
1021 const Type* vecType = (firstIdxIsZero
1022 ? GetElementPtrInst::getIndexedType(ptrType,
1023 std::vector<Value*>(1U, idxVec[0]),
1024 /*AllowCompositeLeaf*/ true)
1026 const Type* eltType = cast<SequentialType>(vecType)->getElementType();
1027 ConstantUInt* eltSizeVal = ConstantUInt::get(Type::ULongTy,
1028 target.DataLayout.getTypeSize(eltType));
1030 // CreateMulInstruction() folds constants intelligently enough.
1031 CreateMulInstruction(target, memInst->getParent()->getParent(),
1032 idxVal, /* lval, not likely to be const*/
1033 eltSizeVal, /* rval, likely to be constant */
1035 mulVec, MachineCodeForInstruction::get(memInst),
1036 INVALID_MACHINE_OPCODE);
1038 // Insert mulVec[] before *mvecI in mvec[] and update mvecI
1039 // to point to the same instruction it pointed to before.
1040 assert(mulVec.size() > 0 && "No multiply code created?");
1041 vector<MachineInstr*>::iterator oldMvecI = mvecI;
1042 for (unsigned i=0, N=mulVec.size(); i < N; ++i)
1043 mvecI = mvec.insert(mvecI, mulVec[i]) + 1; // pts to mem instr
1045 valueForRegOffset = addr;
1050 offsetOpType = MachineOperand::MO_SignExtendedImmed;
1051 smallConstOffset = 0;
1055 // Operand 0 is value, operand 1 is ptr, operand 2 is offset
1056 // For LOAD or GET_ELEMENT_PTR,
1057 // Operand 0 is ptr, operand 1 is offset, operand 2 is result.
1059 unsigned offsetOpNum, ptrOpNum;
1060 if (memInst->getOpcode() == Instruction::Store)
1062 (*mvecI)->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister,
1063 vmInstrNode->leftChild()->getValue());
1071 (*mvecI)->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister,
1075 (*mvecI)->SetMachineOperandVal(ptrOpNum, MachineOperand::MO_VirtualRegister,
1078 if (offsetOpType == MachineOperand::MO_VirtualRegister)
1080 assert(valueForRegOffset != NULL);
1081 (*mvecI)->SetMachineOperandVal(offsetOpNum, offsetOpType,
1085 (*mvecI)->SetMachineOperandConst(offsetOpNum, offsetOpType,
1091 // Substitute operand `operandNum' of the instruction in node `treeNode'
1092 // in place of the use(s) of that instruction in node `parent'.
1093 // Check both explicit and implicit operands!
1094 // Also make sure to skip over a parent who:
1095 // (1) is a list node in the Burg tree, or
1096 // (2) itself had its results forwarded to its parent
1099 ForwardOperand(InstructionNode* treeNode,
1100 InstrTreeNode* parent,
1103 assert(treeNode && parent && "Invalid invocation of ForwardOperand");
1105 Instruction* unusedOp = treeNode->getInstruction();
1106 Value* fwdOp = unusedOp->getOperand(operandNum);
1108 // The parent itself may be a list node, so find the real parent instruction
1109 while (parent->getNodeType() != InstrTreeNode::NTInstructionNode)
1111 parent = parent->parent();
1112 assert(parent && "ERROR: Non-instruction node has no parent in tree.");
1114 InstructionNode* parentInstrNode = (InstructionNode*) parent;
1116 Instruction* userInstr = parentInstrNode->getInstruction();
1117 MachineCodeForInstruction &mvec = MachineCodeForInstruction::get(userInstr);
1119 // The parent's mvec would be empty if it was itself forwarded.
1120 // Recursively call ForwardOperand in that case...
1122 if (mvec.size() == 0)
1124 assert(parent->parent() != NULL &&
1125 "Parent could not have been forwarded, yet has no instructions?");
1126 ForwardOperand(treeNode, parent->parent(), operandNum);
1130 for (unsigned i=0, N=mvec.size(); i < N; i++)
1132 MachineInstr* minstr = mvec[i];
1133 for (unsigned i=0, numOps=minstr->getNumOperands(); i < numOps; ++i)
1135 const MachineOperand& mop = minstr->getOperand(i);
1136 if (mop.getType() == MachineOperand::MO_VirtualRegister &&
1137 mop.getVRegValue() == unusedOp)
1138 minstr->SetMachineOperandVal(i,
1139 MachineOperand::MO_VirtualRegister, fwdOp);
1142 for (unsigned i=0,numOps=minstr->getNumImplicitRefs(); i<numOps; ++i)
1143 if (minstr->getImplicitRef(i) == unusedOp)
1144 minstr->setImplicitRef(i, fwdOp,
1145 minstr->implicitRefIsDefined(i),
1146 minstr->implicitRefIsDefinedAndUsed(i));
1153 AllUsesAreBranches(const Instruction* setccI)
1155 for (Value::use_const_iterator UI=setccI->use_begin(), UE=setccI->use_end();
1157 if (! isa<TmpInstruction>(*UI) // ignore tmp instructions here
1158 && cast<Instruction>(*UI)->getOpcode() != Instruction::Br)
1163 //******************* Externally Visible Functions *************************/
1165 //------------------------------------------------------------------------
1166 // External Function: ThisIsAChainRule
1169 // Check if a given BURG rule is a chain rule.
1170 //------------------------------------------------------------------------
1173 ThisIsAChainRule(int eruleno)
1177 case 111: // stmt: reg
1201 return false; break;
1206 //------------------------------------------------------------------------
1207 // External Function: GetInstructionsByRule
1210 // Choose machine instructions for the SPARC according to the
1211 // patterns chosen by the BURG-generated parser.
1212 //------------------------------------------------------------------------
1215 GetInstructionsByRule(InstructionNode* subtreeRoot,
1218 TargetMachine &target,
1219 vector<MachineInstr*>& mvec)
1221 bool checkCast = false; // initialize here to use fall-through
1222 bool maskUnsignedResult = false;
1224 int forwardOperandNum = -1;
1225 unsigned int allocaSize = 0;
1226 MachineInstr* M, *M2;
1231 // If the code for this instruction was folded into the parent (user),
1233 if (subtreeRoot->isFoldedIntoParent())
1237 // Let's check for chain rules outside the switch so that we don't have
1238 // to duplicate the list of chain rule production numbers here again
1240 if (ThisIsAChainRule(ruleForNode))
1242 // Chain rules have a single nonterminal on the RHS.
1243 // Get the rule that matches the RHS non-terminal and use that instead.
1245 assert(nts[0] && ! nts[1]
1246 && "A chain rule should have only one RHS non-terminal!");
1247 nextRule = burm_rule(subtreeRoot->state, nts[0]);
1248 nts = burm_nts[nextRule];
1249 GetInstructionsByRule(subtreeRoot, nextRule, nts, target, mvec);
1253 switch(ruleForNode) {
1254 case 1: // stmt: Ret
1255 case 2: // stmt: RetValue(reg)
1256 { // NOTE: Prepass of register allocation is responsible
1257 // for moving return value to appropriate register.
1258 // Mark the return-address register as a hidden virtual reg.
1259 // Mark the return value register as an implicit ref of
1260 // the machine instruction.
1261 // Finally put a NOP in the delay slot.
1262 ReturnInst *returnInstr =
1263 cast<ReturnInst>(subtreeRoot->getInstruction());
1264 assert(returnInstr->getOpcode() == Instruction::Ret);
1266 Instruction* returnReg = new TmpInstruction(returnInstr);
1267 MachineCodeForInstruction::get(returnInstr).addTemp(returnReg);
1269 M = new MachineInstr(JMPLRET);
1270 M->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister,
1272 M->SetMachineOperandConst(1,MachineOperand::MO_SignExtendedImmed,
1274 M->SetMachineOperandReg(2, target.getRegInfo().getZeroRegNum());
1276 if (returnInstr->getReturnValue() != NULL)
1277 M->addImplicitRef(returnInstr->getReturnValue());
1280 mvec.push_back(new MachineInstr(NOP));
1285 case 3: // stmt: Store(reg,reg)
1286 case 4: // stmt: Store(reg,ptrreg)
1287 mvec.push_back(new MachineInstr(
1288 ChooseStoreInstruction(
1289 subtreeRoot->leftChild()->getValue()->getType())));
1290 SetOperandsForMemInstr(mvec, subtreeRoot, target);
1293 case 5: // stmt: BrUncond
1294 M = new MachineInstr(BA);
1295 M->SetMachineOperandVal(0, MachineOperand::MO_PCRelativeDisp,
1296 cast<BranchInst>(subtreeRoot->getInstruction())->getSuccessor(0));
1300 mvec.push_back(new MachineInstr(NOP));
1303 case 206: // stmt: BrCond(setCCconst)
1304 { // setCCconst => boolean was computed with `%b = setCC type reg1 const'
1305 // If the constant is ZERO, we can use the branch-on-integer-register
1306 // instructions and avoid the SUBcc instruction entirely.
1307 // Otherwise this is just the same as case 5, so just fall through.
1309 InstrTreeNode* constNode = subtreeRoot->leftChild()->rightChild();
1311 constNode->getNodeType() ==InstrTreeNode::NTConstNode);
1312 Constant *constVal = cast<Constant>(constNode->getValue());
1315 if ((constVal->getType()->isInteger()
1316 || isa<PointerType>(constVal->getType()))
1317 && GetConstantValueAsSignedInt(constVal, isValidConst) == 0
1320 // That constant is a zero after all...
1321 // Use the left child of setCC as the first argument!
1322 // Mark the setCC node so that no code is generated for it.
1323 InstructionNode* setCCNode = (InstructionNode*)
1324 subtreeRoot->leftChild();
1325 assert(setCCNode->getOpLabel() == SetCCOp);
1326 setCCNode->markFoldedIntoParent();
1328 BranchInst* brInst=cast<BranchInst>(subtreeRoot->getInstruction());
1330 M = new MachineInstr(ChooseBprInstruction(subtreeRoot));
1331 M->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister,
1332 setCCNode->leftChild()->getValue());
1333 M->SetMachineOperandVal(1, MachineOperand::MO_PCRelativeDisp,
1334 brInst->getSuccessor(0));
1338 mvec.push_back(new MachineInstr(NOP));
1341 M = new MachineInstr(BA);
1342 M->SetMachineOperandVal(0, MachineOperand::MO_PCRelativeDisp,
1343 brInst->getSuccessor(1));
1347 mvec.push_back(new MachineInstr(NOP));
1351 // ELSE FALL THROUGH
1354 case 6: // stmt: BrCond(setCC)
1355 { // bool => boolean was computed with SetCC.
1356 // The branch to use depends on whether it is FP, signed, or unsigned.
1357 // If it is an integer CC, we also need to find the unique
1358 // TmpInstruction representing that CC.
1360 BranchInst* brInst = cast<BranchInst>(subtreeRoot->getInstruction());
1362 M = new MachineInstr(ChooseBccInstruction(subtreeRoot, isFPBranch));
1364 Value* ccValue = GetTmpForCC(subtreeRoot->leftChild()->getValue(),
1365 brInst->getParent()->getParent(),
1366 isFPBranch? Type::FloatTy : Type::IntTy);
1368 M->SetMachineOperandVal(0, MachineOperand::MO_CCRegister, ccValue);
1369 M->SetMachineOperandVal(1, MachineOperand::MO_PCRelativeDisp,
1370 brInst->getSuccessor(0));
1374 mvec.push_back(new MachineInstr(NOP));
1377 M = new MachineInstr(BA);
1378 M->SetMachineOperandVal(0, MachineOperand::MO_PCRelativeDisp,
1379 brInst->getSuccessor(1));
1383 mvec.push_back(new MachineInstr(NOP));
1387 case 208: // stmt: BrCond(boolconst)
1389 // boolconst => boolean is a constant; use BA to first or second label
1390 Constant* constVal =
1391 cast<Constant>(subtreeRoot->leftChild()->getValue());
1392 unsigned dest = cast<ConstantBool>(constVal)->getValue()? 0 : 1;
1394 M = new MachineInstr(BA);
1395 M->SetMachineOperandVal(0, MachineOperand::MO_PCRelativeDisp,
1396 cast<BranchInst>(subtreeRoot->getInstruction())->getSuccessor(dest));
1400 mvec.push_back(new MachineInstr(NOP));
1404 case 8: // stmt: BrCond(boolreg)
1405 { // boolreg => boolean is stored in an existing register.
1406 // Just use the branch-on-integer-register instruction!
1408 M = new MachineInstr(BRNZ);
1409 M->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister,
1410 subtreeRoot->leftChild()->getValue());
1411 M->SetMachineOperandVal(1, MachineOperand::MO_PCRelativeDisp,
1412 cast<BranchInst>(subtreeRoot->getInstruction())->getSuccessor(0));
1416 mvec.push_back(new MachineInstr(NOP));
1419 M = new MachineInstr(BA);
1420 M->SetMachineOperandVal(0, MachineOperand::MO_PCRelativeDisp,
1421 cast<BranchInst>(subtreeRoot->getInstruction())->getSuccessor(1));
1425 mvec.push_back(new MachineInstr(NOP));
1429 case 9: // stmt: Switch(reg)
1430 assert(0 && "*** SWITCH instruction is not implemented yet.");
1433 case 10: // reg: VRegList(reg, reg)
1434 assert(0 && "VRegList should never be the topmost non-chain rule");
1437 case 21: // bool: Not(bool,reg): Both these are implemented as:
1438 case 421: // reg: BNot(reg,reg): reg = reg XOR-NOT 0
1439 { // First find the unary operand. It may be left or right, usually right.
1440 Value* notArg = BinaryOperator::getNotArgument(
1441 cast<BinaryOperator>(subtreeRoot->getInstruction()));
1442 mvec.push_back(Create3OperandInstr_Reg(XNOR, notArg,
1443 target.getRegInfo().getZeroRegNum(),
1444 subtreeRoot->getValue()));
1448 case 22: // reg: ToBoolTy(reg):
1450 const Type* opType = subtreeRoot->leftChild()->getValue()->getType();
1451 assert(opType->isIntegral() || isa<PointerType>(opType));
1452 forwardOperandNum = 0; // forward first operand to user
1456 case 23: // reg: ToUByteTy(reg)
1457 case 24: // reg: ToSByteTy(reg)
1458 case 25: // reg: ToUShortTy(reg)
1459 case 26: // reg: ToShortTy(reg)
1460 case 27: // reg: ToUIntTy(reg)
1461 case 28: // reg: ToIntTy(reg)
1463 //======================================================================
1464 // Rules for integer conversions:
1467 // From ISO 1998 C++ Standard, Sec. 4.7:
1469 // 2. If the destination type is unsigned, the resulting value is
1470 // the least unsigned integer congruent to the source integer
1471 // (modulo 2n where n is the number of bits used to represent the
1472 // unsigned type). [Note: In a two s complement representation,
1473 // this conversion is conceptual and there is no change in the
1474 // bit pattern (if there is no truncation). ]
1476 // 3. If the destination type is signed, the value is unchanged if
1477 // it can be represented in the destination type (and bitfield width);
1478 // otherwise, the value is implementation-defined.
1481 // Since we assume 2s complement representations, this implies:
1483 // -- if operand is smaller than destination, zero-extend or sign-extend
1484 // according to the signedness of the *operand*: source decides.
1485 // ==> we have to do nothing here!
1487 // -- if operand is same size as or larger than destination, and the
1488 // destination is *unsigned*, zero-extend the operand: dest. decides
1490 // -- if operand is same size as or larger than destination, and the
1491 // destination is *signed*, the choice is implementation defined:
1492 // we sign-extend the operand: i.e., again dest. decides.
1493 // Note: this matches both Sun's cc and gcc3.2.
1494 //======================================================================
1496 Instruction* destI = subtreeRoot->getInstruction();
1497 Value* opVal = subtreeRoot->leftChild()->getValue();
1498 const Type* opType = opVal->getType();
1499 if (opType->isIntegral() || isa<PointerType>(opType))
1501 unsigned opSize = target.DataLayout.getTypeSize(opType);
1502 unsigned destSize = target.DataLayout.getTypeSize(destI->getType());
1503 if (opSize >= destSize)
1504 { // Operand is same size as or larger than dest:
1505 // zero- or sign-extend, according to the signeddness of
1506 // the destination (see above).
1507 if (destI->getType()->isSigned())
1508 target.getInstrInfo().CreateSignExtensionInstructions(target,
1509 destI->getParent()->getParent(), opVal, destI, 8*destSize,
1510 mvec, MachineCodeForInstruction::get(destI));
1512 target.getInstrInfo().CreateZeroExtensionInstructions(target,
1513 destI->getParent()->getParent(), opVal, destI, 8*destSize,
1514 mvec, MachineCodeForInstruction::get(destI));
1517 forwardOperandNum = 0; // forward first operand to user
1519 else if (opType->isFloatingPoint())
1521 CreateCodeToConvertFloatToInt(target, opVal, destI, mvec,
1522 MachineCodeForInstruction::get(destI));
1523 if (destI->getType()->isUnsigned())
1524 maskUnsignedResult = true; // not handled by fp->int code
1527 assert(0 && "Unrecognized operand type for convert-to-unsigned");
1532 case 29: // reg: ToULongTy(reg)
1533 case 30: // reg: ToLongTy(reg)
1535 Value* opVal = subtreeRoot->leftChild()->getValue();
1536 const Type* opType = opVal->getType();
1537 if (opType->isIntegral() || isa<PointerType>(opType))
1538 forwardOperandNum = 0; // forward first operand to user
1539 else if (opType->isFloatingPoint())
1541 Instruction* destI = subtreeRoot->getInstruction();
1542 CreateCodeToConvertFloatToInt(target, opVal, destI, mvec,
1543 MachineCodeForInstruction::get(destI));
1546 assert(0 && "Unrecognized operand type for convert-to-signed");
1550 case 31: // reg: ToFloatTy(reg):
1551 case 32: // reg: ToDoubleTy(reg):
1552 case 232: // reg: ToDoubleTy(Constant):
1554 // If this instruction has a parent (a user) in the tree
1555 // and the user is translated as an FsMULd instruction,
1556 // then the cast is unnecessary. So check that first.
1557 // In the future, we'll want to do the same for the FdMULq instruction,
1558 // so do the check here instead of only for ToFloatTy(reg).
1560 if (subtreeRoot->parent() != NULL)
1562 const MachineCodeForInstruction& mcfi =
1563 MachineCodeForInstruction::get(
1564 cast<InstructionNode>(subtreeRoot->parent())->getInstruction());
1565 if (mcfi.size() == 0 || mcfi.front()->getOpCode() == FSMULD)
1566 forwardOperandNum = 0; // forward first operand to user
1569 if (forwardOperandNum != 0) // we do need the cast
1571 Value* leftVal = subtreeRoot->leftChild()->getValue();
1572 const Type* opType = leftVal->getType();
1573 MachineOpCode opCode=ChooseConvertToFloatInstr(
1574 subtreeRoot->getOpLabel(), opType);
1575 if (opCode == INVALID_OPCODE) // no conversion needed
1577 forwardOperandNum = 0; // forward first operand to user
1581 // If the source operand is a non-FP type it must be
1582 // first copied from int to float register via memory!
1583 Instruction *dest = subtreeRoot->getInstruction();
1586 if (! opType->isFloatingPoint())
1588 // Create a temporary to represent the FP register
1589 // into which the integer will be copied via memory.
1590 // The type of this temporary will determine the FP
1591 // register used: single-prec for a 32-bit int or smaller,
1592 // double-prec for a 64-bit int.
1595 target.DataLayout.getTypeSize(leftVal->getType());
1596 Type* tmpTypeToUse =
1597 (srcSize <= 4)? Type::FloatTy : Type::DoubleTy;
1598 srcForCast = new TmpInstruction(tmpTypeToUse, dest);
1599 MachineCodeForInstruction &destMCFI =
1600 MachineCodeForInstruction::get(dest);
1601 destMCFI.addTemp(srcForCast);
1603 target.getInstrInfo().CreateCodeToCopyIntToFloat(target,
1604 dest->getParent()->getParent(),
1605 leftVal, cast<Instruction>(srcForCast),
1609 srcForCast = leftVal;
1611 M = new MachineInstr(opCode);
1612 M->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister,
1614 M->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister,
1621 case 19: // reg: ToArrayTy(reg):
1622 case 20: // reg: ToPointerTy(reg):
1623 forwardOperandNum = 0; // forward first operand to user
1626 case 233: // reg: Add(reg, Constant)
1627 maskUnsignedResult = true;
1628 M = CreateAddConstInstruction(subtreeRoot);
1634 // ELSE FALL THROUGH
1636 case 33: // reg: Add(reg, reg)
1637 maskUnsignedResult = true;
1638 mvec.push_back(new MachineInstr(ChooseAddInstruction(subtreeRoot)));
1639 Set3OperandsFromInstr(mvec.back(), subtreeRoot, target);
1642 case 234: // reg: Sub(reg, Constant)
1643 maskUnsignedResult = true;
1644 M = CreateSubConstInstruction(subtreeRoot);
1650 // ELSE FALL THROUGH
1652 case 34: // reg: Sub(reg, reg)
1653 maskUnsignedResult = true;
1654 mvec.push_back(new MachineInstr(ChooseSubInstructionByType(
1655 subtreeRoot->getInstruction()->getType())));
1656 Set3OperandsFromInstr(mvec.back(), subtreeRoot, target);
1659 case 135: // reg: Mul(todouble, todouble)
1663 case 35: // reg: Mul(reg, reg)
1665 maskUnsignedResult = true;
1666 MachineOpCode forceOp = ((checkCast && BothFloatToDouble(subtreeRoot))
1668 : INVALID_MACHINE_OPCODE);
1669 Instruction* mulInstr = subtreeRoot->getInstruction();
1670 CreateMulInstruction(target, mulInstr->getParent()->getParent(),
1671 subtreeRoot->leftChild()->getValue(),
1672 subtreeRoot->rightChild()->getValue(),
1674 MachineCodeForInstruction::get(mulInstr),forceOp);
1677 case 335: // reg: Mul(todouble, todoubleConst)
1681 case 235: // reg: Mul(reg, Constant)
1683 maskUnsignedResult = true;
1684 MachineOpCode forceOp = ((checkCast && BothFloatToDouble(subtreeRoot))
1686 : INVALID_MACHINE_OPCODE);
1687 Instruction* mulInstr = subtreeRoot->getInstruction();
1688 CreateMulInstruction(target, mulInstr->getParent()->getParent(),
1689 subtreeRoot->leftChild()->getValue(),
1690 subtreeRoot->rightChild()->getValue(),
1692 MachineCodeForInstruction::get(mulInstr),
1696 case 236: // reg: Div(reg, Constant)
1697 maskUnsignedResult = true;
1699 CreateDivConstInstruction(target, subtreeRoot, mvec);
1700 if (mvec.size() > L)
1702 // ELSE FALL THROUGH
1704 case 36: // reg: Div(reg, reg)
1705 maskUnsignedResult = true;
1706 mvec.push_back(new MachineInstr(ChooseDivInstruction(target, subtreeRoot)));
1707 Set3OperandsFromInstr(mvec.back(), subtreeRoot, target);
1710 case 37: // reg: Rem(reg, reg)
1711 case 237: // reg: Rem(reg, Constant)
1713 maskUnsignedResult = true;
1714 Instruction* remInstr = subtreeRoot->getInstruction();
1716 TmpInstruction* quot = new TmpInstruction(
1717 subtreeRoot->leftChild()->getValue(),
1718 subtreeRoot->rightChild()->getValue());
1719 TmpInstruction* prod = new TmpInstruction(
1721 subtreeRoot->rightChild()->getValue());
1722 MachineCodeForInstruction::get(remInstr).addTemp(quot).addTemp(prod);
1724 M = new MachineInstr(ChooseDivInstruction(target, subtreeRoot));
1725 Set3OperandsFromInstr(M, subtreeRoot, target);
1726 M->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister,quot);
1729 M = Create3OperandInstr(ChooseMulInstructionByType(
1730 subtreeRoot->getInstruction()->getType()),
1731 quot, subtreeRoot->rightChild()->getValue(),
1735 M = new MachineInstr(ChooseSubInstructionByType(
1736 subtreeRoot->getInstruction()->getType()));
1737 Set3OperandsFromInstr(M, subtreeRoot, target);
1738 M->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister,prod);
1744 case 38: // bool: And(bool, bool)
1745 case 238: // bool: And(bool, boolconst)
1746 case 338: // reg : BAnd(reg, reg)
1747 case 538: // reg : BAnd(reg, Constant)
1748 mvec.push_back(new MachineInstr(AND));
1749 Set3OperandsFromInstr(mvec.back(), subtreeRoot, target);
1752 case 138: // bool: And(bool, not)
1753 case 438: // bool: BAnd(bool, bnot)
1754 { // Use the argument of NOT as the second argument!
1755 // Mark the NOT node so that no code is generated for it.
1756 InstructionNode* notNode = (InstructionNode*) subtreeRoot->rightChild();
1757 Value* notArg = BinaryOperator::getNotArgument(
1758 cast<BinaryOperator>(notNode->getInstruction()));
1759 notNode->markFoldedIntoParent();
1760 mvec.push_back(Create3OperandInstr(ANDN,
1761 subtreeRoot->leftChild()->getValue(),
1762 notArg, subtreeRoot->getValue()));
1766 case 39: // bool: Or(bool, bool)
1767 case 239: // bool: Or(bool, boolconst)
1768 case 339: // reg : BOr(reg, reg)
1769 case 539: // reg : BOr(reg, Constant)
1770 mvec.push_back(new MachineInstr(OR));
1771 Set3OperandsFromInstr(mvec.back(), subtreeRoot, target);
1774 case 139: // bool: Or(bool, not)
1775 case 439: // bool: BOr(bool, bnot)
1776 { // Use the argument of NOT as the second argument!
1777 // Mark the NOT node so that no code is generated for it.
1778 InstructionNode* notNode = (InstructionNode*) subtreeRoot->rightChild();
1779 Value* notArg = BinaryOperator::getNotArgument(
1780 cast<BinaryOperator>(notNode->getInstruction()));
1781 notNode->markFoldedIntoParent();
1782 mvec.push_back(Create3OperandInstr(ORN,
1783 subtreeRoot->leftChild()->getValue(),
1784 notArg, subtreeRoot->getValue()));
1788 case 40: // bool: Xor(bool, bool)
1789 case 240: // bool: Xor(bool, boolconst)
1790 case 340: // reg : BXor(reg, reg)
1791 case 540: // reg : BXor(reg, Constant)
1792 mvec.push_back(new MachineInstr(XOR));
1793 Set3OperandsFromInstr(mvec.back(), subtreeRoot, target);
1796 case 140: // bool: Xor(bool, not)
1797 case 440: // bool: BXor(bool, bnot)
1798 { // Use the argument of NOT as the second argument!
1799 // Mark the NOT node so that no code is generated for it.
1800 InstructionNode* notNode = (InstructionNode*) subtreeRoot->rightChild();
1801 Value* notArg = BinaryOperator::getNotArgument(
1802 cast<BinaryOperator>(notNode->getInstruction()));
1803 notNode->markFoldedIntoParent();
1804 mvec.push_back(Create3OperandInstr(XNOR,
1805 subtreeRoot->leftChild()->getValue(),
1806 notArg, subtreeRoot->getValue()));
1810 case 41: // boolconst: SetCC(reg, Constant)
1812 // If the SetCC was folded into the user (parent), it will be
1813 // caught above. All other cases are the same as case 42,
1814 // so just fall through.
1816 case 42: // bool: SetCC(reg, reg):
1818 // This generates a SUBCC instruction, putting the difference in
1819 // a result register, and setting a condition code.
1821 // If the boolean result of the SetCC is used by anything other
1822 // than a branch instruction, or if it is used outside the current
1823 // basic block, the boolean must be
1824 // computed and stored in the result register. Otherwise, discard
1825 // the difference (by using %g0) and keep only the condition code.
1827 // To compute the boolean result in a register we use a conditional
1828 // move, unless the result of the SUBCC instruction can be used as
1829 // the bool! This assumes that zero is FALSE and any non-zero
1832 InstructionNode* parentNode = (InstructionNode*) subtreeRoot->parent();
1833 Instruction* setCCInstr = subtreeRoot->getInstruction();
1835 bool keepBoolVal = parentNode == NULL ||
1836 ! AllUsesAreBranches(setCCInstr);
1837 bool subValIsBoolVal = setCCInstr->getOpcode() == Instruction::SetNE;
1838 bool keepSubVal = keepBoolVal && subValIsBoolVal;
1839 bool computeBoolVal = keepBoolVal && ! subValIsBoolVal;
1843 MachineOpCode movOpCode = 0;
1845 // Mark the 4th operand as being a CC register, and as a def
1846 // A TmpInstruction is created to represent the CC "result".
1847 // Unlike other instances of TmpInstruction, this one is used
1848 // by machine code of multiple LLVM instructions, viz.,
1849 // the SetCC and the branch. Make sure to get the same one!
1850 // Note that we do this even for FP CC registers even though they
1851 // are explicit operands, because the type of the operand
1852 // needs to be a floating point condition code, not an integer
1853 // condition code. Think of this as casting the bool result to
1854 // a FP condition code register.
1856 Value* leftVal = subtreeRoot->leftChild()->getValue();
1857 bool isFPCompare = leftVal->getType()->isFloatingPoint();
1859 TmpInstruction* tmpForCC = GetTmpForCC(setCCInstr,
1860 setCCInstr->getParent()->getParent(),
1861 isFPCompare ? Type::FloatTy : Type::IntTy);
1862 MachineCodeForInstruction::get(setCCInstr).addTemp(tmpForCC);
1866 // Integer condition: dest. should be %g0 or an integer register.
1867 // If result must be saved but condition is not SetEQ then we need
1868 // a separate instruction to compute the bool result, so discard
1869 // result of SUBcc instruction anyway.
1871 M = new MachineInstr(SUBcc);
1872 Set3OperandsFromInstr(M, subtreeRoot, target, ! keepSubVal);
1873 M->SetMachineOperandVal(3, MachineOperand::MO_CCRegister,
1874 tmpForCC, /*def*/true);
1878 { // recompute bool using the integer condition codes
1880 ChooseMovpccAfterSub(subtreeRoot,mustClearReg,valueToMove);
1885 // FP condition: dest of FCMP should be some FCCn register
1886 M = new MachineInstr(ChooseFcmpInstruction(subtreeRoot));
1887 M->SetMachineOperandVal(0, MachineOperand::MO_CCRegister,
1889 M->SetMachineOperandVal(1,MachineOperand::MO_VirtualRegister,
1890 subtreeRoot->leftChild()->getValue());
1891 M->SetMachineOperandVal(2,MachineOperand::MO_VirtualRegister,
1892 subtreeRoot->rightChild()->getValue());
1896 {// recompute bool using the FP condition codes
1897 mustClearReg = true;
1899 movOpCode = ChooseMovFpccInstruction(subtreeRoot);
1906 {// Unconditionally set register to 0
1907 M = new MachineInstr(SETHI);
1908 M->SetMachineOperandConst(0,MachineOperand::MO_UnextendedImmed,
1910 M->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister,
1915 // Now conditionally move `valueToMove' (0 or 1) into the register
1916 // Mark the register as a use (as well as a def) because the old
1917 // value should be retained if the condition is false.
1918 M = new MachineInstr(movOpCode);
1919 M->SetMachineOperandVal(0, MachineOperand::MO_CCRegister,
1921 M->SetMachineOperandConst(1, MachineOperand::MO_UnextendedImmed,
1923 M->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister,
1924 setCCInstr, /*isDef*/ true,
1925 /*isDefAndUse*/ true);
1931 case 51: // reg: Load(reg)
1932 case 52: // reg: Load(ptrreg)
1933 mvec.push_back(new MachineInstr(ChooseLoadInstruction(
1934 subtreeRoot->getValue()->getType())));
1935 SetOperandsForMemInstr(mvec, subtreeRoot, target);
1938 case 55: // reg: GetElemPtr(reg)
1939 case 56: // reg: GetElemPtrIdx(reg,reg)
1940 // If the GetElemPtr was folded into the user (parent), it will be
1941 // caught above. For other cases, we have to compute the address.
1942 mvec.push_back(new MachineInstr(ADD));
1943 SetOperandsForMemInstr(mvec, subtreeRoot, target);
1946 case 57: // reg: Alloca: Implement as 1 instruction:
1947 { // add %fp, offsetFromFP -> result
1948 AllocationInst* instr =
1949 cast<AllocationInst>(subtreeRoot->getInstruction());
1950 unsigned int tsize =
1951 target.DataLayout.getTypeSize(instr->getAllocatedType());
1953 CreateCodeForFixedSizeAlloca(target, instr, tsize, 1, mvec);
1957 case 58: // reg: Alloca(reg): Implement as 3 instructions:
1958 // mul num, typeSz -> tmp
1959 // sub %sp, tmp -> %sp
1960 { // add %sp, frameSizeBelowDynamicArea -> result
1961 AllocationInst* instr =
1962 cast<AllocationInst>(subtreeRoot->getInstruction());
1963 const Type* eltType = instr->getAllocatedType();
1965 // If #elements is constant, use simpler code for fixed-size allocas
1966 int tsize = (int) target.DataLayout.getTypeSize(eltType);
1967 Value* numElementsVal = NULL;
1968 bool isArray = instr->isArrayAllocation();
1971 isa<Constant>(numElementsVal = instr->getArraySize()))
1972 { // total size is constant: generate code for fixed-size alloca
1973 unsigned int numElements = isArray?
1974 cast<ConstantUInt>(numElementsVal)->getValue() : 1;
1975 CreateCodeForFixedSizeAlloca(target, instr, tsize,
1978 else // total size is not constant.
1979 CreateCodeForVariableSizeAlloca(target, instr, tsize,
1980 numElementsVal, mvec);
1984 case 61: // reg: Call
1985 { // Generate a direct (CALL) or indirect (JMPL) call.
1986 // Mark the return-address register, the indirection
1987 // register (for indirect calls), the operands of the Call,
1988 // and the return value (if any) as implicit operands
1989 // of the machine instruction.
1991 // If this is a varargs function, floating point arguments
1992 // have to passed in integer registers so insert
1993 // copy-float-to-int instructions for each float operand.
1995 CallInst *callInstr = cast<CallInst>(subtreeRoot->getInstruction());
1996 Value *callee = callInstr->getCalledValue();
1998 // Create hidden virtual register for return address with type void*
1999 TmpInstruction* retAddrReg =
2000 new TmpInstruction(PointerType::get(Type::VoidTy), callInstr);
2001 MachineCodeForInstruction::get(callInstr).addTemp(retAddrReg);
2003 // Generate the machine instruction and its operands.
2004 // Use CALL for direct function calls; this optimistically assumes
2005 // the PC-relative address fits in the CALL address field (22 bits).
2006 // Use JMPL for indirect calls.
2008 if (isa<Function>(callee)) // direct function call
2009 M = Create1OperandInstr_Addr(CALL, callee);
2010 else // indirect function call
2011 M = Create3OperandInstr_SImmed(JMPLCALL, callee,
2012 (int64_t) 0, retAddrReg);
2015 const FunctionType* funcType =
2016 cast<FunctionType>(cast<PointerType>(callee->getType())
2017 ->getElementType());
2018 bool isVarArgs = funcType->isVarArg();
2019 bool noPrototype = isVarArgs && funcType->getNumParams() == 0;
2021 // Use a descriptor to pass information about call arguments
2022 // to the register allocator. This descriptor will be "owned"
2023 // and freed automatically when the MachineCodeForInstruction
2024 // object for the callInstr goes away.
2025 CallArgsDescriptor* argDesc = new CallArgsDescriptor(callInstr,
2026 retAddrReg, isVarArgs, noPrototype);
2028 assert(callInstr->getOperand(0) == callee
2029 && "This is assumed in the loop below!");
2031 for (unsigned i=1, N=callInstr->getNumOperands(); i < N; ++i)
2033 Value* argVal = callInstr->getOperand(i);
2034 Instruction* intArgReg = NULL;
2036 // Check for FP arguments to varargs functions.
2037 // Any such argument in the first $K$ args must be passed in an
2038 // integer register, where K = #integer argument registers.
2039 if (isVarArgs && argVal->getType()->isFloatingPoint())
2041 // If it is a function with no prototype, pass value
2042 // as an FP value as well as a varargs value
2044 argDesc->getArgInfo(i-1).setUseFPArgReg();
2046 // If this arg. is in the first $K$ regs, add a copy
2047 // float-to-int instruction to pass the value as an integer.
2048 if (i <= target.getRegInfo().GetNumOfIntArgRegs())
2050 MachineCodeForInstruction &destMCFI =
2051 MachineCodeForInstruction::get(callInstr);
2052 intArgReg = new TmpInstruction(Type::IntTy, argVal);
2053 destMCFI.addTemp(intArgReg);
2055 vector<MachineInstr*> copyMvec;
2056 target.getInstrInfo().CreateCodeToCopyFloatToInt(target,
2057 callInstr->getParent()->getParent(),
2058 argVal, (TmpInstruction*) intArgReg,
2059 copyMvec, destMCFI);
2060 mvec.insert(mvec.begin(),copyMvec.begin(),copyMvec.end());
2062 argDesc->getArgInfo(i-1).setUseIntArgReg();
2063 argDesc->getArgInfo(i-1).setArgCopy(intArgReg);
2066 // Cannot fit in first $K$ regs so pass the arg on the stack
2067 argDesc->getArgInfo(i-1).setUseStackSlot();
2071 mvec.back()->addImplicitRef(intArgReg);
2073 mvec.back()->addImplicitRef(argVal);
2076 // Add the return value as an implicit ref. The call operands
2077 // were added above.
2078 if (callInstr->getType() != Type::VoidTy)
2079 mvec.back()->addImplicitRef(callInstr, /*isDef*/ true);
2081 // For the CALL instruction, the ret. addr. reg. is also implicit
2082 if (isa<Function>(callee))
2083 mvec.back()->addImplicitRef(retAddrReg, /*isDef*/ true);
2086 mvec.push_back(new MachineInstr(NOP));
2090 case 62: // reg: Shl(reg, reg)
2092 Value* argVal1 = subtreeRoot->leftChild()->getValue();
2093 Value* argVal2 = subtreeRoot->rightChild()->getValue();
2094 Instruction* shlInstr = subtreeRoot->getInstruction();
2096 const Type* opType = argVal1->getType();
2097 assert((opType->isInteger() || isa<PointerType>(opType)) &&
2098 "Shl unsupported for other types");
2100 CreateShiftInstructions(target, shlInstr->getParent()->getParent(),
2101 (opType == Type::LongTy)? SLLX : SLL,
2102 argVal1, argVal2, 0, shlInstr, mvec,
2103 MachineCodeForInstruction::get(shlInstr));
2107 case 63: // reg: Shr(reg, reg)
2108 { const Type* opType = subtreeRoot->leftChild()->getValue()->getType();
2109 assert((opType->isInteger() || isa<PointerType>(opType)) &&
2110 "Shr unsupported for other types");
2111 mvec.push_back(new MachineInstr((opType->isSigned()
2112 ? ((opType == Type::LongTy)? SRAX : SRA)
2113 : ((opType == Type::LongTy)? SRLX : SRL))));
2114 Set3OperandsFromInstr(mvec.back(), subtreeRoot, target);
2118 case 64: // reg: Phi(reg,reg)
2119 break; // don't forward the value
2121 case 71: // reg: VReg
2122 case 72: // reg: Constant
2123 break; // don't forward the value
2126 assert(0 && "Unrecognized BURG rule");
2131 if (forwardOperandNum >= 0)
2132 { // We did not generate a machine instruction but need to use operand.
2133 // If user is in the same tree, replace Value in its machine operand.
2134 // If not, insert a copy instruction which should get coalesced away
2135 // by register allocation.
2136 if (subtreeRoot->parent() != NULL)
2137 ForwardOperand(subtreeRoot, subtreeRoot->parent(), forwardOperandNum);
2140 vector<MachineInstr*> minstrVec;
2141 Instruction* instr = subtreeRoot->getInstruction();
2142 target.getInstrInfo().
2143 CreateCopyInstructionsByType(target,
2144 instr->getParent()->getParent(),
2145 instr->getOperand(forwardOperandNum),
2147 MachineCodeForInstruction::get(instr));
2148 assert(minstrVec.size() > 0);
2149 mvec.insert(mvec.end(), minstrVec.begin(), minstrVec.end());
2153 if (maskUnsignedResult)
2154 { // If result is unsigned and smaller than int reg size,
2155 // we need to clear high bits of result value.
2156 assert(forwardOperandNum < 0 && "Need mask but no instruction generated");
2157 Instruction* dest = subtreeRoot->getInstruction();
2158 if (dest->getType()->isUnsigned())
2160 unsigned destSize = target.DataLayout.getTypeSize(dest->getType());
2162 { // Mask high bits. Use a TmpInstruction to represent the
2163 // intermediate result before masking. Since those instructions
2164 // have already been generated, go back and substitute tmpI
2165 // for dest in the result position of each one of them.
2166 TmpInstruction *tmpI = new TmpInstruction(dest->getType(), dest,
2168 MachineCodeForInstruction::get(dest).addTemp(tmpI);
2170 for (unsigned i=0, N=mvec.size(); i < N; ++i)
2171 mvec[i]->substituteValue(dest, tmpI);
2173 M = Create3OperandInstr_UImmed(SRL, tmpI, 8*(4-destSize), dest);
2176 else if (destSize < target.DataLayout.getIntegerRegize())
2177 assert(0 && "Unsupported type size: 32 < size < 64 bits");