1 //===-- SparcInstrSelection.cpp -------------------------------------------===//
3 // BURS instruction selection for SPARC V9 architecture.
5 //===----------------------------------------------------------------------===//
7 #include "SparcInternals.h"
8 #include "SparcInstrSelectionSupport.h"
9 #include "SparcRegClassInfo.h"
10 #include "llvm/CodeGen/InstrSelectionSupport.h"
11 #include "llvm/CodeGen/MachineInstr.h"
12 #include "llvm/CodeGen/MachineInstrAnnot.h"
13 #include "llvm/CodeGen/InstrForest.h"
14 #include "llvm/CodeGen/InstrSelection.h"
15 #include "llvm/CodeGen/MachineCodeForMethod.h"
16 #include "llvm/CodeGen/MachineCodeForInstruction.h"
17 #include "llvm/DerivedTypes.h"
18 #include "llvm/iTerminators.h"
19 #include "llvm/iMemory.h"
20 #include "llvm/iOther.h"
21 #include "llvm/Function.h"
22 #include "llvm/Constants.h"
23 #include "llvm/ConstantHandling.h"
24 #include "Support/MathExtras.h"
28 //************************ Internal Functions ******************************/
31 static inline MachineOpCode
32 ChooseBprInstruction(const InstructionNode* instrNode)
36 Instruction* setCCInstr =
37 ((InstructionNode*) instrNode->leftChild())->getInstruction();
39 switch(setCCInstr->getOpcode())
41 case Instruction::SetEQ: opCode = BRZ; break;
42 case Instruction::SetNE: opCode = BRNZ; break;
43 case Instruction::SetLE: opCode = BRLEZ; break;
44 case Instruction::SetGE: opCode = BRGEZ; break;
45 case Instruction::SetLT: opCode = BRLZ; break;
46 case Instruction::SetGT: opCode = BRGZ; break;
48 assert(0 && "Unrecognized VM instruction!");
49 opCode = INVALID_OPCODE;
57 static inline MachineOpCode
58 ChooseBpccInstruction(const InstructionNode* instrNode,
59 const BinaryOperator* setCCInstr)
61 MachineOpCode opCode = INVALID_OPCODE;
63 bool isSigned = setCCInstr->getOperand(0)->getType()->isSigned();
67 switch(setCCInstr->getOpcode())
69 case Instruction::SetEQ: opCode = BE; break;
70 case Instruction::SetNE: opCode = BNE; break;
71 case Instruction::SetLE: opCode = BLE; break;
72 case Instruction::SetGE: opCode = BGE; break;
73 case Instruction::SetLT: opCode = BL; break;
74 case Instruction::SetGT: opCode = BG; break;
76 assert(0 && "Unrecognized VM instruction!");
82 switch(setCCInstr->getOpcode())
84 case Instruction::SetEQ: opCode = BE; break;
85 case Instruction::SetNE: opCode = BNE; break;
86 case Instruction::SetLE: opCode = BLEU; break;
87 case Instruction::SetGE: opCode = BCC; break;
88 case Instruction::SetLT: opCode = BCS; break;
89 case Instruction::SetGT: opCode = BGU; break;
91 assert(0 && "Unrecognized VM instruction!");
99 static inline MachineOpCode
100 ChooseBFpccInstruction(const InstructionNode* instrNode,
101 const BinaryOperator* setCCInstr)
103 MachineOpCode opCode = INVALID_OPCODE;
105 switch(setCCInstr->getOpcode())
107 case Instruction::SetEQ: opCode = FBE; break;
108 case Instruction::SetNE: opCode = FBNE; break;
109 case Instruction::SetLE: opCode = FBLE; break;
110 case Instruction::SetGE: opCode = FBGE; break;
111 case Instruction::SetLT: opCode = FBL; break;
112 case Instruction::SetGT: opCode = FBG; break;
114 assert(0 && "Unrecognized VM instruction!");
122 // Create a unique TmpInstruction for a boolean value,
123 // representing the CC register used by a branch on that value.
124 // For now, hack this using a little static cache of TmpInstructions.
125 // Eventually the entire BURG instruction selection should be put
126 // into a separate class that can hold such information.
127 // The static cache is not too bad because the memory for these
128 // TmpInstructions will be freed along with the rest of the Function anyway.
130 static TmpInstruction*
131 GetTmpForCC(Value* boolVal, const Function *F, const Type* ccType)
133 typedef hash_map<const Value*, TmpInstruction*> BoolTmpCache;
134 static BoolTmpCache boolToTmpCache; // Map boolVal -> TmpInstruction*
135 static const Function *lastFunction = 0;// Use to flush cache between funcs
137 assert(boolVal->getType() == Type::BoolTy && "Weird but ok! Delete assert");
139 if (lastFunction != F)
142 boolToTmpCache.clear();
145 // Look for tmpI and create a new one otherwise. The new value is
146 // directly written to map using the ref returned by operator[].
147 TmpInstruction*& tmpI = boolToTmpCache[boolVal];
149 tmpI = new TmpInstruction(ccType, boolVal);
155 static inline MachineOpCode
156 ChooseBccInstruction(const InstructionNode* instrNode,
159 InstructionNode* setCCNode = (InstructionNode*) instrNode->leftChild();
160 assert(setCCNode->getOpLabel() == SetCCOp);
161 BinaryOperator* setCCInstr =cast<BinaryOperator>(setCCNode->getInstruction());
162 const Type* setCCType = setCCInstr->getOperand(0)->getType();
164 isFPBranch = setCCType->isFloatingPoint(); // Return value: don't delete!
167 return ChooseBFpccInstruction(instrNode, setCCInstr);
169 return ChooseBpccInstruction(instrNode, setCCInstr);
173 static inline MachineOpCode
174 ChooseMovFpccInstruction(const InstructionNode* instrNode)
176 MachineOpCode opCode = INVALID_OPCODE;
178 switch(instrNode->getInstruction()->getOpcode())
180 case Instruction::SetEQ: opCode = MOVFE; break;
181 case Instruction::SetNE: opCode = MOVFNE; break;
182 case Instruction::SetLE: opCode = MOVFLE; break;
183 case Instruction::SetGE: opCode = MOVFGE; break;
184 case Instruction::SetLT: opCode = MOVFL; break;
185 case Instruction::SetGT: opCode = MOVFG; break;
187 assert(0 && "Unrecognized VM instruction!");
195 // Assumes that SUBcc v1, v2 -> v3 has been executed.
196 // In most cases, we want to clear v3 and then follow it by instruction
198 // Set mustClearReg=false if v3 need not be cleared before conditional move.
199 // Set valueToMove=0 if we want to conditionally move 0 instead of 1
200 // (i.e., we want to test inverse of a condition)
201 // (The latter two cases do not seem to arise because SetNE needs nothing.)
204 ChooseMovpccAfterSub(const InstructionNode* instrNode,
208 MachineOpCode opCode = INVALID_OPCODE;
212 switch(instrNode->getInstruction()->getOpcode())
214 case Instruction::SetEQ: opCode = MOVE; break;
215 case Instruction::SetLE: opCode = MOVLE; break;
216 case Instruction::SetGE: opCode = MOVGE; break;
217 case Instruction::SetLT: opCode = MOVL; break;
218 case Instruction::SetGT: opCode = MOVG; break;
219 case Instruction::SetNE: assert(0 && "No move required!"); break;
220 default: assert(0 && "Unrecognized VM instr!"); break;
226 static inline MachineOpCode
227 ChooseConvertToFloatInstr(OpLabel vopCode, const Type* opType)
229 MachineOpCode opCode = INVALID_OPCODE;
234 if (opType == Type::SByteTy || opType == Type::ShortTy || opType == Type::IntTy)
236 else if (opType == Type::LongTy)
238 else if (opType == Type::DoubleTy)
240 else if (opType == Type::FloatTy)
243 assert(0 && "Cannot convert this type to FLOAT on SPARC");
247 // This is usually used in conjunction with CreateCodeToCopyIntToFloat().
248 // Both functions should treat the integer as a 32-bit value for types
249 // of 4 bytes or less, and as a 64-bit value otherwise.
250 if (opType == Type::SByteTy || opType == Type::UByteTy ||
251 opType == Type::ShortTy || opType == Type::UShortTy ||
252 opType == Type::IntTy || opType == Type::UIntTy)
254 else if (opType == Type::LongTy || opType == Type::ULongTy)
256 else if (opType == Type::FloatTy)
258 else if (opType == Type::DoubleTy)
261 assert(0 && "Cannot convert this type to DOUBLE on SPARC");
271 static inline MachineOpCode
272 ChooseConvertFPToIntInstr(Type::PrimitiveID tid, const Type* opType)
274 MachineOpCode opCode = INVALID_OPCODE;;
276 assert((opType == Type::FloatTy || opType == Type::DoubleTy)
277 && "This function should only be called for FLOAT or DOUBLE");
279 if (tid==Type::UIntTyID)
281 assert(tid != Type::UIntTyID && "FP-to-uint conversions must be expanded"
282 " into FP->long->uint for SPARC v9: SO RUN PRESELECTION PASS!");
284 else if (tid==Type::SByteTyID || tid==Type::ShortTyID || tid==Type::IntTyID ||
285 tid==Type::UByteTyID || tid==Type::UShortTyID)
287 opCode = (opType == Type::FloatTy)? FSTOI : FDTOI;
289 else if (tid==Type::LongTyID || tid==Type::ULongTyID)
291 opCode = (opType == Type::FloatTy)? FSTOX : FDTOX;
294 assert(0 && "Should not get here, Mo!");
300 CreateConvertFPToIntInstr(Type::PrimitiveID destTID,
301 Value* srcVal, Value* destVal)
303 MachineOpCode opCode = ChooseConvertFPToIntInstr(destTID, srcVal->getType());
304 assert(opCode != INVALID_OPCODE && "Expected to need conversion!");
306 MachineInstr* M = new MachineInstr(opCode);
307 M->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister, srcVal);
308 M->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister, destVal);
312 // CreateCodeToConvertFloatToInt: Convert FP value to signed or unsigned integer
313 // The FP value must be converted to the dest type in an FP register,
314 // and the result is then copied from FP to int register via memory.
316 // Since fdtoi converts to signed integers, any FP value V between MAXINT+1
317 // and MAXUNSIGNED (i.e., 2^31 <= V <= 2^32-1) would be converted incorrectly
318 // *only* when converting to an unsigned int. (Unsigned byte, short or long
319 // don't have this problem.)
320 // For unsigned int, we therefore have to generate the code sequence:
322 // if (V > (float) MAXINT) {
323 // unsigned result = (unsigned) (V - (float) MAXINT);
324 // result = result + (unsigned) MAXINT;
327 // result = (unsigned int) V;
330 CreateCodeToConvertFloatToInt(const TargetMachine& target,
333 std::vector<MachineInstr*>& mvec,
334 MachineCodeForInstruction& mcfi)
336 // Create a temporary to represent the FP register into which the
337 // int value will placed after conversion. The type of this temporary
338 // depends on the type of FP register to use: single-prec for a 32-bit
339 // int or smaller; double-prec for a 64-bit int.
341 size_t destSize = target.DataLayout.getTypeSize(destI->getType());
342 const Type* destTypeToUse = (destSize > 4)? Type::DoubleTy : Type::FloatTy;
343 TmpInstruction* destForCast = new TmpInstruction(destTypeToUse, opVal);
344 mcfi.addTemp(destForCast);
346 // Create the fp-to-int conversion code
347 MachineInstr* M =CreateConvertFPToIntInstr(destI->getType()->getPrimitiveID(),
351 // Create the fpreg-to-intreg copy code
352 target.getInstrInfo().
353 CreateCodeToCopyFloatToInt(target, destI->getParent()->getParent(),
354 destForCast, destI, mvec, mcfi);
358 static inline MachineOpCode
359 ChooseAddInstruction(const InstructionNode* instrNode)
361 return ChooseAddInstructionByType(instrNode->getInstruction()->getType());
365 static inline MachineInstr*
366 CreateMovFloatInstruction(const InstructionNode* instrNode,
367 const Type* resultType)
369 MachineInstr* minstr = new MachineInstr((resultType == Type::FloatTy)
371 minstr->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister,
372 instrNode->leftChild()->getValue());
373 minstr->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister,
374 instrNode->getValue());
378 static inline MachineInstr*
379 CreateAddConstInstruction(const InstructionNode* instrNode)
381 MachineInstr* minstr = NULL;
383 Value* constOp = ((InstrTreeNode*) instrNode->rightChild())->getValue();
384 assert(isa<Constant>(constOp));
386 // Cases worth optimizing are:
387 // (1) Add with 0 for float or double: use an FMOV of appropriate type,
388 // instead of an FADD (1 vs 3 cycles). There is no integer MOV.
390 if (ConstantFP *FPC = dyn_cast<ConstantFP>(constOp)) {
391 double dval = FPC->getValue();
393 minstr = CreateMovFloatInstruction(instrNode,
394 instrNode->getInstruction()->getType());
401 static inline MachineOpCode
402 ChooseSubInstructionByType(const Type* resultType)
404 MachineOpCode opCode = INVALID_OPCODE;
406 if (resultType->isInteger() || isa<PointerType>(resultType))
411 switch(resultType->getPrimitiveID())
413 case Type::FloatTyID: opCode = FSUBS; break;
414 case Type::DoubleTyID: opCode = FSUBD; break;
415 default: assert(0 && "Invalid type for SUB instruction"); break;
422 static inline MachineInstr*
423 CreateSubConstInstruction(const InstructionNode* instrNode)
425 MachineInstr* minstr = NULL;
427 Value* constOp = ((InstrTreeNode*) instrNode->rightChild())->getValue();
428 assert(isa<Constant>(constOp));
430 // Cases worth optimizing are:
431 // (1) Sub with 0 for float or double: use an FMOV of appropriate type,
432 // instead of an FSUB (1 vs 3 cycles). There is no integer MOV.
434 if (ConstantFP *FPC = dyn_cast<ConstantFP>(constOp)) {
435 double dval = FPC->getValue();
437 minstr = CreateMovFloatInstruction(instrNode,
438 instrNode->getInstruction()->getType());
445 static inline MachineOpCode
446 ChooseFcmpInstruction(const InstructionNode* instrNode)
448 MachineOpCode opCode = INVALID_OPCODE;
450 Value* operand = ((InstrTreeNode*) instrNode->leftChild())->getValue();
451 switch(operand->getType()->getPrimitiveID()) {
452 case Type::FloatTyID: opCode = FCMPS; break;
453 case Type::DoubleTyID: opCode = FCMPD; break;
454 default: assert(0 && "Invalid type for FCMP instruction"); break;
461 // Assumes that leftArg and rightArg are both cast instructions.
464 BothFloatToDouble(const InstructionNode* instrNode)
466 InstrTreeNode* leftArg = instrNode->leftChild();
467 InstrTreeNode* rightArg = instrNode->rightChild();
468 InstrTreeNode* leftArgArg = leftArg->leftChild();
469 InstrTreeNode* rightArgArg = rightArg->leftChild();
470 assert(leftArg->getValue()->getType() == rightArg->getValue()->getType());
472 // Check if both arguments are floats cast to double
473 return (leftArg->getValue()->getType() == Type::DoubleTy &&
474 leftArgArg->getValue()->getType() == Type::FloatTy &&
475 rightArgArg->getValue()->getType() == Type::FloatTy);
479 static inline MachineOpCode
480 ChooseMulInstructionByType(const Type* resultType)
482 MachineOpCode opCode = INVALID_OPCODE;
484 if (resultType->isInteger())
487 switch(resultType->getPrimitiveID())
489 case Type::FloatTyID: opCode = FMULS; break;
490 case Type::DoubleTyID: opCode = FMULD; break;
491 default: assert(0 && "Invalid type for MUL instruction"); break;
499 static inline MachineInstr*
500 CreateIntNegInstruction(const TargetMachine& target,
503 MachineInstr* minstr = new MachineInstr(SUB);
504 minstr->SetMachineOperandReg(0, target.getRegInfo().getZeroRegNum());
505 minstr->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister, vreg);
506 minstr->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister, vreg);
511 // Create instruction sequence for any shift operation.
512 // SLL or SLLX on an operand smaller than the integer reg. size (64bits)
513 // requires a second instruction for explicit sign-extension.
514 // Note that we only have to worry about a sign-bit appearing in the
515 // most significant bit of the operand after shifting (e.g., bit 32 of
516 // Int or bit 16 of Short), so we do not have to worry about results
517 // that are as large as a normal integer register.
520 CreateShiftInstructions(const TargetMachine& target,
522 MachineOpCode shiftOpCode,
524 Value* optArgVal2, /* Use optArgVal2 if not NULL */
525 unsigned int optShiftNum, /* else use optShiftNum */
526 Instruction* destVal,
527 vector<MachineInstr*>& mvec,
528 MachineCodeForInstruction& mcfi)
530 assert((optArgVal2 != NULL || optShiftNum <= 64) &&
531 "Large shift sizes unexpected, but can be handled below: "
532 "You need to check whether or not it fits in immed field below");
534 // If this is a logical left shift of a type smaller than the standard
535 // integer reg. size, we have to extend the sign-bit into upper bits
536 // of dest, so we need to put the result of the SLL into a temporary.
538 Value* shiftDest = destVal;
539 unsigned opSize = target.DataLayout.getTypeSize(argVal1->getType());
540 if ((shiftOpCode == SLL || shiftOpCode == SLLX)
541 && opSize < target.DataLayout.getIntegerRegize())
542 { // put SLL result into a temporary
543 shiftDest = new TmpInstruction(argVal1, optArgVal2, "sllTmp");
544 mcfi.addTemp(shiftDest);
547 MachineInstr* M = (optArgVal2 != NULL)
548 ? Create3OperandInstr(shiftOpCode, argVal1, optArgVal2, shiftDest)
549 : Create3OperandInstr_UImmed(shiftOpCode, argVal1, optShiftNum, shiftDest);
552 if (shiftDest != destVal)
553 { // extend the sign-bit of the result into all upper bits of dest
554 assert(8*opSize <= 32 && "Unexpected type size > 4 and < IntRegSize?");
555 target.getInstrInfo().
556 CreateSignExtensionInstructions(target, F, shiftDest, destVal,
557 8*opSize, mvec, mcfi);
562 // Does not create any instructions if we cannot exploit constant to
563 // create a cheaper instruction.
564 // This returns the approximate cost of the instructions generated,
565 // which is used to pick the cheapest when both operands are constant.
566 static inline unsigned int
567 CreateMulConstInstruction(const TargetMachine &target, Function* F,
568 Value* lval, Value* rval, Instruction* destVal,
569 vector<MachineInstr*>& mvec,
570 MachineCodeForInstruction& mcfi)
572 /* Use max. multiply cost, viz., cost of MULX */
573 unsigned int cost = target.getInstrInfo().minLatency(MULX);
574 unsigned int firstNewInstr = mvec.size();
576 Value* constOp = rval;
577 if (! isa<Constant>(constOp))
580 // Cases worth optimizing are:
581 // (1) Multiply by 0 or 1 for any type: replace with copy (ADD or FMOV)
582 // (2) Multiply by 2^x for integer types: replace with Shift
584 const Type* resultType = destVal->getType();
586 if (resultType->isInteger() || isa<PointerType>(resultType))
589 int64_t C = GetConstantValueAsSignedInt(constOp, isValidConst);
593 bool needNeg = false;
600 if (C == 0 || C == 1)
602 cost = target.getInstrInfo().minLatency(ADD);
603 MachineInstr* M = (C == 0)
604 ? Create3OperandInstr_Reg(ADD,
605 target.getRegInfo().getZeroRegNum(),
606 target.getRegInfo().getZeroRegNum(),
608 : Create3OperandInstr_Reg(ADD, lval,
609 target.getRegInfo().getZeroRegNum(),
613 else if (isPowerOf2(C, pow))
615 unsigned int opSize = target.DataLayout.getTypeSize(resultType);
616 MachineOpCode opCode = (opSize <= 32)? SLL : SLLX;
617 CreateShiftInstructions(target, F, opCode, lval, NULL, pow,
618 destVal, mvec, mcfi);
621 if (mvec.size() > 0 && needNeg)
622 { // insert <reg = SUB 0, reg> after the instr to flip the sign
623 MachineInstr* M = CreateIntNegInstruction(target, destVal);
630 if (ConstantFP *FPC = dyn_cast<ConstantFP>(constOp))
632 double dval = FPC->getValue();
635 MachineOpCode opCode = (dval < 0)
636 ? (resultType == Type::FloatTy? FNEGS : FNEGD)
637 : (resultType == Type::FloatTy? FMOVS : FMOVD);
638 MachineInstr* M = Create2OperandInstr(opCode, lval, destVal);
644 if (firstNewInstr < mvec.size())
647 for (unsigned int i=firstNewInstr; i < mvec.size(); ++i)
648 cost += target.getInstrInfo().minLatency(mvec[i]->getOpCode());
655 // Does not create any instructions if we cannot exploit constant to
656 // create a cheaper instruction.
659 CreateCheapestMulConstInstruction(const TargetMachine &target,
661 Value* lval, Value* rval,
662 Instruction* destVal,
663 vector<MachineInstr*>& mvec,
664 MachineCodeForInstruction& mcfi)
667 if (isa<Constant>(lval) && isa<Constant>(rval))
668 { // both operands are constant: evaluate and "set" in dest
669 Constant* P = ConstantFoldBinaryInstruction(Instruction::Mul,
670 cast<Constant>(lval), cast<Constant>(rval));
671 target.getInstrInfo().CreateCodeToLoadConst(target,F,P,destVal,mvec,mcfi);
673 else if (isa<Constant>(rval)) // rval is constant, but not lval
674 CreateMulConstInstruction(target, F, lval, rval, destVal, mvec, mcfi);
675 else if (isa<Constant>(lval)) // lval is constant, but not rval
676 CreateMulConstInstruction(target, F, lval, rval, destVal, mvec, mcfi);
678 // else neither is constant
682 // Return NULL if we cannot exploit constant to create a cheaper instruction
684 CreateMulInstruction(const TargetMachine &target, Function* F,
685 Value* lval, Value* rval, Instruction* destVal,
686 vector<MachineInstr*>& mvec,
687 MachineCodeForInstruction& mcfi,
688 MachineOpCode forceMulOp = INVALID_MACHINE_OPCODE)
690 unsigned int L = mvec.size();
691 CreateCheapestMulConstInstruction(target,F, lval, rval, destVal, mvec, mcfi);
692 if (mvec.size() == L)
693 { // no instructions were added so create MUL reg, reg, reg.
694 // Use FSMULD if both operands are actually floats cast to doubles.
695 // Otherwise, use the default opcode for the appropriate type.
696 MachineOpCode mulOp = ((forceMulOp != INVALID_MACHINE_OPCODE)
698 : ChooseMulInstructionByType(destVal->getType()));
699 MachineInstr* M = new MachineInstr(mulOp);
700 M->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister, lval);
701 M->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister, rval);
702 M->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister, destVal);
708 // Generate a divide instruction for Div or Rem.
709 // For Rem, this assumes that the operand type will be signed if the result
710 // type is signed. This is correct because they must have the same sign.
712 static inline MachineOpCode
713 ChooseDivInstruction(TargetMachine &target,
714 const InstructionNode* instrNode)
716 MachineOpCode opCode = INVALID_OPCODE;
718 const Type* resultType = instrNode->getInstruction()->getType();
720 if (resultType->isInteger())
721 opCode = resultType->isSigned()? SDIVX : UDIVX;
723 switch(resultType->getPrimitiveID())
725 case Type::FloatTyID: opCode = FDIVS; break;
726 case Type::DoubleTyID: opCode = FDIVD; break;
727 default: assert(0 && "Invalid type for DIV instruction"); break;
734 // Return NULL if we cannot exploit constant to create a cheaper instruction
736 CreateDivConstInstruction(TargetMachine &target,
737 const InstructionNode* instrNode,
738 vector<MachineInstr*>& mvec)
740 MachineInstr* minstr1 = NULL;
741 MachineInstr* minstr2 = NULL;
743 Value* constOp = ((InstrTreeNode*) instrNode->rightChild())->getValue();
744 if (! isa<Constant>(constOp))
747 // Cases worth optimizing are:
748 // (1) Divide by 1 for any type: replace with copy (ADD or FMOV)
749 // (2) Divide by 2^x for integer types: replace with SR[L or A]{X}
751 const Type* resultType = instrNode->getInstruction()->getType();
753 if (resultType->isInteger())
757 int64_t C = GetConstantValueAsSignedInt(constOp, isValidConst);
760 bool needNeg = false;
769 minstr1 = new MachineInstr(ADD);
770 minstr1->SetMachineOperandVal(0,
771 MachineOperand::MO_VirtualRegister,
772 instrNode->leftChild()->getValue());
773 minstr1->SetMachineOperandReg(1,
774 target.getRegInfo().getZeroRegNum());
776 else if (isPowerOf2(C, pow))
778 MachineOpCode opCode= ((resultType->isSigned())
779 ? (resultType==Type::LongTy)? SRAX : SRA
780 : (resultType==Type::LongTy)? SRLX : SRL);
781 minstr1 = new MachineInstr(opCode);
782 minstr1->SetMachineOperandVal(0,
783 MachineOperand::MO_VirtualRegister,
784 instrNode->leftChild()->getValue());
785 minstr1->SetMachineOperandConst(1,
786 MachineOperand::MO_UnextendedImmed,
790 if (minstr1 && needNeg)
791 { // insert <reg = SUB 0, reg> after the instr to flip the sign
792 minstr2 = CreateIntNegInstruction(target,
793 instrNode->getValue());
799 if (ConstantFP *FPC = dyn_cast<ConstantFP>(constOp))
801 double dval = FPC->getValue();
804 bool needNeg = (dval < 0);
806 MachineOpCode opCode = needNeg
807 ? (resultType == Type::FloatTy? FNEGS : FNEGD)
808 : (resultType == Type::FloatTy? FMOVS : FMOVD);
810 minstr1 = new MachineInstr(opCode);
811 minstr1->SetMachineOperandVal(0,
812 MachineOperand::MO_VirtualRegister,
813 instrNode->leftChild()->getValue());
819 minstr1->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister,
820 instrNode->getValue());
823 mvec.push_back(minstr1);
825 mvec.push_back(minstr2);
830 CreateCodeForVariableSizeAlloca(const TargetMachine& target,
833 Value* numElementsVal,
834 vector<MachineInstr*>& getMvec)
837 MachineCodeForInstruction& mcfi = MachineCodeForInstruction::get(result);
839 // Create a Value to hold the (constant) element size
840 Value* tsizeVal = ConstantSInt::get(Type::IntTy, tsize);
842 // Get the constant offset from SP for dynamically allocated storage
843 // and create a temporary Value to hold it.
844 assert(result && result->getParent() && "Result value is not part of a fn?");
845 Function *F = result->getParent()->getParent();
846 MachineCodeForMethod& mcInfo = MachineCodeForMethod::get(F);
848 ConstantSInt* dynamicAreaOffset =
849 ConstantSInt::get(Type::IntTy,
850 target.getFrameInfo().getDynamicAreaOffset(mcInfo,growUp));
851 assert(! growUp && "Has SPARC v9 stack frame convention changed?");
853 // Create a temporary value to hold the result of MUL
854 TmpInstruction* tmpProd = new TmpInstruction(numElementsVal, tsizeVal);
855 mcfi.addTemp(tmpProd);
857 // Instruction 1: mul numElements, typeSize -> tmpProd
858 CreateMulInstruction(target, F, numElementsVal, tsizeVal, tmpProd, getMvec,
859 mcfi, INVALID_MACHINE_OPCODE);
861 // Instruction 2: sub %sp, tmpProd -> %sp
862 M = new MachineInstr(SUB);
863 M->SetMachineOperandReg(0, target.getRegInfo().getStackPointer());
864 M->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister, tmpProd);
865 M->SetMachineOperandReg(2, target.getRegInfo().getStackPointer());
866 getMvec.push_back(M);
868 // Instruction 3: add %sp, frameSizeBelowDynamicArea -> result
869 M = new MachineInstr(ADD);
870 M->SetMachineOperandReg(0, target.getRegInfo().getStackPointer());
871 M->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister, dynamicAreaOffset);
872 M->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister, result);
873 getMvec.push_back(M);
878 CreateCodeForFixedSizeAlloca(const TargetMachine& target,
881 unsigned int numElements,
882 vector<MachineInstr*>& getMvec)
884 assert(tsize > 0 && "Illegal (zero) type size for alloca");
885 assert(result && result->getParent() &&
886 "Result value is not part of a function?");
887 Function *F = result->getParent()->getParent();
888 MachineCodeForMethod &mcInfo = MachineCodeForMethod::get(F);
890 // Check if the offset would small enough to use as an immediate in
891 // load/stores (check LDX because all load/stores have the same-size immediate
892 // field). If not, put the variable in the dynamically sized area of the
894 unsigned int paddedSizeIgnored;
895 int offsetFromFP = mcInfo.computeOffsetforLocalVar(target, result,
897 tsize * numElements);
898 if (! target.getInstrInfo().constantFitsInImmedField(LDX, offsetFromFP))
900 CreateCodeForVariableSizeAlloca(target, result, tsize,
901 ConstantSInt::get(Type::IntTy,numElements),
906 // else offset fits in immediate field so go ahead and allocate it.
907 offsetFromFP = mcInfo.allocateLocalVar(target, result, tsize * numElements);
909 // Create a temporary Value to hold the constant offset.
910 // This is needed because it may not fit in the immediate field.
911 ConstantSInt* offsetVal = ConstantSInt::get(Type::IntTy, offsetFromFP);
913 // Instruction 1: add %fp, offsetFromFP -> result
914 MachineInstr* M = new MachineInstr(ADD);
915 M->SetMachineOperandReg(0, target.getRegInfo().getFramePointer());
916 M->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister, offsetVal);
917 M->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister, result);
919 getMvec.push_back(M);
923 //------------------------------------------------------------------------
924 // Function SetOperandsForMemInstr
926 // Choose addressing mode for the given load or store instruction.
927 // Use [reg+reg] if it is an indexed reference, and the index offset is
928 // not a constant or if it cannot fit in the offset field.
929 // Use [reg+offset] in all other cases.
931 // This assumes that all array refs are "lowered" to one of these forms:
932 // %x = load (subarray*) ptr, constant ; single constant offset
933 // %x = load (subarray*) ptr, offsetVal ; single non-constant offset
934 // Generally, this should happen via strength reduction + LICM.
935 // Also, strength reduction should take care of using the same register for
936 // the loop index variable and an array index, when that is profitable.
937 //------------------------------------------------------------------------
940 SetOperandsForMemInstr(vector<MachineInstr*>& mvec,
941 InstructionNode* vmInstrNode,
942 const TargetMachine& target)
944 Instruction* memInst = vmInstrNode->getInstruction();
945 vector<MachineInstr*>::iterator mvecI = mvec.end() - 1;
947 // Index vector, ptr value, and flag if all indices are const.
948 vector<Value*> idxVec;
949 bool allConstantIndices;
950 Value* ptrVal = GetMemInstArgs(vmInstrNode, idxVec, allConstantIndices);
952 // Now create the appropriate operands for the machine instruction.
953 // First, initialize so we default to storing the offset in a register.
954 int64_t smallConstOffset = 0;
955 Value* valueForRegOffset = NULL;
956 MachineOperand::MachineOperandType offsetOpType =
957 MachineOperand::MO_VirtualRegister;
959 // Check if there is an index vector and if so, compute the
960 // right offset for structures and for arrays
964 const PointerType* ptrType = cast<PointerType>(ptrVal->getType());
966 // If all indices are constant, compute the combined offset directly.
967 if (allConstantIndices)
969 // Compute the offset value using the index vector. Create a
970 // virtual reg. for it since it may not fit in the immed field.
971 uint64_t offset = target.DataLayout.getIndexedOffset(ptrType,idxVec);
972 valueForRegOffset = ConstantSInt::get(Type::LongTy, offset);
976 // There is at least one non-constant offset. Therefore, this must
977 // be an array ref, and must have been lowered to a single non-zero
978 // offset. (An extra leading zero offset, if any, can be ignored.)
979 // Generate code sequence to compute address from index.
981 bool firstIdxIsZero =
982 (idxVec[0] == Constant::getNullValue(idxVec[0]->getType()));
983 assert(idxVec.size() == 1U + firstIdxIsZero
984 && "Array refs must be lowered before Instruction Selection");
986 Value* idxVal = idxVec[firstIdxIsZero];
988 vector<MachineInstr*> mulVec;
989 Instruction* addr = new TmpInstruction(Type::ULongTy, memInst);
990 MachineCodeForInstruction::get(memInst).addTemp(addr);
992 // Get the array type indexed by idxVal, and compute its element size.
993 // The call to getTypeSize() will fail if size is not constant.
994 const Type* vecType = (firstIdxIsZero
995 ? GetElementPtrInst::getIndexedType(ptrType,
996 std::vector<Value*>(1U, idxVec[0]),
997 /*AllowCompositeLeaf*/ true)
999 const Type* eltType = cast<SequentialType>(vecType)->getElementType();
1000 ConstantUInt* eltSizeVal = ConstantUInt::get(Type::ULongTy,
1001 target.DataLayout.getTypeSize(eltType));
1003 // CreateMulInstruction() folds constants intelligently enough.
1004 CreateMulInstruction(target, memInst->getParent()->getParent(),
1005 idxVal, /* lval, not likely to be const*/
1006 eltSizeVal, /* rval, likely to be constant */
1008 mulVec, MachineCodeForInstruction::get(memInst),
1009 INVALID_MACHINE_OPCODE);
1011 // Insert mulVec[] before *mvecI in mvec[] and update mvecI
1012 // to point to the same instruction it pointed to before.
1013 assert(mulVec.size() > 0 && "No multiply code created?");
1014 vector<MachineInstr*>::iterator oldMvecI = mvecI;
1015 for (unsigned i=0, N=mulVec.size(); i < N; ++i)
1016 mvecI = mvec.insert(mvecI, mulVec[i]) + 1; // pts to mem instr
1018 valueForRegOffset = addr;
1023 offsetOpType = MachineOperand::MO_SignExtendedImmed;
1024 smallConstOffset = 0;
1028 // Operand 0 is value, operand 1 is ptr, operand 2 is offset
1029 // For LOAD or GET_ELEMENT_PTR,
1030 // Operand 0 is ptr, operand 1 is offset, operand 2 is result.
1032 unsigned offsetOpNum, ptrOpNum;
1033 if (memInst->getOpcode() == Instruction::Store)
1035 (*mvecI)->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister,
1036 vmInstrNode->leftChild()->getValue());
1044 (*mvecI)->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister,
1048 (*mvecI)->SetMachineOperandVal(ptrOpNum, MachineOperand::MO_VirtualRegister,
1051 if (offsetOpType == MachineOperand::MO_VirtualRegister)
1053 assert(valueForRegOffset != NULL);
1054 (*mvecI)->SetMachineOperandVal(offsetOpNum, offsetOpType,
1058 (*mvecI)->SetMachineOperandConst(offsetOpNum, offsetOpType,
1064 // Substitute operand `operandNum' of the instruction in node `treeNode'
1065 // in place of the use(s) of that instruction in node `parent'.
1066 // Check both explicit and implicit operands!
1067 // Also make sure to skip over a parent who:
1068 // (1) is a list node in the Burg tree, or
1069 // (2) itself had its results forwarded to its parent
1072 ForwardOperand(InstructionNode* treeNode,
1073 InstrTreeNode* parent,
1076 assert(treeNode && parent && "Invalid invocation of ForwardOperand");
1078 Instruction* unusedOp = treeNode->getInstruction();
1079 Value* fwdOp = unusedOp->getOperand(operandNum);
1081 // The parent itself may be a list node, so find the real parent instruction
1082 while (parent->getNodeType() != InstrTreeNode::NTInstructionNode)
1084 parent = parent->parent();
1085 assert(parent && "ERROR: Non-instruction node has no parent in tree.");
1087 InstructionNode* parentInstrNode = (InstructionNode*) parent;
1089 Instruction* userInstr = parentInstrNode->getInstruction();
1090 MachineCodeForInstruction &mvec = MachineCodeForInstruction::get(userInstr);
1092 // The parent's mvec would be empty if it was itself forwarded.
1093 // Recursively call ForwardOperand in that case...
1095 if (mvec.size() == 0)
1097 assert(parent->parent() != NULL &&
1098 "Parent could not have been forwarded, yet has no instructions?");
1099 ForwardOperand(treeNode, parent->parent(), operandNum);
1103 for (unsigned i=0, N=mvec.size(); i < N; i++)
1105 MachineInstr* minstr = mvec[i];
1106 for (unsigned i=0, numOps=minstr->getNumOperands(); i < numOps; ++i)
1108 const MachineOperand& mop = minstr->getOperand(i);
1109 if (mop.getOperandType() == MachineOperand::MO_VirtualRegister &&
1110 mop.getVRegValue() == unusedOp)
1111 minstr->SetMachineOperandVal(i,
1112 MachineOperand::MO_VirtualRegister, fwdOp);
1115 for (unsigned i=0,numOps=minstr->getNumImplicitRefs(); i<numOps; ++i)
1116 if (minstr->getImplicitRef(i) == unusedOp)
1117 minstr->setImplicitRef(i, fwdOp,
1118 minstr->implicitRefIsDefined(i),
1119 minstr->implicitRefIsDefinedAndUsed(i));
1126 AllUsesAreBranches(const Instruction* setccI)
1128 for (Value::use_const_iterator UI=setccI->use_begin(), UE=setccI->use_end();
1130 if (! isa<TmpInstruction>(*UI) // ignore tmp instructions here
1131 && cast<Instruction>(*UI)->getOpcode() != Instruction::Br)
1136 //******************* Externally Visible Functions *************************/
1138 //------------------------------------------------------------------------
1139 // External Function: ThisIsAChainRule
1142 // Check if a given BURG rule is a chain rule.
1143 //------------------------------------------------------------------------
1146 ThisIsAChainRule(int eruleno)
1150 case 111: // stmt: reg
1174 return false; break;
1179 //------------------------------------------------------------------------
1180 // External Function: GetInstructionsByRule
1183 // Choose machine instructions for the SPARC according to the
1184 // patterns chosen by the BURG-generated parser.
1185 //------------------------------------------------------------------------
1188 GetInstructionsByRule(InstructionNode* subtreeRoot,
1191 TargetMachine &target,
1192 vector<MachineInstr*>& mvec)
1194 bool checkCast = false; // initialize here to use fall-through
1195 bool maskUnsignedResult = false;
1197 int forwardOperandNum = -1;
1198 unsigned int allocaSize = 0;
1199 MachineInstr* M, *M2;
1204 // If the code for this instruction was folded into the parent (user),
1206 if (subtreeRoot->isFoldedIntoParent())
1210 // Let's check for chain rules outside the switch so that we don't have
1211 // to duplicate the list of chain rule production numbers here again
1213 if (ThisIsAChainRule(ruleForNode))
1215 // Chain rules have a single nonterminal on the RHS.
1216 // Get the rule that matches the RHS non-terminal and use that instead.
1218 assert(nts[0] && ! nts[1]
1219 && "A chain rule should have only one RHS non-terminal!");
1220 nextRule = burm_rule(subtreeRoot->state, nts[0]);
1221 nts = burm_nts[nextRule];
1222 GetInstructionsByRule(subtreeRoot, nextRule, nts, target, mvec);
1226 switch(ruleForNode) {
1227 case 1: // stmt: Ret
1228 case 2: // stmt: RetValue(reg)
1229 { // NOTE: Prepass of register allocation is responsible
1230 // for moving return value to appropriate register.
1231 // Mark the return-address register as a hidden virtual reg.
1232 // Mark the return value register as an implicit ref of
1233 // the machine instruction.
1234 // Finally put a NOP in the delay slot.
1235 ReturnInst *returnInstr =
1236 cast<ReturnInst>(subtreeRoot->getInstruction());
1237 assert(returnInstr->getOpcode() == Instruction::Ret);
1239 Instruction* returnReg = new TmpInstruction(returnInstr);
1240 MachineCodeForInstruction::get(returnInstr).addTemp(returnReg);
1242 M = new MachineInstr(JMPLRET);
1243 M->SetMachineOperandReg(0, MachineOperand::MO_VirtualRegister,
1245 M->SetMachineOperandConst(1,MachineOperand::MO_SignExtendedImmed,
1247 M->SetMachineOperandReg(2, target.getRegInfo().getZeroRegNum());
1249 if (returnInstr->getReturnValue() != NULL)
1250 M->addImplicitRef(returnInstr->getReturnValue());
1253 mvec.push_back(new MachineInstr(NOP));
1258 case 3: // stmt: Store(reg,reg)
1259 case 4: // stmt: Store(reg,ptrreg)
1260 mvec.push_back(new MachineInstr(
1261 ChooseStoreInstruction(
1262 subtreeRoot->leftChild()->getValue()->getType())));
1263 SetOperandsForMemInstr(mvec, subtreeRoot, target);
1266 case 5: // stmt: BrUncond
1267 M = new MachineInstr(BA);
1268 M->SetMachineOperandVal(0, MachineOperand::MO_PCRelativeDisp,
1269 cast<BranchInst>(subtreeRoot->getInstruction())->getSuccessor(0));
1273 mvec.push_back(new MachineInstr(NOP));
1276 case 206: // stmt: BrCond(setCCconst)
1277 { // setCCconst => boolean was computed with `%b = setCC type reg1 const'
1278 // If the constant is ZERO, we can use the branch-on-integer-register
1279 // instructions and avoid the SUBcc instruction entirely.
1280 // Otherwise this is just the same as case 5, so just fall through.
1282 InstrTreeNode* constNode = subtreeRoot->leftChild()->rightChild();
1284 constNode->getNodeType() ==InstrTreeNode::NTConstNode);
1285 Constant *constVal = cast<Constant>(constNode->getValue());
1288 if ((constVal->getType()->isInteger()
1289 || isa<PointerType>(constVal->getType()))
1290 && GetConstantValueAsSignedInt(constVal, isValidConst) == 0
1293 // That constant is a zero after all...
1294 // Use the left child of setCC as the first argument!
1295 // Mark the setCC node so that no code is generated for it.
1296 InstructionNode* setCCNode = (InstructionNode*)
1297 subtreeRoot->leftChild();
1298 assert(setCCNode->getOpLabel() == SetCCOp);
1299 setCCNode->markFoldedIntoParent();
1301 BranchInst* brInst=cast<BranchInst>(subtreeRoot->getInstruction());
1303 M = new MachineInstr(ChooseBprInstruction(subtreeRoot));
1304 M->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister,
1305 setCCNode->leftChild()->getValue());
1306 M->SetMachineOperandVal(1, MachineOperand::MO_PCRelativeDisp,
1307 brInst->getSuccessor(0));
1311 mvec.push_back(new MachineInstr(NOP));
1314 M = new MachineInstr(BA);
1315 M->SetMachineOperandVal(0, MachineOperand::MO_PCRelativeDisp,
1316 brInst->getSuccessor(1));
1320 mvec.push_back(new MachineInstr(NOP));
1324 // ELSE FALL THROUGH
1327 case 6: // stmt: BrCond(setCC)
1328 { // bool => boolean was computed with SetCC.
1329 // The branch to use depends on whether it is FP, signed, or unsigned.
1330 // If it is an integer CC, we also need to find the unique
1331 // TmpInstruction representing that CC.
1333 BranchInst* brInst = cast<BranchInst>(subtreeRoot->getInstruction());
1335 M = new MachineInstr(ChooseBccInstruction(subtreeRoot, isFPBranch));
1337 Value* ccValue = GetTmpForCC(subtreeRoot->leftChild()->getValue(),
1338 brInst->getParent()->getParent(),
1339 isFPBranch? Type::FloatTy : Type::IntTy);
1341 M->SetMachineOperandVal(0, MachineOperand::MO_CCRegister, ccValue);
1342 M->SetMachineOperandVal(1, MachineOperand::MO_PCRelativeDisp,
1343 brInst->getSuccessor(0));
1347 mvec.push_back(new MachineInstr(NOP));
1350 M = new MachineInstr(BA);
1351 M->SetMachineOperandVal(0, MachineOperand::MO_PCRelativeDisp,
1352 brInst->getSuccessor(1));
1356 mvec.push_back(new MachineInstr(NOP));
1360 case 208: // stmt: BrCond(boolconst)
1362 // boolconst => boolean is a constant; use BA to first or second label
1363 Constant* constVal =
1364 cast<Constant>(subtreeRoot->leftChild()->getValue());
1365 unsigned dest = cast<ConstantBool>(constVal)->getValue()? 0 : 1;
1367 M = new MachineInstr(BA);
1368 M->SetMachineOperandVal(0, MachineOperand::MO_PCRelativeDisp,
1369 cast<BranchInst>(subtreeRoot->getInstruction())->getSuccessor(dest));
1373 mvec.push_back(new MachineInstr(NOP));
1377 case 8: // stmt: BrCond(boolreg)
1378 { // boolreg => boolean is stored in an existing register.
1379 // Just use the branch-on-integer-register instruction!
1381 M = new MachineInstr(BRNZ);
1382 M->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister,
1383 subtreeRoot->leftChild()->getValue());
1384 M->SetMachineOperandVal(1, MachineOperand::MO_PCRelativeDisp,
1385 cast<BranchInst>(subtreeRoot->getInstruction())->getSuccessor(0));
1389 mvec.push_back(new MachineInstr(NOP));
1392 M = new MachineInstr(BA);
1393 M->SetMachineOperandVal(0, MachineOperand::MO_PCRelativeDisp,
1394 cast<BranchInst>(subtreeRoot->getInstruction())->getSuccessor(1));
1398 mvec.push_back(new MachineInstr(NOP));
1402 case 9: // stmt: Switch(reg)
1403 assert(0 && "*** SWITCH instruction is not implemented yet.");
1406 case 10: // reg: VRegList(reg, reg)
1407 assert(0 && "VRegList should never be the topmost non-chain rule");
1410 case 21: // bool: Not(bool,reg): Both these are implemented as:
1411 case 421: // reg: BNot(reg,reg): reg = reg XOR-NOT 0
1412 { // First find the unary operand. It may be left or right, usually right.
1413 Value* notArg = BinaryOperator::getNotArgument(
1414 cast<BinaryOperator>(subtreeRoot->getInstruction()));
1415 mvec.push_back(Create3OperandInstr_Reg(XNOR, notArg,
1416 target.getRegInfo().getZeroRegNum(),
1417 subtreeRoot->getValue()));
1421 case 22: // reg: ToBoolTy(reg):
1423 const Type* opType = subtreeRoot->leftChild()->getValue()->getType();
1424 assert(opType->isIntegral() || isa<PointerType>(opType));
1425 forwardOperandNum = 0; // forward first operand to user
1429 case 23: // reg: ToUByteTy(reg)
1430 case 24: // reg: ToSByteTy(reg)
1431 case 25: // reg: ToUShortTy(reg)
1432 case 26: // reg: ToShortTy(reg)
1433 case 27: // reg: ToUIntTy(reg)
1434 case 28: // reg: ToIntTy(reg)
1436 //======================================================================
1437 // Rules for integer conversions:
1440 // From ISO 1998 C++ Standard, Sec. 4.7:
1442 // 2. If the destination type is unsigned, the resulting value is
1443 // the least unsigned integer congruent to the source integer
1444 // (modulo 2n where n is the number of bits used to represent the
1445 // unsigned type). [Note: In a two s complement representation,
1446 // this conversion is conceptual and there is no change in the
1447 // bit pattern (if there is no truncation). ]
1449 // 3. If the destination type is signed, the value is unchanged if
1450 // it can be represented in the destination type (and bitfield width);
1451 // otherwise, the value is implementation-defined.
1454 // Since we assume 2s complement representations, this implies:
1456 // -- if operand is smaller than destination, zero-extend or sign-extend
1457 // according to the signedness of the *operand*: source decides.
1458 // ==> we have to do nothing here!
1460 // -- if operand is same size as or larger than destination, and the
1461 // destination is *unsigned*, zero-extend the operand: dest. decides
1463 // -- if operand is same size as or larger than destination, and the
1464 // destination is *signed*, the choice is implementation defined:
1465 // we sign-extend the operand: i.e., again dest. decides.
1466 // Note: this matches both Sun's cc and gcc3.2.
1467 //======================================================================
1469 Instruction* destI = subtreeRoot->getInstruction();
1470 Value* opVal = subtreeRoot->leftChild()->getValue();
1471 const Type* opType = opVal->getType();
1472 if (opType->isIntegral() || isa<PointerType>(opType))
1474 unsigned opSize = target.DataLayout.getTypeSize(opType);
1475 unsigned destSize = target.DataLayout.getTypeSize(destI->getType());
1476 if (opSize >= destSize)
1477 { // Operand is same size as or larger than dest:
1478 // zero- or sign-extend, according to the signeddness of
1479 // the destination (see above).
1480 if (destI->getType()->isSigned())
1481 target.getInstrInfo().CreateSignExtensionInstructions(target,
1482 destI->getParent()->getParent(), opVal, destI, 8*destSize,
1483 mvec, MachineCodeForInstruction::get(destI));
1485 target.getInstrInfo().CreateZeroExtensionInstructions(target,
1486 destI->getParent()->getParent(), opVal, destI, 8*destSize,
1487 mvec, MachineCodeForInstruction::get(destI));
1490 forwardOperandNum = 0; // forward first operand to user
1492 else if (opType->isFloatingPoint())
1494 CreateCodeToConvertFloatToInt(target, opVal, destI, mvec,
1495 MachineCodeForInstruction::get(destI));
1496 if (destI->getType()->isUnsigned())
1497 maskUnsignedResult = true; // not handled by fp->int code
1500 assert(0 && "Unrecognized operand type for convert-to-unsigned");
1505 case 29: // reg: ToULongTy(reg)
1506 case 30: // reg: ToLongTy(reg)
1508 Value* opVal = subtreeRoot->leftChild()->getValue();
1509 const Type* opType = opVal->getType();
1510 if (opType->isIntegral() || isa<PointerType>(opType))
1511 forwardOperandNum = 0; // forward first operand to user
1512 else if (opType->isFloatingPoint())
1514 Instruction* destI = subtreeRoot->getInstruction();
1515 CreateCodeToConvertFloatToInt(target, opVal, destI, mvec,
1516 MachineCodeForInstruction::get(destI));
1519 assert(0 && "Unrecognized operand type for convert-to-signed");
1523 case 31: // reg: ToFloatTy(reg):
1524 case 32: // reg: ToDoubleTy(reg):
1525 case 232: // reg: ToDoubleTy(Constant):
1527 // If this instruction has a parent (a user) in the tree
1528 // and the user is translated as an FsMULd instruction,
1529 // then the cast is unnecessary. So check that first.
1530 // In the future, we'll want to do the same for the FdMULq instruction,
1531 // so do the check here instead of only for ToFloatTy(reg).
1533 if (subtreeRoot->parent() != NULL)
1535 const MachineCodeForInstruction& mcfi =
1536 MachineCodeForInstruction::get(
1537 cast<InstructionNode>(subtreeRoot->parent())->getInstruction());
1538 if (mcfi.size() == 0 || mcfi.front()->getOpCode() == FSMULD)
1539 forwardOperandNum = 0; // forward first operand to user
1542 if (forwardOperandNum != 0) // we do need the cast
1544 Value* leftVal = subtreeRoot->leftChild()->getValue();
1545 const Type* opType = leftVal->getType();
1546 MachineOpCode opCode=ChooseConvertToFloatInstr(
1547 subtreeRoot->getOpLabel(), opType);
1548 if (opCode == INVALID_OPCODE) // no conversion needed
1550 forwardOperandNum = 0; // forward first operand to user
1554 // If the source operand is a non-FP type it must be
1555 // first copied from int to float register via memory!
1556 Instruction *dest = subtreeRoot->getInstruction();
1559 if (! opType->isFloatingPoint())
1561 // Create a temporary to represent the FP register
1562 // into which the integer will be copied via memory.
1563 // The type of this temporary will determine the FP
1564 // register used: single-prec for a 32-bit int or smaller,
1565 // double-prec for a 64-bit int.
1568 target.DataLayout.getTypeSize(leftVal->getType());
1569 Type* tmpTypeToUse =
1570 (srcSize <= 4)? Type::FloatTy : Type::DoubleTy;
1571 srcForCast = new TmpInstruction(tmpTypeToUse, dest);
1572 MachineCodeForInstruction &destMCFI =
1573 MachineCodeForInstruction::get(dest);
1574 destMCFI.addTemp(srcForCast);
1576 target.getInstrInfo().CreateCodeToCopyIntToFloat(target,
1577 dest->getParent()->getParent(),
1578 leftVal, cast<Instruction>(srcForCast),
1582 srcForCast = leftVal;
1584 M = new MachineInstr(opCode);
1585 M->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister,
1587 M->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister,
1594 case 19: // reg: ToArrayTy(reg):
1595 case 20: // reg: ToPointerTy(reg):
1596 forwardOperandNum = 0; // forward first operand to user
1599 case 233: // reg: Add(reg, Constant)
1600 maskUnsignedResult = true;
1601 M = CreateAddConstInstruction(subtreeRoot);
1607 // ELSE FALL THROUGH
1609 case 33: // reg: Add(reg, reg)
1610 maskUnsignedResult = true;
1611 mvec.push_back(new MachineInstr(ChooseAddInstruction(subtreeRoot)));
1612 Set3OperandsFromInstr(mvec.back(), subtreeRoot, target);
1615 case 234: // reg: Sub(reg, Constant)
1616 maskUnsignedResult = true;
1617 M = CreateSubConstInstruction(subtreeRoot);
1623 // ELSE FALL THROUGH
1625 case 34: // reg: Sub(reg, reg)
1626 maskUnsignedResult = true;
1627 mvec.push_back(new MachineInstr(ChooseSubInstructionByType(
1628 subtreeRoot->getInstruction()->getType())));
1629 Set3OperandsFromInstr(mvec.back(), subtreeRoot, target);
1632 case 135: // reg: Mul(todouble, todouble)
1636 case 35: // reg: Mul(reg, reg)
1638 maskUnsignedResult = true;
1639 MachineOpCode forceOp = ((checkCast && BothFloatToDouble(subtreeRoot))
1641 : INVALID_MACHINE_OPCODE);
1642 Instruction* mulInstr = subtreeRoot->getInstruction();
1643 CreateMulInstruction(target, mulInstr->getParent()->getParent(),
1644 subtreeRoot->leftChild()->getValue(),
1645 subtreeRoot->rightChild()->getValue(),
1647 MachineCodeForInstruction::get(mulInstr),forceOp);
1650 case 335: // reg: Mul(todouble, todoubleConst)
1654 case 235: // reg: Mul(reg, Constant)
1656 maskUnsignedResult = true;
1657 MachineOpCode forceOp = ((checkCast && BothFloatToDouble(subtreeRoot))
1659 : INVALID_MACHINE_OPCODE);
1660 Instruction* mulInstr = subtreeRoot->getInstruction();
1661 CreateMulInstruction(target, mulInstr->getParent()->getParent(),
1662 subtreeRoot->leftChild()->getValue(),
1663 subtreeRoot->rightChild()->getValue(),
1665 MachineCodeForInstruction::get(mulInstr),
1669 case 236: // reg: Div(reg, Constant)
1670 maskUnsignedResult = true;
1672 CreateDivConstInstruction(target, subtreeRoot, mvec);
1673 if (mvec.size() > L)
1675 // ELSE FALL THROUGH
1677 case 36: // reg: Div(reg, reg)
1678 maskUnsignedResult = true;
1679 mvec.push_back(new MachineInstr(ChooseDivInstruction(target, subtreeRoot)));
1680 Set3OperandsFromInstr(mvec.back(), subtreeRoot, target);
1683 case 37: // reg: Rem(reg, reg)
1684 case 237: // reg: Rem(reg, Constant)
1686 maskUnsignedResult = true;
1687 Instruction* remInstr = subtreeRoot->getInstruction();
1689 TmpInstruction* quot = new TmpInstruction(
1690 subtreeRoot->leftChild()->getValue(),
1691 subtreeRoot->rightChild()->getValue());
1692 TmpInstruction* prod = new TmpInstruction(
1694 subtreeRoot->rightChild()->getValue());
1695 MachineCodeForInstruction::get(remInstr).addTemp(quot).addTemp(prod);
1697 M = new MachineInstr(ChooseDivInstruction(target, subtreeRoot));
1698 Set3OperandsFromInstr(M, subtreeRoot, target);
1699 M->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister,quot);
1702 M = Create3OperandInstr(ChooseMulInstructionByType(
1703 subtreeRoot->getInstruction()->getType()),
1704 quot, subtreeRoot->rightChild()->getValue(),
1708 M = new MachineInstr(ChooseSubInstructionByType(
1709 subtreeRoot->getInstruction()->getType()));
1710 Set3OperandsFromInstr(M, subtreeRoot, target);
1711 M->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister,prod);
1717 case 38: // bool: And(bool, bool)
1718 case 238: // bool: And(bool, boolconst)
1719 case 338: // reg : BAnd(reg, reg)
1720 case 538: // reg : BAnd(reg, Constant)
1721 mvec.push_back(new MachineInstr(AND));
1722 Set3OperandsFromInstr(mvec.back(), subtreeRoot, target);
1725 case 138: // bool: And(bool, not)
1726 case 438: // bool: BAnd(bool, bnot)
1727 { // Use the argument of NOT as the second argument!
1728 // Mark the NOT node so that no code is generated for it.
1729 InstructionNode* notNode = (InstructionNode*) subtreeRoot->rightChild();
1730 Value* notArg = BinaryOperator::getNotArgument(
1731 cast<BinaryOperator>(notNode->getInstruction()));
1732 notNode->markFoldedIntoParent();
1733 mvec.push_back(Create3OperandInstr(ANDN,
1734 subtreeRoot->leftChild()->getValue(),
1735 notArg, subtreeRoot->getValue()));
1739 case 39: // bool: Or(bool, bool)
1740 case 239: // bool: Or(bool, boolconst)
1741 case 339: // reg : BOr(reg, reg)
1742 case 539: // reg : BOr(reg, Constant)
1743 mvec.push_back(new MachineInstr(OR));
1744 Set3OperandsFromInstr(mvec.back(), subtreeRoot, target);
1747 case 139: // bool: Or(bool, not)
1748 case 439: // bool: BOr(bool, bnot)
1749 { // Use the argument of NOT as the second argument!
1750 // Mark the NOT node so that no code is generated for it.
1751 InstructionNode* notNode = (InstructionNode*) subtreeRoot->rightChild();
1752 Value* notArg = BinaryOperator::getNotArgument(
1753 cast<BinaryOperator>(notNode->getInstruction()));
1754 notNode->markFoldedIntoParent();
1755 mvec.push_back(Create3OperandInstr(ORN,
1756 subtreeRoot->leftChild()->getValue(),
1757 notArg, subtreeRoot->getValue()));
1761 case 40: // bool: Xor(bool, bool)
1762 case 240: // bool: Xor(bool, boolconst)
1763 case 340: // reg : BXor(reg, reg)
1764 case 540: // reg : BXor(reg, Constant)
1765 mvec.push_back(new MachineInstr(XOR));
1766 Set3OperandsFromInstr(mvec.back(), subtreeRoot, target);
1769 case 140: // bool: Xor(bool, not)
1770 case 440: // bool: BXor(bool, bnot)
1771 { // Use the argument of NOT as the second argument!
1772 // Mark the NOT node so that no code is generated for it.
1773 InstructionNode* notNode = (InstructionNode*) subtreeRoot->rightChild();
1774 Value* notArg = BinaryOperator::getNotArgument(
1775 cast<BinaryOperator>(notNode->getInstruction()));
1776 notNode->markFoldedIntoParent();
1777 mvec.push_back(Create3OperandInstr(XNOR,
1778 subtreeRoot->leftChild()->getValue(),
1779 notArg, subtreeRoot->getValue()));
1783 case 41: // boolconst: SetCC(reg, Constant)
1785 // If the SetCC was folded into the user (parent), it will be
1786 // caught above. All other cases are the same as case 42,
1787 // so just fall through.
1789 case 42: // bool: SetCC(reg, reg):
1791 // This generates a SUBCC instruction, putting the difference in
1792 // a result register, and setting a condition code.
1794 // If the boolean result of the SetCC is used by anything other
1795 // than a branch instruction, or if it is used outside the current
1796 // basic block, the boolean must be
1797 // computed and stored in the result register. Otherwise, discard
1798 // the difference (by using %g0) and keep only the condition code.
1800 // To compute the boolean result in a register we use a conditional
1801 // move, unless the result of the SUBCC instruction can be used as
1802 // the bool! This assumes that zero is FALSE and any non-zero
1805 InstructionNode* parentNode = (InstructionNode*) subtreeRoot->parent();
1806 Instruction* setCCInstr = subtreeRoot->getInstruction();
1808 bool keepBoolVal = parentNode == NULL ||
1809 ! AllUsesAreBranches(setCCInstr);
1810 bool subValIsBoolVal = setCCInstr->getOpcode() == Instruction::SetNE;
1811 bool keepSubVal = keepBoolVal && subValIsBoolVal;
1812 bool computeBoolVal = keepBoolVal && ! subValIsBoolVal;
1816 MachineOpCode movOpCode = 0;
1818 // Mark the 4th operand as being a CC register, and as a def
1819 // A TmpInstruction is created to represent the CC "result".
1820 // Unlike other instances of TmpInstruction, this one is used
1821 // by machine code of multiple LLVM instructions, viz.,
1822 // the SetCC and the branch. Make sure to get the same one!
1823 // Note that we do this even for FP CC registers even though they
1824 // are explicit operands, because the type of the operand
1825 // needs to be a floating point condition code, not an integer
1826 // condition code. Think of this as casting the bool result to
1827 // a FP condition code register.
1829 Value* leftVal = subtreeRoot->leftChild()->getValue();
1830 bool isFPCompare = leftVal->getType()->isFloatingPoint();
1832 TmpInstruction* tmpForCC = GetTmpForCC(setCCInstr,
1833 setCCInstr->getParent()->getParent(),
1834 isFPCompare ? Type::FloatTy : Type::IntTy);
1835 MachineCodeForInstruction::get(setCCInstr).addTemp(tmpForCC);
1839 // Integer condition: dest. should be %g0 or an integer register.
1840 // If result must be saved but condition is not SetEQ then we need
1841 // a separate instruction to compute the bool result, so discard
1842 // result of SUBcc instruction anyway.
1844 M = new MachineInstr(SUBcc);
1845 Set3OperandsFromInstr(M, subtreeRoot, target, ! keepSubVal);
1846 M->SetMachineOperandVal(3, MachineOperand::MO_CCRegister,
1847 tmpForCC, /*def*/true);
1851 { // recompute bool using the integer condition codes
1853 ChooseMovpccAfterSub(subtreeRoot,mustClearReg,valueToMove);
1858 // FP condition: dest of FCMP should be some FCCn register
1859 M = new MachineInstr(ChooseFcmpInstruction(subtreeRoot));
1860 M->SetMachineOperandVal(0, MachineOperand::MO_CCRegister,
1862 M->SetMachineOperandVal(1,MachineOperand::MO_VirtualRegister,
1863 subtreeRoot->leftChild()->getValue());
1864 M->SetMachineOperandVal(2,MachineOperand::MO_VirtualRegister,
1865 subtreeRoot->rightChild()->getValue());
1869 {// recompute bool using the FP condition codes
1870 mustClearReg = true;
1872 movOpCode = ChooseMovFpccInstruction(subtreeRoot);
1879 {// Unconditionally set register to 0
1880 M = new MachineInstr(SETHI);
1881 M->SetMachineOperandConst(0,MachineOperand::MO_UnextendedImmed,
1883 M->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister,
1888 // Now conditionally move `valueToMove' (0 or 1) into the register
1889 // Mark the register as a use (as well as a def) because the old
1890 // value should be retained if the condition is false.
1891 M = new MachineInstr(movOpCode);
1892 M->SetMachineOperandVal(0, MachineOperand::MO_CCRegister,
1894 M->SetMachineOperandConst(1, MachineOperand::MO_UnextendedImmed,
1896 M->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister,
1897 setCCInstr, /*isDef*/ true,
1898 /*isDefAndUse*/ true);
1904 case 51: // reg: Load(reg)
1905 case 52: // reg: Load(ptrreg)
1906 mvec.push_back(new MachineInstr(ChooseLoadInstruction(
1907 subtreeRoot->getValue()->getType())));
1908 SetOperandsForMemInstr(mvec, subtreeRoot, target);
1911 case 55: // reg: GetElemPtr(reg)
1912 case 56: // reg: GetElemPtrIdx(reg,reg)
1913 // If the GetElemPtr was folded into the user (parent), it will be
1914 // caught above. For other cases, we have to compute the address.
1915 mvec.push_back(new MachineInstr(ADD));
1916 SetOperandsForMemInstr(mvec, subtreeRoot, target);
1919 case 57: // reg: Alloca: Implement as 1 instruction:
1920 { // add %fp, offsetFromFP -> result
1921 AllocationInst* instr =
1922 cast<AllocationInst>(subtreeRoot->getInstruction());
1923 unsigned int tsize =
1924 target.DataLayout.getTypeSize(instr->getAllocatedType());
1926 CreateCodeForFixedSizeAlloca(target, instr, tsize, 1, mvec);
1930 case 58: // reg: Alloca(reg): Implement as 3 instructions:
1931 // mul num, typeSz -> tmp
1932 // sub %sp, tmp -> %sp
1933 { // add %sp, frameSizeBelowDynamicArea -> result
1934 AllocationInst* instr =
1935 cast<AllocationInst>(subtreeRoot->getInstruction());
1936 const Type* eltType = instr->getAllocatedType();
1938 // If #elements is constant, use simpler code for fixed-size allocas
1939 int tsize = (int) target.DataLayout.getTypeSize(eltType);
1940 Value* numElementsVal = NULL;
1941 bool isArray = instr->isArrayAllocation();
1944 isa<Constant>(numElementsVal = instr->getArraySize()))
1945 { // total size is constant: generate code for fixed-size alloca
1946 unsigned int numElements = isArray?
1947 cast<ConstantUInt>(numElementsVal)->getValue() : 1;
1948 CreateCodeForFixedSizeAlloca(target, instr, tsize,
1951 else // total size is not constant.
1952 CreateCodeForVariableSizeAlloca(target, instr, tsize,
1953 numElementsVal, mvec);
1957 case 61: // reg: Call
1958 { // Generate a direct (CALL) or indirect (JMPL) call.
1959 // Mark the return-address register, the indirection
1960 // register (for indirect calls), the operands of the Call,
1961 // and the return value (if any) as implicit operands
1962 // of the machine instruction.
1964 // If this is a varargs function, floating point arguments
1965 // have to passed in integer registers so insert
1966 // copy-float-to-int instructions for each float operand.
1968 CallInst *callInstr = cast<CallInst>(subtreeRoot->getInstruction());
1969 Value *callee = callInstr->getCalledValue();
1971 // Create hidden virtual register for return address with type void*
1972 TmpInstruction* retAddrReg =
1973 new TmpInstruction(PointerType::get(Type::VoidTy), callInstr);
1974 MachineCodeForInstruction::get(callInstr).addTemp(retAddrReg);
1976 // Generate the machine instruction and its operands.
1977 // Use CALL for direct function calls; this optimistically assumes
1978 // the PC-relative address fits in the CALL address field (22 bits).
1979 // Use JMPL for indirect calls.
1981 if (isa<Function>(callee)) // direct function call
1982 M = Create1OperandInstr_Addr(CALL, callee);
1983 else // indirect function call
1984 M = Create3OperandInstr_SImmed(JMPLCALL, callee,
1985 (int64_t) 0, retAddrReg);
1988 const FunctionType* funcType =
1989 cast<FunctionType>(cast<PointerType>(callee->getType())
1990 ->getElementType());
1991 bool isVarArgs = funcType->isVarArg();
1992 bool noPrototype = isVarArgs && funcType->getNumParams() == 0;
1994 // Use an annotation to pass information about call arguments
1995 // to the register allocator.
1996 CallArgsDescriptor* argDesc = new CallArgsDescriptor(callInstr,
1997 retAddrReg, isVarArgs, noPrototype);
1998 M->addAnnotation(argDesc);
2000 assert(callInstr->getOperand(0) == callee
2001 && "This is assumed in the loop below!");
2003 for (unsigned i=1, N=callInstr->getNumOperands(); i < N; ++i)
2005 Value* argVal = callInstr->getOperand(i);
2006 Instruction* intArgReg = NULL;
2008 // Check for FP arguments to varargs functions.
2009 // Any such argument in the first $K$ args must be passed in an
2010 // integer register, where K = #integer argument registers.
2011 if (isVarArgs && argVal->getType()->isFloatingPoint())
2013 // If it is a function with no prototype, pass value
2014 // as an FP value as well as a varargs value
2016 argDesc->getArgInfo(i-1).setUseFPArgReg();
2018 // If this arg. is in the first $K$ regs, add a copy
2019 // float-to-int instruction to pass the value as an integer.
2020 if (i <= target.getRegInfo().GetNumOfIntArgRegs())
2022 MachineCodeForInstruction &destMCFI =
2023 MachineCodeForInstruction::get(callInstr);
2024 intArgReg = new TmpInstruction(Type::IntTy, argVal);
2025 destMCFI.addTemp(intArgReg);
2027 vector<MachineInstr*> copyMvec;
2028 target.getInstrInfo().CreateCodeToCopyFloatToInt(target,
2029 callInstr->getParent()->getParent(),
2030 argVal, (TmpInstruction*) intArgReg,
2031 copyMvec, destMCFI);
2032 mvec.insert(mvec.begin(),copyMvec.begin(),copyMvec.end());
2034 argDesc->getArgInfo(i-1).setUseIntArgReg();
2035 argDesc->getArgInfo(i-1).setArgCopy(intArgReg);
2038 // Cannot fit in first $K$ regs so pass the arg on the stack
2039 argDesc->getArgInfo(i-1).setUseStackSlot();
2043 mvec.back()->addImplicitRef(intArgReg);
2045 mvec.back()->addImplicitRef(argVal);
2048 // Add the return value as an implicit ref. The call operands
2049 // were added above.
2050 if (callInstr->getType() != Type::VoidTy)
2051 mvec.back()->addImplicitRef(callInstr, /*isDef*/ true);
2053 // For the CALL instruction, the ret. addr. reg. is also implicit
2054 if (isa<Function>(callee))
2055 mvec.back()->addImplicitRef(retAddrReg, /*isDef*/ true);
2058 mvec.push_back(new MachineInstr(NOP));
2062 case 62: // reg: Shl(reg, reg)
2064 Value* argVal1 = subtreeRoot->leftChild()->getValue();
2065 Value* argVal2 = subtreeRoot->rightChild()->getValue();
2066 Instruction* shlInstr = subtreeRoot->getInstruction();
2068 const Type* opType = argVal1->getType();
2069 assert((opType->isInteger() || isa<PointerType>(opType)) &&
2070 "Shl unsupported for other types");
2072 CreateShiftInstructions(target, shlInstr->getParent()->getParent(),
2073 (opType == Type::LongTy)? SLLX : SLL,
2074 argVal1, argVal2, 0, shlInstr, mvec,
2075 MachineCodeForInstruction::get(shlInstr));
2079 case 63: // reg: Shr(reg, reg)
2080 { const Type* opType = subtreeRoot->leftChild()->getValue()->getType();
2081 assert((opType->isInteger() || isa<PointerType>(opType)) &&
2082 "Shr unsupported for other types");
2083 mvec.push_back(new MachineInstr((opType->isSigned()
2084 ? ((opType == Type::LongTy)? SRAX : SRA)
2085 : ((opType == Type::LongTy)? SRLX : SRL))));
2086 Set3OperandsFromInstr(mvec.back(), subtreeRoot, target);
2090 case 64: // reg: Phi(reg,reg)
2091 break; // don't forward the value
2093 case 71: // reg: VReg
2094 case 72: // reg: Constant
2095 break; // don't forward the value
2098 assert(0 && "Unrecognized BURG rule");
2103 if (forwardOperandNum >= 0)
2104 { // We did not generate a machine instruction but need to use operand.
2105 // If user is in the same tree, replace Value in its machine operand.
2106 // If not, insert a copy instruction which should get coalesced away
2107 // by register allocation.
2108 if (subtreeRoot->parent() != NULL)
2109 ForwardOperand(subtreeRoot, subtreeRoot->parent(), forwardOperandNum);
2112 vector<MachineInstr*> minstrVec;
2113 Instruction* instr = subtreeRoot->getInstruction();
2114 target.getInstrInfo().
2115 CreateCopyInstructionsByType(target,
2116 instr->getParent()->getParent(),
2117 instr->getOperand(forwardOperandNum),
2119 MachineCodeForInstruction::get(instr));
2120 assert(minstrVec.size() > 0);
2121 mvec.insert(mvec.end(), minstrVec.begin(), minstrVec.end());
2125 if (maskUnsignedResult)
2126 { // If result is unsigned and smaller than int reg size,
2127 // we need to clear high bits of result value.
2128 assert(forwardOperandNum < 0 && "Need mask but no instruction generated");
2129 Instruction* dest = subtreeRoot->getInstruction();
2130 if (dest->getType()->isUnsigned())
2132 unsigned destSize = target.DataLayout.getTypeSize(dest->getType());
2134 { // Mask high bits. Use a TmpInstruction to represent the
2135 // intermediate result before masking. Since those instructions
2136 // have already been generated, go back and substitute tmpI
2137 // for dest in the result position of each one of them.
2138 TmpInstruction *tmpI = new TmpInstruction(dest->getType(), dest,
2140 MachineCodeForInstruction::get(dest).addTemp(tmpI);
2142 for (unsigned i=0, N=mvec.size(); i < N; ++i)
2143 mvec[i]->substituteValue(dest, tmpI);
2145 M = Create3OperandInstr_UImmed(SRL, tmpI, 8*(4-destSize), dest);
2148 else if (destSize < target.DataLayout.getIntegerRegize())
2149 assert(0 && "Unsupported type size: 32 < size < 64 bits");