2 //***************************************************************************
4 // SparcInstrSelection.cpp
7 // BURS instruction selection for SPARC V9 architecture.
10 // 7/02/01 - Vikram Adve - Created
11 //**************************************************************************/
13 #include "SparcInternals.h"
14 #include "SparcInstrSelectionSupport.h"
15 #include "SparcRegClassInfo.h"
16 #include "llvm/CodeGen/InstrSelectionSupport.h"
17 #include "llvm/CodeGen/MachineInstr.h"
18 #include "llvm/CodeGen/InstrForest.h"
19 #include "llvm/CodeGen/InstrSelection.h"
20 #include "llvm/CodeGen/MachineCodeForMethod.h"
21 #include "llvm/CodeGen/MachineCodeForInstruction.h"
22 #include "llvm/DerivedTypes.h"
23 #include "llvm/iTerminators.h"
24 #include "llvm/iMemory.h"
25 #include "llvm/iOther.h"
26 #include "llvm/BasicBlock.h"
27 #include "llvm/Function.h"
28 #include "llvm/ConstantVals.h"
29 #include "Support/MathExtras.h"
33 //************************* Forward Declarations ***************************/
36 static void SetMemOperands_Internal (vector<MachineInstr*>& mvec,
37 vector<MachineInstr*>::iterator mvecI,
38 const InstructionNode* vmInstrNode,
40 std::vector<Value*>& idxVec,
41 const TargetMachine& target);
44 //************************ Internal Functions ******************************/
47 static inline MachineOpCode
48 ChooseBprInstruction(const InstructionNode* instrNode)
52 Instruction* setCCInstr =
53 ((InstructionNode*) instrNode->leftChild())->getInstruction();
55 switch(setCCInstr->getOpcode())
57 case Instruction::SetEQ: opCode = BRZ; break;
58 case Instruction::SetNE: opCode = BRNZ; break;
59 case Instruction::SetLE: opCode = BRLEZ; break;
60 case Instruction::SetGE: opCode = BRGEZ; break;
61 case Instruction::SetLT: opCode = BRLZ; break;
62 case Instruction::SetGT: opCode = BRGZ; break;
64 assert(0 && "Unrecognized VM instruction!");
65 opCode = INVALID_OPCODE;
73 static inline MachineOpCode
74 ChooseBpccInstruction(const InstructionNode* instrNode,
75 const BinaryOperator* setCCInstr)
77 MachineOpCode opCode = INVALID_OPCODE;
79 bool isSigned = setCCInstr->getOperand(0)->getType()->isSigned();
83 switch(setCCInstr->getOpcode())
85 case Instruction::SetEQ: opCode = BE; break;
86 case Instruction::SetNE: opCode = BNE; break;
87 case Instruction::SetLE: opCode = BLE; break;
88 case Instruction::SetGE: opCode = BGE; break;
89 case Instruction::SetLT: opCode = BL; break;
90 case Instruction::SetGT: opCode = BG; break;
92 assert(0 && "Unrecognized VM instruction!");
98 switch(setCCInstr->getOpcode())
100 case Instruction::SetEQ: opCode = BE; break;
101 case Instruction::SetNE: opCode = BNE; break;
102 case Instruction::SetLE: opCode = BLEU; break;
103 case Instruction::SetGE: opCode = BCC; break;
104 case Instruction::SetLT: opCode = BCS; break;
105 case Instruction::SetGT: opCode = BGU; break;
107 assert(0 && "Unrecognized VM instruction!");
115 static inline MachineOpCode
116 ChooseBFpccInstruction(const InstructionNode* instrNode,
117 const BinaryOperator* setCCInstr)
119 MachineOpCode opCode = INVALID_OPCODE;
121 switch(setCCInstr->getOpcode())
123 case Instruction::SetEQ: opCode = FBE; break;
124 case Instruction::SetNE: opCode = FBNE; break;
125 case Instruction::SetLE: opCode = FBLE; break;
126 case Instruction::SetGE: opCode = FBGE; break;
127 case Instruction::SetLT: opCode = FBL; break;
128 case Instruction::SetGT: opCode = FBG; break;
130 assert(0 && "Unrecognized VM instruction!");
138 // Create a unique TmpInstruction for a boolean value,
139 // representing the CC register used by a branch on that value.
140 // For now, hack this using a little static cache of TmpInstructions.
141 // Eventually the entire BURG instruction selection should be put
142 // into a separate class that can hold such information.
143 // The static cache is not too bad because the memory for these
144 // TmpInstructions will be freed along with the rest of the Function anyway.
146 static TmpInstruction*
147 GetTmpForCC(Value* boolVal, const Function *F, const Type* ccType)
149 typedef std::hash_map<const Value*, TmpInstruction*> BoolTmpCache;
150 static BoolTmpCache boolToTmpCache; // Map boolVal -> TmpInstruction*
151 static const Function *lastFunction = 0;// Use to flush cache between funcs
153 assert(boolVal->getType() == Type::BoolTy && "Weird but ok! Delete assert");
155 if (lastFunction != F)
158 boolToTmpCache.clear();
161 // Look for tmpI and create a new one otherwise. The new value is
162 // directly written to map using the ref returned by operator[].
163 TmpInstruction*& tmpI = boolToTmpCache[boolVal];
165 tmpI = new TmpInstruction(ccType, boolVal);
171 static inline MachineOpCode
172 ChooseBccInstruction(const InstructionNode* instrNode,
175 InstructionNode* setCCNode = (InstructionNode*) instrNode->leftChild();
176 BinaryOperator* setCCInstr = (BinaryOperator*) setCCNode->getInstruction();
177 const Type* setCCType = setCCInstr->getOperand(0)->getType();
179 isFPBranch = (setCCType == Type::FloatTy || setCCType == Type::DoubleTy);
182 return ChooseBFpccInstruction(instrNode, setCCInstr);
184 return ChooseBpccInstruction(instrNode, setCCInstr);
188 static inline MachineOpCode
189 ChooseMovFpccInstruction(const InstructionNode* instrNode)
191 MachineOpCode opCode = INVALID_OPCODE;
193 switch(instrNode->getInstruction()->getOpcode())
195 case Instruction::SetEQ: opCode = MOVFE; break;
196 case Instruction::SetNE: opCode = MOVFNE; break;
197 case Instruction::SetLE: opCode = MOVFLE; break;
198 case Instruction::SetGE: opCode = MOVFGE; break;
199 case Instruction::SetLT: opCode = MOVFL; break;
200 case Instruction::SetGT: opCode = MOVFG; break;
202 assert(0 && "Unrecognized VM instruction!");
210 // Assumes that SUBcc v1, v2 -> v3 has been executed.
211 // In most cases, we want to clear v3 and then follow it by instruction
213 // Set mustClearReg=false if v3 need not be cleared before conditional move.
214 // Set valueToMove=0 if we want to conditionally move 0 instead of 1
215 // (i.e., we want to test inverse of a condition)
216 // (The latter two cases do not seem to arise because SetNE needs nothing.)
219 ChooseMovpccAfterSub(const InstructionNode* instrNode,
223 MachineOpCode opCode = INVALID_OPCODE;
227 switch(instrNode->getInstruction()->getOpcode())
229 case Instruction::SetEQ: opCode = MOVE; break;
230 case Instruction::SetLE: opCode = MOVLE; break;
231 case Instruction::SetGE: opCode = MOVGE; break;
232 case Instruction::SetLT: opCode = MOVL; break;
233 case Instruction::SetGT: opCode = MOVG; break;
234 case Instruction::SetNE: assert(0 && "No move required!"); break;
235 default: assert(0 && "Unrecognized VM instr!"); break;
241 static inline MachineOpCode
242 ChooseConvertToFloatInstr(const InstructionNode* instrNode,
245 MachineOpCode opCode = INVALID_OPCODE;
247 switch(instrNode->getOpLabel())
250 if (opType == Type::SByteTy || opType == Type::ShortTy || opType == Type::IntTy)
252 else if (opType == Type::LongTy)
254 else if (opType == Type::DoubleTy)
256 else if (opType == Type::FloatTy)
259 assert(0 && "Cannot convert this type to FLOAT on SPARC");
263 // This is usually used in conjunction with CreateCodeToCopyIntToFloat().
264 // Both functions should treat the integer as a 32-bit value for types
265 // of 4 bytes or less, and as a 64-bit value otherwise.
266 if (opType == Type::SByteTy || opType == Type::UByteTy ||
267 opType == Type::ShortTy || opType == Type::UShortTy ||
268 opType == Type::IntTy || opType == Type::UIntTy)
270 else if (opType == Type::LongTy || opType == Type::ULongTy)
272 else if (opType == Type::FloatTy)
274 else if (opType == Type::DoubleTy)
277 assert(0 && "Cannot convert this type to DOUBLE on SPARC");
287 static inline MachineOpCode
288 ChooseConvertToIntInstr(const InstructionNode* instrNode,
291 MachineOpCode opCode = INVALID_OPCODE;;
293 int instrType = (int) instrNode->getOpLabel();
295 if (instrType == ToSByteTy || instrType == ToShortTy || instrType == ToIntTy)
297 switch (opType->getPrimitiveID())
299 case Type::FloatTyID: opCode = FSTOI; break;
300 case Type::DoubleTyID: opCode = FDTOI; break;
302 assert(0 && "Non-numeric non-bool type cannot be converted to Int");
306 else if (instrType == ToLongTy)
308 switch (opType->getPrimitiveID())
310 case Type::FloatTyID: opCode = FSTOX; break;
311 case Type::DoubleTyID: opCode = FDTOX; break;
313 assert(0 && "Non-numeric non-bool type cannot be converted to Long");
318 assert(0 && "Should not get here, Mo!");
324 static inline MachineOpCode
325 ChooseAddInstructionByType(const Type* resultType)
327 MachineOpCode opCode = INVALID_OPCODE;
329 if (resultType->isIntegral() ||
330 isa<PointerType>(resultType) ||
331 isa<FunctionType>(resultType) ||
332 resultType == Type::LabelTy ||
333 resultType == Type::BoolTy)
338 switch(resultType->getPrimitiveID())
340 case Type::FloatTyID: opCode = FADDS; break;
341 case Type::DoubleTyID: opCode = FADDD; break;
342 default: assert(0 && "Invalid type for ADD instruction"); break;
349 static inline MachineOpCode
350 ChooseAddInstruction(const InstructionNode* instrNode)
352 return ChooseAddInstructionByType(instrNode->getInstruction()->getType());
356 static inline MachineInstr*
357 CreateMovFloatInstruction(const InstructionNode* instrNode,
358 const Type* resultType)
360 MachineInstr* minstr = new MachineInstr((resultType == Type::FloatTy)
362 minstr->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister,
363 instrNode->leftChild()->getValue());
364 minstr->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister,
365 instrNode->getValue());
369 static inline MachineInstr*
370 CreateAddConstInstruction(const InstructionNode* instrNode)
372 MachineInstr* minstr = NULL;
374 Value* constOp = ((InstrTreeNode*) instrNode->rightChild())->getValue();
375 assert(isa<Constant>(constOp));
377 // Cases worth optimizing are:
378 // (1) Add with 0 for float or double: use an FMOV of appropriate type,
379 // instead of an FADD (1 vs 3 cycles). There is no integer MOV.
381 const Type* resultType = instrNode->getInstruction()->getType();
383 if (resultType == Type::FloatTy ||
384 resultType == Type::DoubleTy)
386 double dval = cast<ConstantFP>(constOp)->getValue();
388 minstr = CreateMovFloatInstruction(instrNode, resultType);
395 static inline MachineOpCode
396 ChooseSubInstructionByType(const Type* resultType)
398 MachineOpCode opCode = INVALID_OPCODE;
400 if (resultType->isIntegral() ||
401 resultType->isPointerType())
406 switch(resultType->getPrimitiveID())
408 case Type::FloatTyID: opCode = FSUBS; break;
409 case Type::DoubleTyID: opCode = FSUBD; break;
410 default: assert(0 && "Invalid type for SUB instruction"); break;
417 static inline MachineInstr*
418 CreateSubConstInstruction(const InstructionNode* instrNode)
420 MachineInstr* minstr = NULL;
422 Value* constOp = ((InstrTreeNode*) instrNode->rightChild())->getValue();
423 assert(isa<Constant>(constOp));
425 // Cases worth optimizing are:
426 // (1) Sub with 0 for float or double: use an FMOV of appropriate type,
427 // instead of an FSUB (1 vs 3 cycles). There is no integer MOV.
429 const Type* resultType = instrNode->getInstruction()->getType();
431 if (resultType == Type::FloatTy ||
432 resultType == Type::DoubleTy)
434 double dval = cast<ConstantFP>(constOp)->getValue();
436 minstr = CreateMovFloatInstruction(instrNode, resultType);
443 static inline MachineOpCode
444 ChooseFcmpInstruction(const InstructionNode* instrNode)
446 MachineOpCode opCode = INVALID_OPCODE;
448 Value* operand = ((InstrTreeNode*) instrNode->leftChild())->getValue();
449 switch(operand->getType()->getPrimitiveID()) {
450 case Type::FloatTyID: opCode = FCMPS; break;
451 case Type::DoubleTyID: opCode = FCMPD; break;
452 default: assert(0 && "Invalid type for FCMP instruction"); break;
459 // Assumes that leftArg and rightArg are both cast instructions.
462 BothFloatToDouble(const InstructionNode* instrNode)
464 InstrTreeNode* leftArg = instrNode->leftChild();
465 InstrTreeNode* rightArg = instrNode->rightChild();
466 InstrTreeNode* leftArgArg = leftArg->leftChild();
467 InstrTreeNode* rightArgArg = rightArg->leftChild();
468 assert(leftArg->getValue()->getType() == rightArg->getValue()->getType());
470 // Check if both arguments are floats cast to double
471 return (leftArg->getValue()->getType() == Type::DoubleTy &&
472 leftArgArg->getValue()->getType() == Type::FloatTy &&
473 rightArgArg->getValue()->getType() == Type::FloatTy);
477 static inline MachineOpCode
478 ChooseMulInstructionByType(const Type* resultType)
480 MachineOpCode opCode = INVALID_OPCODE;
482 if (resultType->isIntegral())
485 switch(resultType->getPrimitiveID())
487 case Type::FloatTyID: opCode = FMULS; break;
488 case Type::DoubleTyID: opCode = FMULD; break;
489 default: assert(0 && "Invalid type for MUL instruction"); break;
497 static inline MachineInstr*
498 CreateIntNegInstruction(const TargetMachine& target,
501 MachineInstr* minstr = new MachineInstr(SUB);
502 minstr->SetMachineOperandReg(0, target.getRegInfo().getZeroRegNum());
503 minstr->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister, vreg);
504 minstr->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister, vreg);
509 // Does not create any instructions if we cannot exploit constant to
510 // create a cheaper instruction.
511 // This returns the approximate cost of the instructions generated,
512 // which is used to pick the cheapest when both operands are constant.
513 static inline unsigned int
514 CreateMulConstInstruction(const TargetMachine &target,
515 Value* lval, Value* rval, Value* destVal,
516 vector<MachineInstr*>& mvec)
518 /* An integer multiply is generally more costly than FP multiply */
519 unsigned int cost = target.getInstrInfo().minLatency(MULX);
520 MachineInstr* minstr1 = NULL;
521 MachineInstr* minstr2 = NULL;
523 Value* constOp = rval;
524 if (! isa<Constant>(constOp))
527 // Cases worth optimizing are:
528 // (1) Multiply by 0 or 1 for any type: replace with copy (ADD or FMOV)
529 // (2) Multiply by 2^x for integer types: replace with Shift
531 const Type* resultType = destVal->getType();
533 if (resultType->isIntegral() || resultType->isPointerType())
537 int64_t C = GetConstantValueAsSignedInt(constOp, isValidConst);
540 bool needNeg = false;
547 if (C == 0 || C == 1)
549 cost = target.getInstrInfo().minLatency(ADD);
550 minstr1 = new MachineInstr(ADD);
552 minstr1->SetMachineOperandReg(0,
553 target.getRegInfo().getZeroRegNum());
555 minstr1->SetMachineOperandVal(0,
556 MachineOperand::MO_VirtualRegister, lval);
557 minstr1->SetMachineOperandReg(1,
558 target.getRegInfo().getZeroRegNum());
560 else if (IsPowerOf2(C, pow))
562 minstr1 = new MachineInstr((resultType == Type::LongTy)
564 minstr1->SetMachineOperandVal(0,
565 MachineOperand::MO_VirtualRegister, lval);
566 minstr1->SetMachineOperandConst(1,
567 MachineOperand::MO_UnextendedImmed, pow);
570 if (minstr1 && needNeg)
571 { // insert <reg = SUB 0, reg> after the instr to flip the sign
572 minstr2 = CreateIntNegInstruction(target, destVal);
573 cost += target.getInstrInfo().minLatency(minstr2->getOpCode());
579 if (resultType == Type::FloatTy ||
580 resultType == Type::DoubleTy)
582 double dval = cast<ConstantFP>(constOp)->getValue();
585 bool needNeg = (dval < 0);
587 MachineOpCode opCode = needNeg
588 ? (resultType == Type::FloatTy? FNEGS : FNEGD)
589 : (resultType == Type::FloatTy? FMOVS : FMOVD);
591 minstr1 = new MachineInstr(opCode);
592 minstr1->SetMachineOperandVal(0,
593 MachineOperand::MO_VirtualRegister,
600 minstr1->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister,
605 mvec.push_back(minstr1);
606 cost = target.getInstrInfo().minLatency(minstr1->getOpCode());
610 assert(minstr1 && "Otherwise cost needs to be initialized to 0");
611 cost += target.getInstrInfo().minLatency(minstr2->getOpCode());
612 mvec.push_back(minstr2);
619 // Does not create any instructions if we cannot exploit constant to
620 // create a cheaper instruction.
623 CreateCheapestMulConstInstruction(const TargetMachine &target,
624 Value* lval, Value* rval, Value* destVal,
625 vector<MachineInstr*>& mvec)
628 if (isa<Constant>(lval) && isa<Constant>(rval))
629 { // both operands are constant: try both orders!
630 vector<MachineInstr*> mvec1, mvec2;
631 unsigned int lcost = CreateMulConstInstruction(target, lval, rval,
633 unsigned int rcost = CreateMulConstInstruction(target, rval, lval,
635 vector<MachineInstr*>& mincostMvec = (lcost <= rcost)? mvec1 : mvec2;
636 vector<MachineInstr*>& maxcostMvec = (lcost <= rcost)? mvec2 : mvec1;
637 mvec.insert(mvec.end(), mincostMvec.begin(), mincostMvec.end());
639 for (unsigned int i=0; i < maxcostMvec.size(); ++i)
640 delete maxcostMvec[i];
642 else if (isa<Constant>(rval)) // rval is constant, but not lval
643 CreateMulConstInstruction(target, lval, rval, destVal, mvec);
644 else if (isa<Constant>(lval)) // lval is constant, but not rval
645 CreateMulConstInstruction(target, lval, rval, destVal, mvec);
647 // else neither is constant
651 // Return NULL if we cannot exploit constant to create a cheaper instruction
653 CreateMulInstruction(const TargetMachine &target,
654 Value* lval, Value* rval, Value* destVal,
655 vector<MachineInstr*>& mvec,
656 MachineOpCode forceMulOp = INVALID_MACHINE_OPCODE)
658 unsigned int L = mvec.size();
659 CreateCheapestMulConstInstruction(target, lval, rval, destVal, mvec);
660 if (mvec.size() == L)
661 { // no instructions were added so create MUL reg, reg, reg.
662 // Use FSMULD if both operands are actually floats cast to doubles.
663 // Otherwise, use the default opcode for the appropriate type.
664 MachineOpCode mulOp = ((forceMulOp != INVALID_MACHINE_OPCODE)
666 : ChooseMulInstructionByType(destVal->getType()));
667 MachineInstr* M = new MachineInstr(mulOp);
668 M->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister, lval);
669 M->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister, rval);
670 M->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister, destVal);
676 // Generate a divide instruction for Div or Rem.
677 // For Rem, this assumes that the operand type will be signed if the result
678 // type is signed. This is correct because they must have the same sign.
680 static inline MachineOpCode
681 ChooseDivInstruction(TargetMachine &target,
682 const InstructionNode* instrNode)
684 MachineOpCode opCode = INVALID_OPCODE;
686 const Type* resultType = instrNode->getInstruction()->getType();
688 if (resultType->isIntegral())
689 opCode = resultType->isSigned()? SDIVX : UDIVX;
691 switch(resultType->getPrimitiveID())
693 case Type::FloatTyID: opCode = FDIVS; break;
694 case Type::DoubleTyID: opCode = FDIVD; break;
695 default: assert(0 && "Invalid type for DIV instruction"); break;
702 // Return NULL if we cannot exploit constant to create a cheaper instruction
704 CreateDivConstInstruction(TargetMachine &target,
705 const InstructionNode* instrNode,
706 vector<MachineInstr*>& mvec)
708 MachineInstr* minstr1 = NULL;
709 MachineInstr* minstr2 = NULL;
711 Value* constOp = ((InstrTreeNode*) instrNode->rightChild())->getValue();
712 if (! isa<Constant>(constOp))
715 // Cases worth optimizing are:
716 // (1) Divide by 1 for any type: replace with copy (ADD or FMOV)
717 // (2) Divide by 2^x for integer types: replace with SR[L or A]{X}
719 const Type* resultType = instrNode->getInstruction()->getType();
721 if (resultType->isIntegral())
725 int64_t C = GetConstantValueAsSignedInt(constOp, isValidConst);
728 bool needNeg = false;
737 minstr1 = new MachineInstr(ADD);
738 minstr1->SetMachineOperandVal(0,
739 MachineOperand::MO_VirtualRegister,
740 instrNode->leftChild()->getValue());
741 minstr1->SetMachineOperandReg(1,
742 target.getRegInfo().getZeroRegNum());
744 else if (IsPowerOf2(C, pow))
746 MachineOpCode opCode= ((resultType->isSigned())
747 ? (resultType==Type::LongTy)? SRAX : SRA
748 : (resultType==Type::LongTy)? SRLX : SRL);
749 minstr1 = new MachineInstr(opCode);
750 minstr1->SetMachineOperandVal(0,
751 MachineOperand::MO_VirtualRegister,
752 instrNode->leftChild()->getValue());
753 minstr1->SetMachineOperandConst(1,
754 MachineOperand::MO_UnextendedImmed,
758 if (minstr1 && needNeg)
759 { // insert <reg = SUB 0, reg> after the instr to flip the sign
760 minstr2 = CreateIntNegInstruction(target,
761 instrNode->getValue());
767 if (resultType == Type::FloatTy ||
768 resultType == Type::DoubleTy)
770 double dval = cast<ConstantFP>(constOp)->getValue();
773 bool needNeg = (dval < 0);
775 MachineOpCode opCode = needNeg
776 ? (resultType == Type::FloatTy? FNEGS : FNEGD)
777 : (resultType == Type::FloatTy? FMOVS : FMOVD);
779 minstr1 = new MachineInstr(opCode);
780 minstr1->SetMachineOperandVal(0,
781 MachineOperand::MO_VirtualRegister,
782 instrNode->leftChild()->getValue());
788 minstr1->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister,
789 instrNode->getValue());
792 mvec.push_back(minstr1);
794 mvec.push_back(minstr2);
799 CreateCodeForVariableSizeAlloca(const TargetMachine& target,
802 Value* numElementsVal,
803 vector<MachineInstr*>& getMvec)
807 // Create a Value to hold the (constant) element size
808 Value* tsizeVal = ConstantSInt::get(Type::IntTy, tsize);
810 // Get the constant offset from SP for dynamically allocated storage
811 // and create a temporary Value to hold it.
812 assert(result && result->getParent() && "Result value is not part of a fn?");
813 Function *F = result->getParent()->getParent();
814 MachineCodeForMethod& mcInfo = MachineCodeForMethod::get(F);
816 ConstantSInt* dynamicAreaOffset =
817 ConstantSInt::get(Type::IntTy,
818 target.getFrameInfo().getDynamicAreaOffset(mcInfo,growUp));
819 assert(! growUp && "Has SPARC v9 stack frame convention changed?");
821 // Create a temporary value to hold the result of MUL
822 TmpInstruction* tmpProd = new TmpInstruction(numElementsVal, tsizeVal);
823 MachineCodeForInstruction::get(result).addTemp(tmpProd);
825 // Instruction 1: mul numElements, typeSize -> tmpProd
826 M = new MachineInstr(MULX);
827 M->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister, numElementsVal);
828 M->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister, tsizeVal);
829 M->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister, tmpProd);
830 getMvec.push_back(M);
832 // Instruction 2: sub %sp, tmpProd -> %sp
833 M = new MachineInstr(SUB);
834 M->SetMachineOperandReg(0, target.getRegInfo().getStackPointer());
835 M->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister, tmpProd);
836 M->SetMachineOperandReg(2, target.getRegInfo().getStackPointer());
837 getMvec.push_back(M);
839 // Instruction 3: add %sp, frameSizeBelowDynamicArea -> result
840 M = new MachineInstr(ADD);
841 M->SetMachineOperandReg(0, target.getRegInfo().getStackPointer());
842 M->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister, dynamicAreaOffset);
843 M->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister, result);
844 getMvec.push_back(M);
849 CreateCodeForFixedSizeAlloca(const TargetMachine& target,
852 unsigned int numElements,
853 vector<MachineInstr*>& getMvec)
855 assert(result && result->getParent() &&
856 "Result value is not part of a function?");
857 Function *F = result->getParent()->getParent();
858 MachineCodeForMethod &mcInfo = MachineCodeForMethod::get(F);
860 // Check if the offset would small enough to use as an immediate in
861 // load/stores (check LDX because all load/stores have the same-size immediate
862 // field). If not, put the variable in the dynamically sized area of the
864 unsigned int paddedSizeIgnored;
865 int offsetFromFP = mcInfo.computeOffsetforLocalVar(target, result,
867 tsize * numElements);
868 if (! target.getInstrInfo().constantFitsInImmedField(LDX, offsetFromFP))
870 CreateCodeForVariableSizeAlloca(target, result, tsize,
871 ConstantSInt::get(Type::IntTy,numElements),
876 // else offset fits in immediate field so go ahead and allocate it.
877 offsetFromFP = mcInfo.allocateLocalVar(target, result, tsize * numElements);
879 // Create a temporary Value to hold the constant offset.
880 // This is needed because it may not fit in the immediate field.
881 ConstantSInt* offsetVal = ConstantSInt::get(Type::IntTy, offsetFromFP);
883 // Instruction 1: add %fp, offsetFromFP -> result
884 MachineInstr* M = new MachineInstr(ADD);
885 M->SetMachineOperandReg(0, target.getRegInfo().getFramePointer());
886 M->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister, offsetVal);
887 M->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister, result);
889 getMvec.push_back(M);
894 //------------------------------------------------------------------------
895 // Function SetOperandsForMemInstr
897 // Choose addressing mode for the given load or store instruction.
898 // Use [reg+reg] if it is an indexed reference, and the index offset is
899 // not a constant or if it cannot fit in the offset field.
900 // Use [reg+offset] in all other cases.
902 // This assumes that all array refs are "lowered" to one of these forms:
903 // %x = load (subarray*) ptr, constant ; single constant offset
904 // %x = load (subarray*) ptr, offsetVal ; single non-constant offset
905 // Generally, this should happen via strength reduction + LICM.
906 // Also, strength reduction should take care of using the same register for
907 // the loop index variable and an array index, when that is profitable.
908 //------------------------------------------------------------------------
911 SetOperandsForMemInstr(vector<MachineInstr*>& mvec,
912 vector<MachineInstr*>::iterator mvecI,
913 const InstructionNode* vmInstrNode,
914 const TargetMachine& target)
916 MemAccessInst* memInst = (MemAccessInst*) vmInstrNode->getInstruction();
918 // Variables to hold the index vector, ptr value, and offset value.
919 // The major work here is to extract these for all 3 instruction types
920 // and then call the common function SetMemOperands_Internal().
922 Value* ptrVal = memInst->getPointerOperand();
924 // Start with the index vector of this instruction, if any.
925 vector<Value*> idxVec;
926 idxVec.insert(idxVec.end(), memInst->idx_begin(), memInst->idx_end());
928 // If there is a GetElemPtr instruction to fold in to this instr,
929 // it must be in the left child for Load and GetElemPtr, and in the
930 // right child for Store instructions.
931 InstrTreeNode* ptrChild = (vmInstrNode->getOpLabel() == Instruction::Store
932 ? vmInstrNode->rightChild()
933 : vmInstrNode->leftChild());
935 // Fold chains of GetElemPtr instructions for structure references.
936 if (isa<StructType>(cast<PointerType>(ptrVal->getType())->getElementType())
937 && (ptrChild->getOpLabel() == Instruction::GetElementPtr ||
938 ptrChild->getOpLabel() == GetElemPtrIdx))
940 Value* newPtr = FoldGetElemChain((InstructionNode*) ptrChild, idxVec);
945 SetMemOperands_Internal(mvec, mvecI, vmInstrNode, ptrVal, idxVec, target);
949 // Generate the correct operands (and additional instructions if needed)
950 // for the given pointer and given index vector.
953 SetMemOperands_Internal(vector<MachineInstr*>& mvec,
954 vector<MachineInstr*>::iterator mvecI,
955 const InstructionNode* vmInstrNode,
957 vector<Value*>& idxVec,
958 const TargetMachine& target)
960 MemAccessInst* memInst = (MemAccessInst*) vmInstrNode->getInstruction();
962 // Initialize so we default to storing the offset in a register.
963 int64_t smallConstOffset = 0;
964 Value* valueForRegOffset = NULL;
965 MachineOperand::MachineOperandType offsetOpType =MachineOperand::MO_VirtualRegister;
967 // Check if there is an index vector and if so, compute the
968 // right offset for structures and for arrays
970 if (idxVec.size() > 0)
974 const PointerType* ptrType = cast<PointerType>(ptrVal->getType());
976 // Handle special common case of leading [0] index.
977 bool firstIndexIsZero =
978 bool(isa<ConstantUInt>(idxVec.front()) &&
979 cast<ConstantUInt>(idxVec.front())->getValue() == 0);
981 // This is a real structure reference if the ptr target is a
982 // structure type, and the first offset is [0] (eliminate that offset).
983 if (firstIndexIsZero && ptrType->getElementType()->isStructType())
985 // Compute the offset value using the index vector. Create a
986 // virtual reg. for it since it may not fit in the immed field.
987 assert(idxVec.size() >= 2);
988 idxVec.erase(idxVec.begin());
989 unsigned offset = target.DataLayout.getIndexedOffset(ptrType,idxVec);
990 valueForRegOffset = ConstantSInt::get(Type::IntTy, offset);
994 // It is an array ref, and must have been lowered to a single offset.
995 assert((memInst->getNumOperands()
996 == (unsigned) 1 + memInst->getFirstIndexOperandNumber())
997 && "Array refs must be lowered before Instruction Selection");
999 Value* arrayOffsetVal = * memInst->idx_begin();
1001 // If index is 0, the offset value is just 0. Otherwise,
1002 // generate a MUL instruction to compute address from index.
1003 // The call to getTypeSize() will fail if size is not constant.
1004 // CreateMulInstruction() folds constants intelligently enough.
1006 if (firstIndexIsZero)
1008 offsetOpType = MachineOperand::MO_SignExtendedImmed;
1009 smallConstOffset = 0;
1013 vector<MachineInstr*> mulVec;
1014 Instruction* addr = new TmpInstruction(Type::UIntTy, memInst);
1015 MachineCodeForInstruction::get(memInst).addTemp(addr);
1017 unsigned int eltSize =
1018 target.DataLayout.getTypeSize(ptrType->getElementType());
1019 assert(eltSize > 0 && "Invalid or non-const array element size");
1020 ConstantUInt* eltVal = ConstantUInt::get(Type::UIntTy, eltSize);
1022 CreateMulInstruction(target,
1023 arrayOffsetVal, /* lval, not likely const */
1024 eltVal, /* rval, likely constant */
1026 mulVec, INVALID_MACHINE_OPCODE);
1027 assert(mulVec.size() > 0 && "No multiply instruction created?");
1028 for (vector<MachineInstr*>::const_iterator I = mulVec.begin();
1029 I != mulVec.end(); ++I)
1031 mvecI = mvec.insert(mvecI, *I); // ptr to inserted value
1032 ++mvecI; // ptr to mem. instr.
1035 valueForRegOffset = addr;
1041 offsetOpType = MachineOperand::MO_SignExtendedImmed;
1042 smallConstOffset = 0;
1046 // Operand 0 is value, operand 1 is ptr, operand 2 is offset
1047 // For LOAD or GET_ELEMENT_PTR,
1048 // Operand 0 is ptr, operand 1 is offset, operand 2 is result.
1050 unsigned offsetOpNum, ptrOpNum;
1051 if (memInst->getOpcode() == Instruction::Store)
1053 (*mvecI)->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister,
1054 vmInstrNode->leftChild()->getValue());
1062 (*mvecI)->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister,
1066 (*mvecI)->SetMachineOperandVal(ptrOpNum, MachineOperand::MO_VirtualRegister,
1069 if (offsetOpType == MachineOperand::MO_VirtualRegister)
1071 assert(valueForRegOffset != NULL);
1072 (*mvecI)->SetMachineOperandVal(offsetOpNum, offsetOpType,
1076 (*mvecI)->SetMachineOperandConst(offsetOpNum, offsetOpType,
1082 // Substitute operand `operandNum' of the instruction in node `treeNode'
1083 // in place of the use(s) of that instruction in node `parent'.
1084 // Check both explicit and implicit operands!
1085 // Also make sure to skip over a parent who:
1086 // (1) is a list node in the Burg tree, or
1087 // (2) itself had its results forwarded to its parent
1090 ForwardOperand(InstructionNode* treeNode,
1091 InstrTreeNode* parent,
1094 assert(treeNode && parent && "Invalid invocation of ForwardOperand");
1096 Instruction* unusedOp = treeNode->getInstruction();
1097 Value* fwdOp = unusedOp->getOperand(operandNum);
1099 // The parent itself may be a list node, so find the real parent instruction
1100 while (parent->getNodeType() != InstrTreeNode::NTInstructionNode)
1102 parent = parent->parent();
1103 assert(parent && "ERROR: Non-instruction node has no parent in tree.");
1105 InstructionNode* parentInstrNode = (InstructionNode*) parent;
1107 Instruction* userInstr = parentInstrNode->getInstruction();
1108 MachineCodeForInstruction &mvec = MachineCodeForInstruction::get(userInstr);
1110 // The parent's mvec would be empty if it was itself forwarded.
1111 // Recursively call ForwardOperand in that case...
1113 if (mvec.size() == 0)
1115 assert(parent->parent() != NULL &&
1116 "Parent could not have been forwarded, yet has no instructions?");
1117 ForwardOperand(treeNode, parent->parent(), operandNum);
1121 bool fwdSuccessful = false;
1122 for (unsigned i=0, N=mvec.size(); i < N; i++)
1124 MachineInstr* minstr = mvec[i];
1125 for (unsigned i=0, numOps=minstr->getNumOperands(); i < numOps; ++i)
1127 const MachineOperand& mop = minstr->getOperand(i);
1128 if (mop.getOperandType() == MachineOperand::MO_VirtualRegister &&
1129 mop.getVRegValue() == unusedOp)
1131 minstr->SetMachineOperandVal(i,
1132 MachineOperand::MO_VirtualRegister, fwdOp);
1133 fwdSuccessful = true;
1137 for (unsigned i=0,numOps=minstr->getNumImplicitRefs(); i<numOps; ++i)
1138 if (minstr->getImplicitRef(i) == unusedOp)
1140 minstr->setImplicitRef(i, fwdOp,
1141 minstr->implicitRefIsDefined(i));
1142 fwdSuccessful = true;
1145 assert(fwdSuccessful && "Value to be forwarded is never used!");
1150 void UltraSparcInstrInfo::
1151 CreateCopyInstructionsByType(const TargetMachine& target,
1155 vector<MachineInstr*>& minstrVec) const
1157 bool loadConstantToReg = false;
1159 const Type* resultType = dest->getType();
1161 MachineOpCode opCode = ChooseAddInstructionByType(resultType);
1162 if (opCode == INVALID_OPCODE)
1164 assert(0 && "Unsupported result type in CreateCopyInstructionsByType()");
1168 // if `src' is a constant that doesn't fit in the immed field or if it is
1169 // a global variable (i.e., a constant address), generate a load
1170 // instruction instead of an add
1172 if (isa<Constant>(src))
1174 unsigned int machineRegNum;
1176 MachineOperand::MachineOperandType opType =
1177 ChooseRegOrImmed(src, opCode, target, /*canUseImmed*/ true,
1178 machineRegNum, immedValue);
1180 if (opType == MachineOperand::MO_VirtualRegister)
1181 loadConstantToReg = true;
1183 else if (isa<GlobalValue>(src))
1184 loadConstantToReg = true;
1186 if (loadConstantToReg)
1187 { // `src' is constant and cannot fit in immed field for the ADD
1188 // Insert instructions to "load" the constant into a register
1189 vector<TmpInstruction*> tempVec;
1190 target.getInstrInfo().CreateCodeToLoadConst(F, src, dest,
1191 minstrVec, tempVec);
1192 for (unsigned i=0; i < tempVec.size(); i++)
1193 MachineCodeForInstruction::get(dest).addTemp(tempVec[i]);
1196 { // Create an add-with-0 instruction of the appropriate type.
1197 // Make `src' the second operand, in case it is a constant
1198 // Use (unsigned long) 0 for a NULL pointer value.
1200 const Type* zeroValueType =
1201 (resultType->getPrimitiveID() == Type::PointerTyID)? Type::ULongTy
1203 MachineInstr* minstr = new MachineInstr(opCode);
1204 minstr->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister,
1205 Constant::getNullConstant(zeroValueType));
1206 minstr->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister, src);
1207 minstr->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister,dest);
1208 minstrVec.push_back(minstr);
1214 //******************* Externally Visible Functions *************************/
1218 //------------------------------------------------------------------------
1219 // External Function: ThisIsAChainRule
1222 // Check if a given BURG rule is a chain rule.
1223 //------------------------------------------------------------------------
1226 ThisIsAChainRule(int eruleno)
1230 case 111: // stmt: reg
1231 case 113: // stmt: bool
1254 return false; break;
1259 //------------------------------------------------------------------------
1260 // External Function: GetInstructionsByRule
1263 // Choose machine instructions for the SPARC according to the
1264 // patterns chosen by the BURG-generated parser.
1265 //------------------------------------------------------------------------
1268 GetInstructionsByRule(InstructionNode* subtreeRoot,
1271 TargetMachine &target,
1272 vector<MachineInstr*>& mvec)
1274 bool checkCast = false; // initialize here to use fall-through
1276 int forwardOperandNum = -1;
1277 unsigned int allocaSize = 0;
1278 MachineInstr* M, *M2;
1283 // If the code for this instruction was folded into the parent (user),
1285 if (subtreeRoot->isFoldedIntoParent())
1289 // Let's check for chain rules outside the switch so that we don't have
1290 // to duplicate the list of chain rule production numbers here again
1292 if (ThisIsAChainRule(ruleForNode))
1294 // Chain rules have a single nonterminal on the RHS.
1295 // Get the rule that matches the RHS non-terminal and use that instead.
1297 assert(nts[0] && ! nts[1]
1298 && "A chain rule should have only one RHS non-terminal!");
1299 nextRule = burm_rule(subtreeRoot->state, nts[0]);
1300 nts = burm_nts[nextRule];
1301 GetInstructionsByRule(subtreeRoot, nextRule, nts, target, mvec);
1305 switch(ruleForNode) {
1306 case 1: // stmt: Ret
1307 case 2: // stmt: RetValue(reg)
1308 { // NOTE: Prepass of register allocation is responsible
1309 // for moving return value to appropriate register.
1310 // Mark the return-address register as a hidden virtual reg.
1311 // Mark the return value register as an implicit ref of
1312 // the machine instruction.
1313 // Finally put a NOP in the delay slot.
1314 ReturnInst *returnInstr =
1315 cast<ReturnInst>(subtreeRoot->getInstruction());
1316 assert(returnInstr->getOpcode() == Instruction::Ret);
1318 Instruction* returnReg = new TmpInstruction(returnInstr);
1319 MachineCodeForInstruction::get(returnInstr).addTemp(returnReg);
1321 M = new MachineInstr(JMPLRET);
1322 M->SetMachineOperandReg(0, MachineOperand::MO_VirtualRegister,
1324 M->SetMachineOperandConst(1,MachineOperand::MO_SignExtendedImmed,
1326 M->SetMachineOperandReg(2, target.getRegInfo().getZeroRegNum());
1328 if (returnInstr->getReturnValue() != NULL)
1329 M->addImplicitRef(returnInstr->getReturnValue());
1332 mvec.push_back(new MachineInstr(NOP));
1337 case 3: // stmt: Store(reg,reg)
1338 case 4: // stmt: Store(reg,ptrreg)
1339 mvec.push_back(new MachineInstr(
1340 ChooseStoreInstruction(
1341 subtreeRoot->leftChild()->getValue()->getType())));
1342 SetOperandsForMemInstr(mvec, mvec.end()-1, subtreeRoot, target);
1345 case 5: // stmt: BrUncond
1346 M = new MachineInstr(BA);
1347 M->SetMachineOperandVal(0, MachineOperand::MO_CCRegister,
1349 M->SetMachineOperandVal(1, MachineOperand::MO_PCRelativeDisp,
1350 cast<BranchInst>(subtreeRoot->getInstruction())->getSuccessor(0));
1354 mvec.push_back(new MachineInstr(NOP));
1357 case 206: // stmt: BrCond(setCCconst)
1358 { // setCCconst => boolean was computed with `%b = setCC type reg1 const'
1359 // If the constant is ZERO, we can use the branch-on-integer-register
1360 // instructions and avoid the SUBcc instruction entirely.
1361 // Otherwise this is just the same as case 5, so just fall through.
1363 InstrTreeNode* constNode = subtreeRoot->leftChild()->rightChild();
1365 constNode->getNodeType() ==InstrTreeNode::NTConstNode);
1366 Constant *constVal = cast<Constant>(constNode->getValue());
1369 if ((constVal->getType()->isIntegral()
1370 || constVal->getType()->isPointerType())
1371 && GetConstantValueAsSignedInt(constVal, isValidConst) == 0
1374 // That constant is a zero after all...
1375 // Use the left child of setCC as the first argument!
1376 // Mark the setCC node so that no code is generated for it.
1377 InstructionNode* setCCNode = (InstructionNode*)
1378 subtreeRoot->leftChild();
1379 assert(setCCNode->getOpLabel() == SetCCOp);
1380 setCCNode->markFoldedIntoParent();
1382 BranchInst* brInst=cast<BranchInst>(subtreeRoot->getInstruction());
1384 M = new MachineInstr(ChooseBprInstruction(subtreeRoot));
1385 M->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister,
1386 setCCNode->leftChild()->getValue());
1387 M->SetMachineOperandVal(1, MachineOperand::MO_PCRelativeDisp,
1388 brInst->getSuccessor(0));
1392 mvec.push_back(new MachineInstr(NOP));
1395 M = new MachineInstr(BA);
1396 M->SetMachineOperandVal(0, MachineOperand::MO_CCRegister,
1398 M->SetMachineOperandVal(1, MachineOperand::MO_PCRelativeDisp,
1399 brInst->getSuccessor(1));
1403 mvec.push_back(new MachineInstr(NOP));
1407 // ELSE FALL THROUGH
1410 case 6: // stmt: BrCond(bool)
1411 { // bool => boolean was computed with some boolean operator
1412 // (SetCC, Not, ...). We need to check whether the type was a FP,
1413 // signed int or unsigned int, and check the branching condition in
1414 // order to choose the branch to use.
1415 // If it is an integer CC, we also need to find the unique
1416 // TmpInstruction representing that CC.
1418 BranchInst* brInst = cast<BranchInst>(subtreeRoot->getInstruction());
1420 M = new MachineInstr(ChooseBccInstruction(subtreeRoot, isFPBranch));
1422 Value* ccValue = GetTmpForCC(subtreeRoot->leftChild()->getValue(),
1423 brInst->getParent()->getParent(),
1424 isFPBranch? Type::FloatTy : Type::IntTy);
1426 M->SetMachineOperandVal(0, MachineOperand::MO_CCRegister, ccValue);
1427 M->SetMachineOperandVal(1, MachineOperand::MO_PCRelativeDisp,
1428 brInst->getSuccessor(0));
1432 mvec.push_back(new MachineInstr(NOP));
1435 M = new MachineInstr(BA);
1436 M->SetMachineOperandVal(0, MachineOperand::MO_CCRegister,
1438 M->SetMachineOperandVal(1, MachineOperand::MO_PCRelativeDisp,
1439 brInst->getSuccessor(1));
1443 mvec.push_back(new MachineInstr(NOP));
1447 case 208: // stmt: BrCond(boolconst)
1449 // boolconst => boolean is a constant; use BA to first or second label
1450 Constant* constVal =
1451 cast<Constant>(subtreeRoot->leftChild()->getValue());
1452 unsigned dest = cast<ConstantBool>(constVal)->getValue()? 0 : 1;
1454 M = new MachineInstr(BA);
1455 M->SetMachineOperandVal(0, MachineOperand::MO_CCRegister,
1457 M->SetMachineOperandVal(1, MachineOperand::MO_PCRelativeDisp,
1458 ((BranchInst*) subtreeRoot->getInstruction())->getSuccessor(dest));
1462 mvec.push_back(new MachineInstr(NOP));
1466 case 8: // stmt: BrCond(boolreg)
1467 { // boolreg => boolean is stored in an existing register.
1468 // Just use the branch-on-integer-register instruction!
1470 M = new MachineInstr(BRNZ);
1471 M->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister,
1472 subtreeRoot->leftChild()->getValue());
1473 M->SetMachineOperandVal(1, MachineOperand::MO_PCRelativeDisp,
1474 ((BranchInst*) subtreeRoot->getInstruction())->getSuccessor(0));
1478 mvec.push_back(new MachineInstr(NOP));
1481 M = new MachineInstr(BA);
1482 M->SetMachineOperandVal(0, MachineOperand::MO_CCRegister,
1484 M->SetMachineOperandVal(1, MachineOperand::MO_PCRelativeDisp,
1485 ((BranchInst*) subtreeRoot->getInstruction())->getSuccessor(1));
1489 mvec.push_back(new MachineInstr(NOP));
1493 case 9: // stmt: Switch(reg)
1494 assert(0 && "*** SWITCH instruction is not implemented yet.");
1497 case 10: // reg: VRegList(reg, reg)
1498 assert(0 && "VRegList should never be the topmost non-chain rule");
1501 case 21: // bool: Not(bool): Both these are implemented as:
1502 case 421: // reg: BNot(reg) : reg = reg XOR-NOT 0
1503 M = new MachineInstr(XNOR);
1504 M->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister,
1505 subtreeRoot->leftChild()->getValue());
1506 M->SetMachineOperandReg(1, target.getRegInfo().getZeroRegNum());
1507 M->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister,
1508 subtreeRoot->getValue());
1512 case 322: // reg: ToBoolTy(bool):
1513 case 22: // reg: ToBoolTy(reg):
1515 const Type* opType = subtreeRoot->leftChild()->getValue()->getType();
1516 assert(opType->isIntegral() || opType->isPointerType()
1517 || opType == Type::BoolTy);
1518 forwardOperandNum = 0; // forward first operand to user
1522 case 23: // reg: ToUByteTy(reg)
1523 case 25: // reg: ToUShortTy(reg)
1524 case 27: // reg: ToUIntTy(reg)
1525 case 29: // reg: ToULongTy(reg)
1527 const Type* opType = subtreeRoot->leftChild()->getValue()->getType();
1528 assert(opType->isIntegral() ||
1529 opType->isPointerType() ||
1530 opType == Type::BoolTy && "Cast is illegal for other types");
1531 forwardOperandNum = 0; // forward first operand to user
1535 case 24: // reg: ToSByteTy(reg)
1536 case 26: // reg: ToShortTy(reg)
1537 case 28: // reg: ToIntTy(reg)
1538 case 30: // reg: ToLongTy(reg)
1540 const Type* opType = subtreeRoot->leftChild()->getValue()->getType();
1541 if (opType->isIntegral()
1542 || opType->isPointerType()
1543 || opType == Type::BoolTy)
1545 forwardOperandNum = 0; // forward first operand to user
1549 // If the source operand is an FP type, the int result must be
1550 // copied from float to int register via memory!
1551 Instruction *dest = subtreeRoot->getInstruction();
1552 Value* leftVal = subtreeRoot->leftChild()->getValue();
1554 vector<MachineInstr*> minstrVec;
1556 if (opType == Type::FloatTy || opType == Type::DoubleTy)
1558 // Create a temporary to represent the INT register
1559 // into which the FP value will be copied via memory.
1560 // The type of this temporary will determine the FP
1561 // register used: single-prec for a 32-bit int or smaller,
1562 // double-prec for a 64-bit int.
1564 const Type* destTypeToUse =
1565 (dest->getType() == Type::LongTy)? Type::DoubleTy
1567 destForCast = new TmpInstruction(destTypeToUse, leftVal);
1568 MachineCodeForInstruction &MCFI =
1569 MachineCodeForInstruction::get(dest);
1570 MCFI.addTemp(destForCast);
1572 vector<TmpInstruction*> tempVec;
1573 target.getInstrInfo().CreateCodeToCopyFloatToInt(
1574 dest->getParent()->getParent(),
1575 (TmpInstruction*) destForCast, dest,
1576 minstrVec, tempVec, target);
1578 for (unsigned i=0; i < tempVec.size(); ++i)
1579 MCFI.addTemp(tempVec[i]);
1582 destForCast = leftVal;
1584 MachineOpCode opCode=ChooseConvertToIntInstr(subtreeRoot, opType);
1585 assert(opCode != INVALID_OPCODE && "Expected to need conversion!");
1587 M = new MachineInstr(opCode);
1588 M->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister,
1590 M->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister,
1594 // Append the copy code, if any, after the conversion instr.
1595 mvec.insert(mvec.end(), minstrVec.begin(), minstrVec.end());
1600 case 31: // reg: ToFloatTy(reg):
1601 case 32: // reg: ToDoubleTy(reg):
1602 case 232: // reg: ToDoubleTy(Constant):
1604 // If this instruction has a parent (a user) in the tree
1605 // and the user is translated as an FsMULd instruction,
1606 // then the cast is unnecessary. So check that first.
1607 // In the future, we'll want to do the same for the FdMULq instruction,
1608 // so do the check here instead of only for ToFloatTy(reg).
1610 if (subtreeRoot->parent() != NULL &&
1611 MachineCodeForInstruction::get(((InstructionNode*)subtreeRoot->parent())->getInstruction())[0]->getOpCode() == FSMULD)
1613 forwardOperandNum = 0; // forward first operand to user
1617 Value* leftVal = subtreeRoot->leftChild()->getValue();
1618 const Type* opType = leftVal->getType();
1619 MachineOpCode opCode=ChooseConvertToFloatInstr(subtreeRoot,opType);
1620 if (opCode == INVALID_OPCODE) // no conversion needed
1622 forwardOperandNum = 0; // forward first operand to user
1626 // If the source operand is a non-FP type it must be
1627 // first copied from int to float register via memory!
1628 Instruction *dest = subtreeRoot->getInstruction();
1631 if (opType != Type::FloatTy && opType != Type::DoubleTy)
1633 // Create a temporary to represent the FP register
1634 // into which the integer will be copied via memory.
1635 // The type of this temporary will determine the FP
1636 // register used: single-prec for a 32-bit int or smaller,
1637 // double-prec for a 64-bit int.
1639 const Type* srcTypeToUse =
1640 (leftVal->getType() == Type::LongTy)? Type::DoubleTy
1643 srcForCast = new TmpInstruction(srcTypeToUse, dest);
1644 MachineCodeForInstruction &DestMCFI =
1645 MachineCodeForInstruction::get(dest);
1646 DestMCFI.addTemp(srcForCast);
1648 vector<MachineInstr*> minstrVec;
1649 vector<TmpInstruction*> tempVec;
1650 target.getInstrInfo().CreateCodeToCopyIntToFloat(
1651 dest->getParent()->getParent(),
1652 leftVal, (TmpInstruction*) srcForCast,
1653 minstrVec, tempVec, target);
1655 mvec.insert(mvec.end(), minstrVec.begin(),minstrVec.end());
1657 for (unsigned i=0; i < tempVec.size(); ++i)
1658 DestMCFI.addTemp(tempVec[i]);
1661 srcForCast = leftVal;
1663 M = new MachineInstr(opCode);
1664 M->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister,
1666 M->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister,
1673 case 19: // reg: ToArrayTy(reg):
1674 case 20: // reg: ToPointerTy(reg):
1675 forwardOperandNum = 0; // forward first operand to user
1678 case 233: // reg: Add(reg, Constant)
1679 M = CreateAddConstInstruction(subtreeRoot);
1685 // ELSE FALL THROUGH
1687 case 33: // reg: Add(reg, reg)
1688 mvec.push_back(new MachineInstr(ChooseAddInstruction(subtreeRoot)));
1689 Set3OperandsFromInstr(mvec.back(), subtreeRoot, target);
1692 case 234: // reg: Sub(reg, Constant)
1693 M = CreateSubConstInstruction(subtreeRoot);
1699 // ELSE FALL THROUGH
1701 case 34: // reg: Sub(reg, reg)
1702 mvec.push_back(new MachineInstr(ChooseSubInstructionByType(
1703 subtreeRoot->getInstruction()->getType())));
1704 Set3OperandsFromInstr(mvec.back(), subtreeRoot, target);
1707 case 135: // reg: Mul(todouble, todouble)
1711 case 35: // reg: Mul(reg, reg)
1713 MachineOpCode forceOp = ((checkCast && BothFloatToDouble(subtreeRoot))
1715 : INVALID_MACHINE_OPCODE);
1716 CreateMulInstruction(target,
1717 subtreeRoot->leftChild()->getValue(),
1718 subtreeRoot->rightChild()->getValue(),
1719 subtreeRoot->getInstruction(),
1723 case 335: // reg: Mul(todouble, todoubleConst)
1727 case 235: // reg: Mul(reg, Constant)
1729 MachineOpCode forceOp = ((checkCast && BothFloatToDouble(subtreeRoot))
1731 : INVALID_MACHINE_OPCODE);
1732 CreateMulInstruction(target,
1733 subtreeRoot->leftChild()->getValue(),
1734 subtreeRoot->rightChild()->getValue(),
1735 subtreeRoot->getInstruction(),
1739 case 236: // reg: Div(reg, Constant)
1741 CreateDivConstInstruction(target, subtreeRoot, mvec);
1742 if (mvec.size() > L)
1744 // ELSE FALL THROUGH
1746 case 36: // reg: Div(reg, reg)
1747 mvec.push_back(new MachineInstr(ChooseDivInstruction(target, subtreeRoot)));
1748 Set3OperandsFromInstr(mvec.back(), subtreeRoot, target);
1751 case 37: // reg: Rem(reg, reg)
1752 case 237: // reg: Rem(reg, Constant)
1754 Instruction* remInstr = subtreeRoot->getInstruction();
1756 TmpInstruction* quot = new TmpInstruction(
1757 subtreeRoot->leftChild()->getValue(),
1758 subtreeRoot->rightChild()->getValue());
1759 TmpInstruction* prod = new TmpInstruction(
1761 subtreeRoot->rightChild()->getValue());
1762 MachineCodeForInstruction::get(remInstr).addTemp(quot).addTemp(prod);
1764 M = new MachineInstr(ChooseDivInstruction(target, subtreeRoot));
1765 Set3OperandsFromInstr(M, subtreeRoot, target);
1766 M->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister,quot);
1769 M = new MachineInstr(ChooseMulInstructionByType(
1770 subtreeRoot->getInstruction()->getType()));
1771 M->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister,quot);
1772 M->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister,
1773 subtreeRoot->rightChild()->getValue());
1774 M->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister,prod);
1777 M = new MachineInstr(ChooseSubInstructionByType(
1778 subtreeRoot->getInstruction()->getType()));
1779 Set3OperandsFromInstr(M, subtreeRoot, target);
1780 M->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister,prod);
1786 case 38: // bool: And(bool, bool)
1787 case 238: // bool: And(bool, boolconst)
1788 case 338: // reg : BAnd(reg, reg)
1789 case 538: // reg : BAnd(reg, Constant)
1790 mvec.push_back(new MachineInstr(AND));
1791 Set3OperandsFromInstr(mvec.back(), subtreeRoot, target);
1794 case 138: // bool: And(bool, not)
1795 case 438: // bool: BAnd(bool, not)
1796 mvec.push_back(new MachineInstr(ANDN));
1797 Set3OperandsFromInstr(mvec.back(), subtreeRoot, target);
1800 case 39: // bool: Or(bool, bool)
1801 case 239: // bool: Or(bool, boolconst)
1802 case 339: // reg : BOr(reg, reg)
1803 case 539: // reg : BOr(reg, Constant)
1804 mvec.push_back(new MachineInstr(ORN));
1805 Set3OperandsFromInstr(mvec.back(), subtreeRoot, target);
1808 case 139: // bool: Or(bool, not)
1809 case 439: // bool: BOr(bool, not)
1810 mvec.push_back(new MachineInstr(ORN));
1811 Set3OperandsFromInstr(mvec.back(), subtreeRoot, target);
1814 case 40: // bool: Xor(bool, bool)
1815 case 240: // bool: Xor(bool, boolconst)
1816 case 340: // reg : BXor(reg, reg)
1817 case 540: // reg : BXor(reg, Constant)
1818 mvec.push_back(new MachineInstr(XOR));
1819 Set3OperandsFromInstr(mvec.back(), subtreeRoot, target);
1822 case 140: // bool: Xor(bool, not)
1823 case 440: // bool: BXor(bool, not)
1824 mvec.push_back(new MachineInstr(XNOR));
1825 Set3OperandsFromInstr(mvec.back(), subtreeRoot, target);
1828 case 41: // boolconst: SetCC(reg, Constant)
1830 // If the SetCC was folded into the user (parent), it will be
1831 // caught above. All other cases are the same as case 42,
1832 // so just fall through.
1834 case 42: // bool: SetCC(reg, reg):
1836 // This generates a SUBCC instruction, putting the difference in
1837 // a result register, and setting a condition code.
1839 // If the boolean result of the SetCC is used by anything other
1840 // than a single branch instruction, the boolean must be
1841 // computed and stored in the result register. Otherwise, discard
1842 // the difference (by using %g0) and keep only the condition code.
1844 // To compute the boolean result in a register we use a conditional
1845 // move, unless the result of the SUBCC instruction can be used as
1846 // the bool! This assumes that zero is FALSE and any non-zero
1849 InstructionNode* parentNode = (InstructionNode*) subtreeRoot->parent();
1850 Instruction* setCCInstr = subtreeRoot->getInstruction();
1851 bool keepBoolVal = (parentNode == NULL ||
1852 parentNode->getInstruction()->getOpcode()
1853 != Instruction::Br);
1854 bool subValIsBoolVal = setCCInstr->getOpcode() == Instruction::SetNE;
1855 bool keepSubVal = keepBoolVal && subValIsBoolVal;
1856 bool computeBoolVal = keepBoolVal && ! subValIsBoolVal;
1860 MachineOpCode movOpCode = 0;
1862 // Mark the 4th operand as being a CC register, and as a def
1863 // A TmpInstruction is created to represent the CC "result".
1864 // Unlike other instances of TmpInstruction, this one is used
1865 // by machine code of multiple LLVM instructions, viz.,
1866 // the SetCC and the branch. Make sure to get the same one!
1867 // Note that we do this even for FP CC registers even though they
1868 // are explicit operands, because the type of the operand
1869 // needs to be a floating point condition code, not an integer
1870 // condition code. Think of this as casting the bool result to
1871 // a FP condition code register.
1873 Value* leftVal = subtreeRoot->leftChild()->getValue();
1874 bool isFPCompare = (leftVal->getType() == Type::FloatTy ||
1875 leftVal->getType() == Type::DoubleTy);
1877 TmpInstruction* tmpForCC = GetTmpForCC(setCCInstr,
1878 setCCInstr->getParent()->getParent(),
1879 isFPCompare? Type::FloatTy : Type::IntTy);
1880 MachineCodeForInstruction::get(setCCInstr).addTemp(tmpForCC);
1884 // Integer condition: dest. should be %g0 or an integer register.
1885 // If result must be saved but condition is not SetEQ then we need
1886 // a separate instruction to compute the bool result, so discard
1887 // result of SUBcc instruction anyway.
1889 M = new MachineInstr(SUBcc);
1890 Set3OperandsFromInstr(M, subtreeRoot, target, ! keepSubVal);
1891 M->SetMachineOperandVal(3, MachineOperand::MO_CCRegister,
1892 tmpForCC, /*def*/true);
1896 { // recompute bool using the integer condition codes
1898 ChooseMovpccAfterSub(subtreeRoot,mustClearReg,valueToMove);
1903 // FP condition: dest of FCMP should be some FCCn register
1904 M = new MachineInstr(ChooseFcmpInstruction(subtreeRoot));
1905 M->SetMachineOperandVal(0, MachineOperand::MO_CCRegister,
1907 M->SetMachineOperandVal(1,MachineOperand::MO_VirtualRegister,
1908 subtreeRoot->leftChild()->getValue());
1909 M->SetMachineOperandVal(2,MachineOperand::MO_VirtualRegister,
1910 subtreeRoot->rightChild()->getValue());
1914 {// recompute bool using the FP condition codes
1915 mustClearReg = true;
1917 movOpCode = ChooseMovFpccInstruction(subtreeRoot);
1924 {// Unconditionally set register to 0
1925 M = new MachineInstr(SETHI);
1926 M->SetMachineOperandConst(0,MachineOperand::MO_UnextendedImmed,
1928 M->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister,
1933 // Now conditionally move `valueToMove' (0 or 1) into the register
1934 M = new MachineInstr(movOpCode);
1935 M->SetMachineOperandVal(0, MachineOperand::MO_CCRegister,
1937 M->SetMachineOperandConst(1, MachineOperand::MO_UnextendedImmed,
1939 M->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister,
1946 case 43: // boolreg: VReg
1947 case 44: // boolreg: Constant
1950 case 51: // reg: Load(reg)
1951 case 52: // reg: Load(ptrreg)
1952 case 53: // reg: LoadIdx(reg,reg)
1953 case 54: // reg: LoadIdx(ptrreg,reg)
1954 mvec.push_back(new MachineInstr(ChooseLoadInstruction(
1955 subtreeRoot->getValue()->getType())));
1956 SetOperandsForMemInstr(mvec, mvec.end()-1, subtreeRoot, target);
1959 case 55: // reg: GetElemPtr(reg)
1960 case 56: // reg: GetElemPtrIdx(reg,reg)
1961 // If the GetElemPtr was folded into the user (parent), it will be
1962 // caught above. For other cases, we have to compute the address.
1963 mvec.push_back(new MachineInstr(ADD));
1964 SetOperandsForMemInstr(mvec, mvec.end()-1, subtreeRoot, target);
1967 case 57: // reg: Alloca: Implement as 1 instruction:
1968 { // add %fp, offsetFromFP -> result
1969 AllocationInst* instr =
1970 cast<AllocationInst>(subtreeRoot->getInstruction());
1971 unsigned int tsize =
1972 target.findOptimalStorageSize(instr->getAllocatedType());
1974 CreateCodeForFixedSizeAlloca(target, instr, tsize, 1, mvec);
1978 case 58: // reg: Alloca(reg): Implement as 3 instructions:
1979 // mul num, typeSz -> tmp
1980 // sub %sp, tmp -> %sp
1981 { // add %sp, frameSizeBelowDynamicArea -> result
1982 AllocationInst* instr =
1983 cast<AllocationInst>(subtreeRoot->getInstruction());
1984 const Type* eltType = instr->getAllocatedType();
1986 // If #elements is constant, use simpler code for fixed-size allocas
1987 int tsize = (int) target.findOptimalStorageSize(eltType);
1988 Value* numElementsVal = NULL;
1989 bool isArray = instr->isArrayAllocation();
1992 isa<Constant>(numElementsVal = instr->getArraySize()))
1993 { // total size is constant: generate code for fixed-size alloca
1994 unsigned int numElements = isArray?
1995 cast<ConstantUInt>(numElementsVal)->getValue() : 1;
1996 CreateCodeForFixedSizeAlloca(target, instr, tsize,
1999 else // total size is not constant.
2000 CreateCodeForVariableSizeAlloca(target, instr, tsize,
2001 numElementsVal, mvec);
2005 case 61: // reg: Call
2006 { // Generate a call-indirect (i.e., jmpl) for now to expose
2007 // the potential need for registers. If an absolute address
2008 // is available, replace this with a CALL instruction.
2009 // Mark both the indirection register and the return-address
2010 // register as hidden virtual registers.
2011 // Also, mark the operands of the Call and return value (if
2012 // any) as implicit operands of the CALL machine instruction.
2014 CallInst *callInstr = cast<CallInst>(subtreeRoot->getInstruction());
2015 Value *callee = callInstr->getCalledValue();
2017 // Create hidden virtual register for return address, with type void*.
2018 Instruction* retAddrReg =
2019 new TmpInstruction(PointerType::get(Type::VoidTy), callInstr);
2020 MachineCodeForInstruction::get(callInstr).addTemp(retAddrReg);
2022 // Generate the machine instruction and its operands.
2023 // Use CALL for direct function calls; this optimistically assumes
2024 // the PC-relative address fits in the CALL address field (22 bits).
2025 // Use JMPL for indirect calls.
2027 if (isa<Function>(callee))
2028 { // direct function call
2029 M = new MachineInstr(CALL);
2030 M->SetMachineOperandVal(0, MachineOperand::MO_PCRelativeDisp,
2034 { // indirect function call
2035 M = new MachineInstr(JMPLCALL);
2036 M->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister,
2038 M->SetMachineOperandConst(1, MachineOperand::MO_SignExtendedImmed,
2040 M->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister,
2046 // WARNING: Operands 0..N-1 must go in slots 0..N-1 of implicitUses.
2047 // The result value must go in slot N. This is assumed
2048 // in register allocation.
2050 // Add the call operands and return value as implicit refs
2051 for (unsigned i=0, N=callInstr->getNumOperands(); i < N; ++i)
2052 if (callInstr->getOperand(i) != callee)
2053 mvec.back()->addImplicitRef(callInstr->getOperand(i));
2055 if (callInstr->getType() != Type::VoidTy)
2056 mvec.back()->addImplicitRef(callInstr, /*isDef*/ true);
2058 // For the CALL instruction, the ret. addr. reg. is also implicit
2059 if (isa<Function>(callee))
2060 mvec.back()->addImplicitRef(retAddrReg, /*isDef*/ true);
2063 mvec.push_back(new MachineInstr(NOP));
2067 case 62: // reg: Shl(reg, reg)
2068 { const Type* opType = subtreeRoot->leftChild()->getValue()->getType();
2069 assert(opType->isIntegral()
2070 || opType == Type::BoolTy
2071 || opType->isPointerType()&& "Shl unsupported for other types");
2072 mvec.push_back(new MachineInstr((opType == Type::LongTy)? SLLX : SLL));
2073 Set3OperandsFromInstr(mvec.back(), subtreeRoot, target);
2077 case 63: // reg: Shr(reg, reg)
2078 { const Type* opType = subtreeRoot->leftChild()->getValue()->getType();
2079 assert(opType->isIntegral()
2080 || opType == Type::BoolTy
2081 || opType->isPointerType() &&"Shr unsupported for other types");
2082 mvec.push_back(new MachineInstr((opType->isSigned()
2083 ? ((opType == Type::LongTy)? SRAX : SRA)
2084 : ((opType == Type::LongTy)? SRLX : SRL))));
2085 Set3OperandsFromInstr(mvec.back(), subtreeRoot, target);
2089 case 64: // reg: Phi(reg,reg)
2090 break; // don't forward the value
2092 #undef NEED_PHI_MACHINE_INSTRS
2093 #ifdef NEED_PHI_MACHINE_INSTRS
2094 { // This instruction has variable #operands, so resultPos is 0.
2095 Instruction* phi = subtreeRoot->getInstruction();
2096 M = new MachineInstr(PHI, 1 + phi->getNumOperands());
2097 M->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister,
2098 subtreeRoot->getValue());
2099 for (unsigned i=0, N=phi->getNumOperands(); i < N; i++)
2100 M->SetMachineOperandVal(i+1, MachineOperand::MO_VirtualRegister,
2101 phi->getOperand(i));
2105 #endif // NEED_PHI_MACHINE_INSTRS
2108 case 71: // reg: VReg
2109 case 72: // reg: Constant
2110 break; // don't forward the value
2113 assert(0 && "Unrecognized BURG rule");
2118 if (forwardOperandNum >= 0)
2119 { // We did not generate a machine instruction but need to use operand.
2120 // If user is in the same tree, replace Value in its machine operand.
2121 // If not, insert a copy instruction which should get coalesced away
2122 // by register allocation.
2123 if (subtreeRoot->parent() != NULL)
2124 ForwardOperand(subtreeRoot, subtreeRoot->parent(), forwardOperandNum);
2127 vector<MachineInstr*> minstrVec;
2128 target.getInstrInfo().CreateCopyInstructionsByType(target,
2129 subtreeRoot->getInstruction()->getParent()->getParent(),
2130 subtreeRoot->getInstruction()->getOperand(forwardOperandNum),
2131 subtreeRoot->getInstruction(), minstrVec);
2132 assert(minstrVec.size() > 0);
2133 mvec.insert(mvec.end(), minstrVec.begin(), minstrVec.end());