2 //***************************************************************************
4 // SparcInstrSelection.cpp
7 // BURS instruction selection for SPARC V9 architecture.
10 // 7/02/01 - Vikram Adve - Created
11 //**************************************************************************/
13 #include "SparcInternals.h"
14 #include "SparcInstrSelectionSupport.h"
15 #include "SparcRegClassInfo.h"
16 #include "llvm/CodeGen/InstrSelectionSupport.h"
17 #include "llvm/CodeGen/MachineInstr.h"
18 #include "llvm/CodeGen/MachineInstrAnnot.h"
19 #include "llvm/CodeGen/InstrForest.h"
20 #include "llvm/CodeGen/InstrSelection.h"
21 #include "llvm/CodeGen/MachineCodeForMethod.h"
22 #include "llvm/CodeGen/MachineCodeForInstruction.h"
23 #include "llvm/DerivedTypes.h"
24 #include "llvm/iTerminators.h"
25 #include "llvm/iMemory.h"
26 #include "llvm/iOther.h"
27 #include "llvm/BasicBlock.h"
28 #include "llvm/Function.h"
29 #include "llvm/Constants.h"
30 #include "Support/MathExtras.h"
34 //************************* Forward Declarations ***************************/
37 static void SetMemOperands_Internal (vector<MachineInstr*>& mvec,
38 vector<MachineInstr*>::iterator mvecI,
39 const InstructionNode* vmInstrNode,
41 std::vector<Value*>& idxVec,
42 bool allConstantIndices,
43 const TargetMachine& target);
46 //************************ Internal Functions ******************************/
49 static inline MachineOpCode
50 ChooseBprInstruction(const InstructionNode* instrNode)
54 Instruction* setCCInstr =
55 ((InstructionNode*) instrNode->leftChild())->getInstruction();
57 switch(setCCInstr->getOpcode())
59 case Instruction::SetEQ: opCode = BRZ; break;
60 case Instruction::SetNE: opCode = BRNZ; break;
61 case Instruction::SetLE: opCode = BRLEZ; break;
62 case Instruction::SetGE: opCode = BRGEZ; break;
63 case Instruction::SetLT: opCode = BRLZ; break;
64 case Instruction::SetGT: opCode = BRGZ; break;
66 assert(0 && "Unrecognized VM instruction!");
67 opCode = INVALID_OPCODE;
75 static inline MachineOpCode
76 ChooseBpccInstruction(const InstructionNode* instrNode,
77 const BinaryOperator* setCCInstr)
79 MachineOpCode opCode = INVALID_OPCODE;
81 bool isSigned = setCCInstr->getOperand(0)->getType()->isSigned();
85 switch(setCCInstr->getOpcode())
87 case Instruction::SetEQ: opCode = BE; break;
88 case Instruction::SetNE: opCode = BNE; break;
89 case Instruction::SetLE: opCode = BLE; break;
90 case Instruction::SetGE: opCode = BGE; break;
91 case Instruction::SetLT: opCode = BL; break;
92 case Instruction::SetGT: opCode = BG; break;
94 assert(0 && "Unrecognized VM instruction!");
100 switch(setCCInstr->getOpcode())
102 case Instruction::SetEQ: opCode = BE; break;
103 case Instruction::SetNE: opCode = BNE; break;
104 case Instruction::SetLE: opCode = BLEU; break;
105 case Instruction::SetGE: opCode = BCC; break;
106 case Instruction::SetLT: opCode = BCS; break;
107 case Instruction::SetGT: opCode = BGU; break;
109 assert(0 && "Unrecognized VM instruction!");
117 static inline MachineOpCode
118 ChooseBFpccInstruction(const InstructionNode* instrNode,
119 const BinaryOperator* setCCInstr)
121 MachineOpCode opCode = INVALID_OPCODE;
123 switch(setCCInstr->getOpcode())
125 case Instruction::SetEQ: opCode = FBE; break;
126 case Instruction::SetNE: opCode = FBNE; break;
127 case Instruction::SetLE: opCode = FBLE; break;
128 case Instruction::SetGE: opCode = FBGE; break;
129 case Instruction::SetLT: opCode = FBL; break;
130 case Instruction::SetGT: opCode = FBG; break;
132 assert(0 && "Unrecognized VM instruction!");
140 // Create a unique TmpInstruction for a boolean value,
141 // representing the CC register used by a branch on that value.
142 // For now, hack this using a little static cache of TmpInstructions.
143 // Eventually the entire BURG instruction selection should be put
144 // into a separate class that can hold such information.
145 // The static cache is not too bad because the memory for these
146 // TmpInstructions will be freed along with the rest of the Function anyway.
148 static TmpInstruction*
149 GetTmpForCC(Value* boolVal, const Function *F, const Type* ccType)
151 typedef hash_map<const Value*, TmpInstruction*> BoolTmpCache;
152 static BoolTmpCache boolToTmpCache; // Map boolVal -> TmpInstruction*
153 static const Function *lastFunction = 0;// Use to flush cache between funcs
155 assert(boolVal->getType() == Type::BoolTy && "Weird but ok! Delete assert");
157 if (lastFunction != F)
160 boolToTmpCache.clear();
163 // Look for tmpI and create a new one otherwise. The new value is
164 // directly written to map using the ref returned by operator[].
165 TmpInstruction*& tmpI = boolToTmpCache[boolVal];
167 tmpI = new TmpInstruction(ccType, boolVal);
173 static inline MachineOpCode
174 ChooseBccInstruction(const InstructionNode* instrNode,
177 InstructionNode* setCCNode = (InstructionNode*) instrNode->leftChild();
178 BinaryOperator* setCCInstr = (BinaryOperator*) setCCNode->getInstruction();
179 const Type* setCCType = setCCInstr->getOperand(0)->getType();
181 isFPBranch = setCCType->isFloatingPoint(); // Return value: don't delete!
184 return ChooseBFpccInstruction(instrNode, setCCInstr);
186 return ChooseBpccInstruction(instrNode, setCCInstr);
190 static inline MachineOpCode
191 ChooseMovFpccInstruction(const InstructionNode* instrNode)
193 MachineOpCode opCode = INVALID_OPCODE;
195 switch(instrNode->getInstruction()->getOpcode())
197 case Instruction::SetEQ: opCode = MOVFE; break;
198 case Instruction::SetNE: opCode = MOVFNE; break;
199 case Instruction::SetLE: opCode = MOVFLE; break;
200 case Instruction::SetGE: opCode = MOVFGE; break;
201 case Instruction::SetLT: opCode = MOVFL; break;
202 case Instruction::SetGT: opCode = MOVFG; break;
204 assert(0 && "Unrecognized VM instruction!");
212 // Assumes that SUBcc v1, v2 -> v3 has been executed.
213 // In most cases, we want to clear v3 and then follow it by instruction
215 // Set mustClearReg=false if v3 need not be cleared before conditional move.
216 // Set valueToMove=0 if we want to conditionally move 0 instead of 1
217 // (i.e., we want to test inverse of a condition)
218 // (The latter two cases do not seem to arise because SetNE needs nothing.)
221 ChooseMovpccAfterSub(const InstructionNode* instrNode,
225 MachineOpCode opCode = INVALID_OPCODE;
229 switch(instrNode->getInstruction()->getOpcode())
231 case Instruction::SetEQ: opCode = MOVE; break;
232 case Instruction::SetLE: opCode = MOVLE; break;
233 case Instruction::SetGE: opCode = MOVGE; break;
234 case Instruction::SetLT: opCode = MOVL; break;
235 case Instruction::SetGT: opCode = MOVG; break;
236 case Instruction::SetNE: assert(0 && "No move required!"); break;
237 default: assert(0 && "Unrecognized VM instr!"); break;
243 static inline MachineOpCode
244 ChooseConvertToFloatInstr(OpLabel vopCode, const Type* opType)
246 MachineOpCode opCode = INVALID_OPCODE;
251 if (opType == Type::SByteTy || opType == Type::ShortTy || opType == Type::IntTy)
253 else if (opType == Type::LongTy)
255 else if (opType == Type::DoubleTy)
257 else if (opType == Type::FloatTy)
260 assert(0 && "Cannot convert this type to FLOAT on SPARC");
264 // This is usually used in conjunction with CreateCodeToCopyIntToFloat().
265 // Both functions should treat the integer as a 32-bit value for types
266 // of 4 bytes or less, and as a 64-bit value otherwise.
267 if (opType == Type::SByteTy || opType == Type::UByteTy ||
268 opType == Type::ShortTy || opType == Type::UShortTy ||
269 opType == Type::IntTy || opType == Type::UIntTy)
271 else if (opType == Type::LongTy || opType == Type::ULongTy)
273 else if (opType == Type::FloatTy)
275 else if (opType == Type::DoubleTy)
278 assert(0 && "Cannot convert this type to DOUBLE on SPARC");
288 static inline MachineOpCode
289 ChooseConvertToIntInstr(Type::PrimitiveID tid, const Type* opType)
291 MachineOpCode opCode = INVALID_OPCODE;;
293 if (tid==Type::SByteTyID || tid==Type::ShortTyID || tid==Type::IntTyID ||
294 tid==Type::UByteTyID || tid==Type::UShortTyID || tid==Type::UIntTyID)
296 switch (opType->getPrimitiveID())
298 case Type::FloatTyID: opCode = FSTOI; break;
299 case Type::DoubleTyID: opCode = FDTOI; break;
301 assert(0 && "Non-numeric non-bool type cannot be converted to Int");
305 else if (tid==Type::LongTyID || tid==Type::ULongTyID)
307 switch (opType->getPrimitiveID())
309 case Type::FloatTyID: opCode = FSTOX; break;
310 case Type::DoubleTyID: opCode = FDTOX; break;
312 assert(0 && "Non-numeric non-bool type cannot be converted to Long");
317 assert(0 && "Should not get here, Mo!");
323 CreateConvertToIntInstr(Type::PrimitiveID destTID, Value* srcVal,Value* destVal)
325 MachineOpCode opCode = ChooseConvertToIntInstr(destTID, srcVal->getType());
326 assert(opCode != INVALID_OPCODE && "Expected to need conversion!");
328 MachineInstr* M = new MachineInstr(opCode);
329 M->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister, srcVal);
330 M->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister, destVal);
334 // CreateCodeToConvertIntToFloat: Convert FP value to signed or unsigned integer
335 // The FP value must be converted to the dest type in an FP register,
336 // and the result is then copied from FP to int register via memory.
338 CreateCodeToConvertIntToFloat (const TargetMachine& target,
341 std::vector<MachineInstr*>& mvec,
342 MachineCodeForInstruction& mcfi)
344 // Create a temporary to represent the FP register into which the
345 // int value will placed after conversion. The type of this temporary
346 // depends on the type of FP register to use: single-prec for a 32-bit
347 // int or smaller; double-prec for a 64-bit int.
349 const Type* destTypeToUse = (destI->getType() == Type::LongTy)? Type::DoubleTy
351 Value* destForCast = new TmpInstruction(destTypeToUse, opVal);
352 mcfi.addTemp(destForCast);
354 // Create the fp-to-int conversion code
355 MachineInstr* M = CreateConvertToIntInstr(destI->getType()->getPrimitiveID(),
359 // Create the fpreg-to-intreg copy code
360 target.getInstrInfo().
361 CreateCodeToCopyFloatToInt(target, destI->getParent()->getParent(),
362 (TmpInstruction*)destForCast, destI, mvec, mcfi);
366 static inline MachineOpCode
367 ChooseAddInstruction(const InstructionNode* instrNode)
369 return ChooseAddInstructionByType(instrNode->getInstruction()->getType());
373 static inline MachineInstr*
374 CreateMovFloatInstruction(const InstructionNode* instrNode,
375 const Type* resultType)
377 MachineInstr* minstr = new MachineInstr((resultType == Type::FloatTy)
379 minstr->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister,
380 instrNode->leftChild()->getValue());
381 minstr->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister,
382 instrNode->getValue());
386 static inline MachineInstr*
387 CreateAddConstInstruction(const InstructionNode* instrNode)
389 MachineInstr* minstr = NULL;
391 Value* constOp = ((InstrTreeNode*) instrNode->rightChild())->getValue();
392 assert(isa<Constant>(constOp));
394 // Cases worth optimizing are:
395 // (1) Add with 0 for float or double: use an FMOV of appropriate type,
396 // instead of an FADD (1 vs 3 cycles). There is no integer MOV.
398 if (ConstantFP *FPC = dyn_cast<ConstantFP>(constOp)) {
399 double dval = FPC->getValue();
401 minstr = CreateMovFloatInstruction(instrNode,
402 instrNode->getInstruction()->getType());
409 static inline MachineOpCode
410 ChooseSubInstructionByType(const Type* resultType)
412 MachineOpCode opCode = INVALID_OPCODE;
414 if (resultType->isIntegral() || isa<PointerType>(resultType))
419 switch(resultType->getPrimitiveID())
421 case Type::FloatTyID: opCode = FSUBS; break;
422 case Type::DoubleTyID: opCode = FSUBD; break;
423 default: assert(0 && "Invalid type for SUB instruction"); break;
430 static inline MachineInstr*
431 CreateSubConstInstruction(const InstructionNode* instrNode)
433 MachineInstr* minstr = NULL;
435 Value* constOp = ((InstrTreeNode*) instrNode->rightChild())->getValue();
436 assert(isa<Constant>(constOp));
438 // Cases worth optimizing are:
439 // (1) Sub with 0 for float or double: use an FMOV of appropriate type,
440 // instead of an FSUB (1 vs 3 cycles). There is no integer MOV.
442 if (ConstantFP *FPC = dyn_cast<ConstantFP>(constOp)) {
443 double dval = FPC->getValue();
445 minstr = CreateMovFloatInstruction(instrNode,
446 instrNode->getInstruction()->getType());
453 static inline MachineOpCode
454 ChooseFcmpInstruction(const InstructionNode* instrNode)
456 MachineOpCode opCode = INVALID_OPCODE;
458 Value* operand = ((InstrTreeNode*) instrNode->leftChild())->getValue();
459 switch(operand->getType()->getPrimitiveID()) {
460 case Type::FloatTyID: opCode = FCMPS; break;
461 case Type::DoubleTyID: opCode = FCMPD; break;
462 default: assert(0 && "Invalid type for FCMP instruction"); break;
469 // Assumes that leftArg and rightArg are both cast instructions.
472 BothFloatToDouble(const InstructionNode* instrNode)
474 InstrTreeNode* leftArg = instrNode->leftChild();
475 InstrTreeNode* rightArg = instrNode->rightChild();
476 InstrTreeNode* leftArgArg = leftArg->leftChild();
477 InstrTreeNode* rightArgArg = rightArg->leftChild();
478 assert(leftArg->getValue()->getType() == rightArg->getValue()->getType());
480 // Check if both arguments are floats cast to double
481 return (leftArg->getValue()->getType() == Type::DoubleTy &&
482 leftArgArg->getValue()->getType() == Type::FloatTy &&
483 rightArgArg->getValue()->getType() == Type::FloatTy);
487 static inline MachineOpCode
488 ChooseMulInstructionByType(const Type* resultType)
490 MachineOpCode opCode = INVALID_OPCODE;
492 if (resultType->isIntegral())
495 switch(resultType->getPrimitiveID())
497 case Type::FloatTyID: opCode = FMULS; break;
498 case Type::DoubleTyID: opCode = FMULD; break;
499 default: assert(0 && "Invalid type for MUL instruction"); break;
507 static inline MachineInstr*
508 CreateIntNegInstruction(const TargetMachine& target,
511 MachineInstr* minstr = new MachineInstr(SUB);
512 minstr->SetMachineOperandReg(0, target.getRegInfo().getZeroRegNum());
513 minstr->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister, vreg);
514 minstr->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister, vreg);
519 // Create instruction sequence for any shift operation.
520 // SLL or SLLX on an operand smaller than the integer reg. size (64bits)
521 // requires a second instruction for explicit sign-extension.
522 // Note that we only have to worry about a sign-bit appearing in the
523 // most significant bit of the operand after shifting (e.g., bit 32 of
524 // Int or bit 16 of Short), so we do not have to worry about results
525 // that are as large as a normal integer register.
528 CreateShiftInstructions(const TargetMachine& target,
530 MachineOpCode shiftOpCode,
532 Value* optArgVal2, /* Use optArgVal2 if not NULL */
533 unsigned int optShiftNum, /* else use optShiftNum */
534 Instruction* destVal,
535 vector<MachineInstr*>& mvec,
536 MachineCodeForInstruction& mcfi)
538 assert((optArgVal2 != NULL || optShiftNum <= 64) &&
539 "Large shift sizes unexpected, but can be handled below: "
540 "You need to check whether or not it fits in immed field below");
542 // If this is a logical left shift of a type smaller than the standard
543 // integer reg. size, we have to extend the sign-bit into upper bits
544 // of dest, so we need to put the result of the SLL into a temporary.
546 Value* shiftDest = destVal;
547 const Type* opType = argVal1->getType();
548 unsigned opSize = target.DataLayout.getTypeSize(argVal1->getType());
549 if ((shiftOpCode == SLL || shiftOpCode == SLLX)
550 && opSize < target.DataLayout.getIntegerRegize())
551 { // put SLL result into a temporary
552 shiftDest = new TmpInstruction(argVal1, optArgVal2, "sllTmp");
553 mcfi.addTemp(shiftDest);
556 MachineInstr* M = (optArgVal2 != NULL)
557 ? Create3OperandInstr(shiftOpCode, argVal1, optArgVal2, shiftDest)
558 : Create3OperandInstr_UImmed(shiftOpCode, argVal1, optShiftNum, shiftDest);
561 if (shiftDest != destVal)
562 { // extend the sign-bit of the result into all upper bits of dest
563 assert(8*opSize <= 32 && "Unexpected type size > 4 and < IntRegSize?");
564 target.getInstrInfo().
565 CreateSignExtensionInstructions(target, F, shiftDest, 8*opSize,
566 destVal, mvec, mcfi);
571 // Does not create any instructions if we cannot exploit constant to
572 // create a cheaper instruction.
573 // This returns the approximate cost of the instructions generated,
574 // which is used to pick the cheapest when both operands are constant.
575 static inline unsigned int
576 CreateMulConstInstruction(const TargetMachine &target, Function* F,
577 Value* lval, Value* rval, Instruction* destVal,
578 vector<MachineInstr*>& mvec,
579 MachineCodeForInstruction& mcfi)
581 /* Use max. multiply cost, viz., cost of MULX */
582 unsigned int cost = target.getInstrInfo().minLatency(MULX);
583 unsigned int firstNewInstr = mvec.size();
585 Value* constOp = rval;
586 if (! isa<Constant>(constOp))
589 // Cases worth optimizing are:
590 // (1) Multiply by 0 or 1 for any type: replace with copy (ADD or FMOV)
591 // (2) Multiply by 2^x for integer types: replace with Shift
593 const Type* resultType = destVal->getType();
595 if (resultType->isIntegral() || isa<PointerType>(resultType))
598 int64_t C = GetConstantValueAsSignedInt(constOp, isValidConst);
602 bool needNeg = false;
609 if (C == 0 || C == 1)
611 cost = target.getInstrInfo().minLatency(ADD);
612 MachineInstr* M = (C == 0)
613 ? Create3OperandInstr_Reg(ADD,
614 target.getRegInfo().getZeroRegNum(),
615 target.getRegInfo().getZeroRegNum(),
617 : Create3OperandInstr_Reg(ADD, lval,
618 target.getRegInfo().getZeroRegNum(),
622 else if (isPowerOf2(C, pow))
624 unsigned int opSize = target.DataLayout.getTypeSize(resultType);
625 MachineOpCode opCode = (opSize <= 32)? SLL : SLLX;
626 CreateShiftInstructions(target, F, opCode, lval, NULL, pow,
627 destVal, mvec, mcfi);
630 if (mvec.size() > 0 && needNeg)
631 { // insert <reg = SUB 0, reg> after the instr to flip the sign
632 MachineInstr* M = CreateIntNegInstruction(target, destVal);
639 if (ConstantFP *FPC = dyn_cast<ConstantFP>(constOp))
641 double dval = FPC->getValue();
644 MachineOpCode opCode = (dval < 0)
645 ? (resultType == Type::FloatTy? FNEGS : FNEGD)
646 : (resultType == Type::FloatTy? FMOVS : FMOVD);
647 MachineInstr* M = Create2OperandInstr(opCode, lval, destVal);
653 if (firstNewInstr < mvec.size())
656 for (unsigned int i=firstNewInstr; i < mvec.size(); ++i)
657 cost += target.getInstrInfo().minLatency(mvec[i]->getOpCode());
664 // Does not create any instructions if we cannot exploit constant to
665 // create a cheaper instruction.
668 CreateCheapestMulConstInstruction(const TargetMachine &target,
670 Value* lval, Value* rval,
671 Instruction* destVal,
672 vector<MachineInstr*>& mvec,
673 MachineCodeForInstruction& mcfi)
676 if (isa<Constant>(lval) && isa<Constant>(rval))
677 { // both operands are constant: try both orders!
678 vector<MachineInstr*> mvec1, mvec2;
679 unsigned int lcost = CreateMulConstInstruction(target, F, lval, rval,
680 destVal, mvec1, mcfi);
681 unsigned int rcost = CreateMulConstInstruction(target, F, rval, lval,
682 destVal, mvec2, mcfi);
683 vector<MachineInstr*>& mincostMvec = (lcost <= rcost)? mvec1 : mvec2;
684 vector<MachineInstr*>& maxcostMvec = (lcost <= rcost)? mvec2 : mvec1;
685 mvec.insert(mvec.end(), mincostMvec.begin(), mincostMvec.end());
687 for (unsigned int i=0; i < maxcostMvec.size(); ++i)
688 delete maxcostMvec[i];
690 else if (isa<Constant>(rval)) // rval is constant, but not lval
691 CreateMulConstInstruction(target, F, lval, rval, destVal, mvec, mcfi);
692 else if (isa<Constant>(lval)) // lval is constant, but not rval
693 CreateMulConstInstruction(target, F, lval, rval, destVal, mvec, mcfi);
695 // else neither is constant
699 // Return NULL if we cannot exploit constant to create a cheaper instruction
701 CreateMulInstruction(const TargetMachine &target, Function* F,
702 Value* lval, Value* rval, Instruction* destVal,
703 vector<MachineInstr*>& mvec,
704 MachineCodeForInstruction& mcfi,
705 MachineOpCode forceMulOp = INVALID_MACHINE_OPCODE)
707 unsigned int L = mvec.size();
708 CreateCheapestMulConstInstruction(target,F, lval, rval, destVal, mvec, mcfi);
709 if (mvec.size() == L)
710 { // no instructions were added so create MUL reg, reg, reg.
711 // Use FSMULD if both operands are actually floats cast to doubles.
712 // Otherwise, use the default opcode for the appropriate type.
713 MachineOpCode mulOp = ((forceMulOp != INVALID_MACHINE_OPCODE)
715 : ChooseMulInstructionByType(destVal->getType()));
716 MachineInstr* M = new MachineInstr(mulOp);
717 M->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister, lval);
718 M->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister, rval);
719 M->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister, destVal);
725 // Generate a divide instruction for Div or Rem.
726 // For Rem, this assumes that the operand type will be signed if the result
727 // type is signed. This is correct because they must have the same sign.
729 static inline MachineOpCode
730 ChooseDivInstruction(TargetMachine &target,
731 const InstructionNode* instrNode)
733 MachineOpCode opCode = INVALID_OPCODE;
735 const Type* resultType = instrNode->getInstruction()->getType();
737 if (resultType->isIntegral())
738 opCode = resultType->isSigned()? SDIVX : UDIVX;
740 switch(resultType->getPrimitiveID())
742 case Type::FloatTyID: opCode = FDIVS; break;
743 case Type::DoubleTyID: opCode = FDIVD; break;
744 default: assert(0 && "Invalid type for DIV instruction"); break;
751 // Return NULL if we cannot exploit constant to create a cheaper instruction
753 CreateDivConstInstruction(TargetMachine &target,
754 const InstructionNode* instrNode,
755 vector<MachineInstr*>& mvec)
757 MachineInstr* minstr1 = NULL;
758 MachineInstr* minstr2 = NULL;
760 Value* constOp = ((InstrTreeNode*) instrNode->rightChild())->getValue();
761 if (! isa<Constant>(constOp))
764 // Cases worth optimizing are:
765 // (1) Divide by 1 for any type: replace with copy (ADD or FMOV)
766 // (2) Divide by 2^x for integer types: replace with SR[L or A]{X}
768 const Type* resultType = instrNode->getInstruction()->getType();
770 if (resultType->isIntegral())
774 int64_t C = GetConstantValueAsSignedInt(constOp, isValidConst);
777 bool needNeg = false;
786 minstr1 = new MachineInstr(ADD);
787 minstr1->SetMachineOperandVal(0,
788 MachineOperand::MO_VirtualRegister,
789 instrNode->leftChild()->getValue());
790 minstr1->SetMachineOperandReg(1,
791 target.getRegInfo().getZeroRegNum());
793 else if (isPowerOf2(C, pow))
795 MachineOpCode opCode= ((resultType->isSigned())
796 ? (resultType==Type::LongTy)? SRAX : SRA
797 : (resultType==Type::LongTy)? SRLX : SRL);
798 minstr1 = new MachineInstr(opCode);
799 minstr1->SetMachineOperandVal(0,
800 MachineOperand::MO_VirtualRegister,
801 instrNode->leftChild()->getValue());
802 minstr1->SetMachineOperandConst(1,
803 MachineOperand::MO_UnextendedImmed,
807 if (minstr1 && needNeg)
808 { // insert <reg = SUB 0, reg> after the instr to flip the sign
809 minstr2 = CreateIntNegInstruction(target,
810 instrNode->getValue());
816 if (ConstantFP *FPC = dyn_cast<ConstantFP>(constOp))
818 double dval = FPC->getValue();
821 bool needNeg = (dval < 0);
823 MachineOpCode opCode = needNeg
824 ? (resultType == Type::FloatTy? FNEGS : FNEGD)
825 : (resultType == Type::FloatTy? FMOVS : FMOVD);
827 minstr1 = new MachineInstr(opCode);
828 minstr1->SetMachineOperandVal(0,
829 MachineOperand::MO_VirtualRegister,
830 instrNode->leftChild()->getValue());
836 minstr1->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister,
837 instrNode->getValue());
840 mvec.push_back(minstr1);
842 mvec.push_back(minstr2);
847 CreateCodeForVariableSizeAlloca(const TargetMachine& target,
850 Value* numElementsVal,
851 vector<MachineInstr*>& getMvec)
855 // Create a Value to hold the (constant) element size
856 Value* tsizeVal = ConstantSInt::get(Type::IntTy, tsize);
858 // Get the constant offset from SP for dynamically allocated storage
859 // and create a temporary Value to hold it.
860 assert(result && result->getParent() && "Result value is not part of a fn?");
861 Function *F = result->getParent()->getParent();
862 MachineCodeForMethod& mcInfo = MachineCodeForMethod::get(F);
864 ConstantSInt* dynamicAreaOffset =
865 ConstantSInt::get(Type::IntTy,
866 target.getFrameInfo().getDynamicAreaOffset(mcInfo,growUp));
867 assert(! growUp && "Has SPARC v9 stack frame convention changed?");
869 // Create a temporary value to hold the result of MUL
870 TmpInstruction* tmpProd = new TmpInstruction(numElementsVal, tsizeVal);
871 MachineCodeForInstruction::get(result).addTemp(tmpProd);
873 // Instruction 1: mul numElements, typeSize -> tmpProd
874 M = new MachineInstr(MULX);
875 M->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister, numElementsVal);
876 M->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister, tsizeVal);
877 M->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister, tmpProd);
878 getMvec.push_back(M);
880 // Instruction 2: sub %sp, tmpProd -> %sp
881 M = new MachineInstr(SUB);
882 M->SetMachineOperandReg(0, target.getRegInfo().getStackPointer());
883 M->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister, tmpProd);
884 M->SetMachineOperandReg(2, target.getRegInfo().getStackPointer());
885 getMvec.push_back(M);
887 // Instruction 3: add %sp, frameSizeBelowDynamicArea -> result
888 M = new MachineInstr(ADD);
889 M->SetMachineOperandReg(0, target.getRegInfo().getStackPointer());
890 M->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister, dynamicAreaOffset);
891 M->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister, result);
892 getMvec.push_back(M);
897 CreateCodeForFixedSizeAlloca(const TargetMachine& target,
900 unsigned int numElements,
901 vector<MachineInstr*>& getMvec)
903 assert(result && result->getParent() &&
904 "Result value is not part of a function?");
905 Function *F = result->getParent()->getParent();
906 MachineCodeForMethod &mcInfo = MachineCodeForMethod::get(F);
908 // Check if the offset would small enough to use as an immediate in
909 // load/stores (check LDX because all load/stores have the same-size immediate
910 // field). If not, put the variable in the dynamically sized area of the
912 unsigned int paddedSizeIgnored;
913 int offsetFromFP = mcInfo.computeOffsetforLocalVar(target, result,
915 tsize * numElements);
916 if (! target.getInstrInfo().constantFitsInImmedField(LDX, offsetFromFP))
918 CreateCodeForVariableSizeAlloca(target, result, tsize,
919 ConstantSInt::get(Type::IntTy,numElements),
924 // else offset fits in immediate field so go ahead and allocate it.
925 offsetFromFP = mcInfo.allocateLocalVar(target, result, tsize * numElements);
927 // Create a temporary Value to hold the constant offset.
928 // This is needed because it may not fit in the immediate field.
929 ConstantSInt* offsetVal = ConstantSInt::get(Type::IntTy, offsetFromFP);
931 // Instruction 1: add %fp, offsetFromFP -> result
932 MachineInstr* M = new MachineInstr(ADD);
933 M->SetMachineOperandReg(0, target.getRegInfo().getFramePointer());
934 M->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister, offsetVal);
935 M->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister, result);
937 getMvec.push_back(M);
942 // Check for a constant (uint) 0.
946 return (isa<ConstantInt>(idx) && cast<ConstantInt>(idx)->isNullValue());
950 //------------------------------------------------------------------------
951 // Function SetOperandsForMemInstr
953 // Choose addressing mode for the given load or store instruction.
954 // Use [reg+reg] if it is an indexed reference, and the index offset is
955 // not a constant or if it cannot fit in the offset field.
956 // Use [reg+offset] in all other cases.
958 // This assumes that all array refs are "lowered" to one of these forms:
959 // %x = load (subarray*) ptr, constant ; single constant offset
960 // %x = load (subarray*) ptr, offsetVal ; single non-constant offset
961 // Generally, this should happen via strength reduction + LICM.
962 // Also, strength reduction should take care of using the same register for
963 // the loop index variable and an array index, when that is profitable.
964 //------------------------------------------------------------------------
967 SetOperandsForMemInstr(vector<MachineInstr*>& mvec,
968 vector<MachineInstr*>::iterator mvecI,
969 const InstructionNode* vmInstrNode,
970 const TargetMachine& target)
972 MemAccessInst* memInst = (MemAccessInst*) vmInstrNode->getInstruction();
974 // Variables to hold the index vector and ptr value.
975 // The major work here is to extract these for all 3 instruction types
976 // and to try to fold chains of constant indices into a single offset.
977 // After that, we call SetMemOperands_Internal(), which creates the
978 // appropriate operands for the machine instruction.
979 vector<Value*> idxVec;
980 bool allConstantIndices = true;
981 Value* ptrVal = memInst->getPointerOperand();
983 // If there is a GetElemPtr instruction to fold in to this instr,
984 // it must be in the left child for Load and GetElemPtr, and in the
985 // right child for Store instructions.
986 InstrTreeNode* ptrChild = (vmInstrNode->getOpLabel() == Instruction::Store
987 ? vmInstrNode->rightChild()
988 : vmInstrNode->leftChild());
990 // Check if all indices are constant for this instruction
991 for (MemAccessInst::op_iterator OI=memInst->idx_begin(),OE=memInst->idx_end();
992 allConstantIndices && OI != OE; ++OI)
993 if (! isa<Constant>(*OI))
994 allConstantIndices = false;
996 // If we have only constant indices, fold chains of constant indices
997 // in this and any preceding GetElemPtr instructions.
998 if (allConstantIndices &&
999 (ptrChild->getOpLabel() == Instruction::GetElementPtr ||
1000 ptrChild->getOpLabel() == GetElemPtrIdx))
1001 if (Value* newPtr = FoldGetElemChain((InstructionNode*) ptrChild, idxVec))
1004 // Append the index vector of the current instruction, if any.
1005 // Discard any leading [0] index.
1006 if (memInst->getNumIndices() > 0)
1007 idxVec.insert(idxVec.end(),
1008 memInst->idx_begin() + IsZero(*memInst->idx_begin()),
1009 memInst->idx_end());
1011 // Now create the appropriate operands for the machine instruction
1012 SetMemOperands_Internal(mvec, mvecI, vmInstrNode,
1013 ptrVal, idxVec, allConstantIndices, target);
1017 // Generate the correct operands (and additional instructions if needed)
1018 // for the given pointer and given index vector.
1021 SetMemOperands_Internal(vector<MachineInstr*>& mvec,
1022 vector<MachineInstr*>::iterator mvecI,
1023 const InstructionNode* vmInstrNode,
1025 vector<Value*>& idxVec,
1026 bool allConstantIndices,
1027 const TargetMachine& target)
1029 MemAccessInst* memInst = (MemAccessInst*) vmInstrNode->getInstruction();
1031 // Initialize so we default to storing the offset in a register.
1032 int64_t smallConstOffset = 0;
1033 Value* valueForRegOffset = NULL;
1034 MachineOperand::MachineOperandType offsetOpType =
1035 MachineOperand::MO_VirtualRegister;
1037 // Check if there is an index vector and if so, compute the
1038 // right offset for structures and for arrays
1040 if (idxVec.size() > 0)
1042 const PointerType* ptrType = cast<PointerType>(ptrVal->getType());
1044 // If all indices are constant, compute the combined offset directly.
1045 if (allConstantIndices)
1047 // Compute the offset value using the index vector. Create a
1048 // virtual reg. for it since it may not fit in the immed field.
1049 uint64_t offset = target.DataLayout.getIndexedOffset(ptrType,idxVec);
1050 valueForRegOffset = ConstantSInt::get(Type::LongTy, offset);
1054 // There is at least one non-constant offset. Therefore, this must
1055 // be an array ref, and must have been lowered to a single non-zero
1056 // offset. (An extra leading zero offset, if any, can be ignored.)
1057 // Generate code sequence to compute address from index.
1059 assert(idxVec.size() == 1U + IsZero(idxVec[0])
1060 && "Array refs must be lowered before Instruction Selection");
1062 Value* idxVal = idxVec[IsZero(idxVec[0])];
1064 vector<MachineInstr*> mulVec;
1065 Instruction* addr = new TmpInstruction(Type::UIntTy, memInst);
1066 MachineCodeForInstruction::get(memInst).addTemp(addr);
1068 // The call to getTypeSize() will fail if size is not constant.
1069 unsigned int eltSize =
1070 target.DataLayout.getTypeSize(ptrType->getElementType());
1071 assert(eltSize > 0 && "Invalid or non-const array element size");
1072 ConstantUInt* eltVal = ConstantUInt::get(Type::UIntTy, eltSize);
1074 // CreateMulInstruction() folds constants intelligently enough.
1075 CreateMulInstruction(target,
1076 memInst->getParent()->getParent(),
1077 idxVal, /* lval, not likely const */
1078 eltVal, /* rval, likely constant */
1081 MachineCodeForInstruction::get(memInst),
1082 INVALID_MACHINE_OPCODE);
1084 // Insert mulVec[] before *mvecI in mvec[] and update mvecI
1085 // to point to the same instruction it pointed to before.
1086 assert(mulVec.size() > 0 && "No multiply code created?");
1087 vector<MachineInstr*>::iterator oldMvecI = mvecI;
1088 for (unsigned i=0, N=mulVec.size(); i < N; ++i)
1089 mvecI = mvec.insert(mvecI, mulVec[i]) + 1; // pts to mem instr
1091 valueForRegOffset = addr;
1096 offsetOpType = MachineOperand::MO_SignExtendedImmed;
1097 smallConstOffset = 0;
1101 // Operand 0 is value, operand 1 is ptr, operand 2 is offset
1102 // For LOAD or GET_ELEMENT_PTR,
1103 // Operand 0 is ptr, operand 1 is offset, operand 2 is result.
1105 unsigned offsetOpNum, ptrOpNum;
1106 if (memInst->getOpcode() == Instruction::Store)
1108 (*mvecI)->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister,
1109 vmInstrNode->leftChild()->getValue());
1117 (*mvecI)->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister,
1121 (*mvecI)->SetMachineOperandVal(ptrOpNum, MachineOperand::MO_VirtualRegister,
1124 if (offsetOpType == MachineOperand::MO_VirtualRegister)
1126 assert(valueForRegOffset != NULL);
1127 (*mvecI)->SetMachineOperandVal(offsetOpNum, offsetOpType,
1131 (*mvecI)->SetMachineOperandConst(offsetOpNum, offsetOpType,
1137 // Substitute operand `operandNum' of the instruction in node `treeNode'
1138 // in place of the use(s) of that instruction in node `parent'.
1139 // Check both explicit and implicit operands!
1140 // Also make sure to skip over a parent who:
1141 // (1) is a list node in the Burg tree, or
1142 // (2) itself had its results forwarded to its parent
1145 ForwardOperand(InstructionNode* treeNode,
1146 InstrTreeNode* parent,
1149 assert(treeNode && parent && "Invalid invocation of ForwardOperand");
1151 Instruction* unusedOp = treeNode->getInstruction();
1152 Value* fwdOp = unusedOp->getOperand(operandNum);
1154 // The parent itself may be a list node, so find the real parent instruction
1155 while (parent->getNodeType() != InstrTreeNode::NTInstructionNode)
1157 parent = parent->parent();
1158 assert(parent && "ERROR: Non-instruction node has no parent in tree.");
1160 InstructionNode* parentInstrNode = (InstructionNode*) parent;
1162 Instruction* userInstr = parentInstrNode->getInstruction();
1163 MachineCodeForInstruction &mvec = MachineCodeForInstruction::get(userInstr);
1165 // The parent's mvec would be empty if it was itself forwarded.
1166 // Recursively call ForwardOperand in that case...
1168 if (mvec.size() == 0)
1170 assert(parent->parent() != NULL &&
1171 "Parent could not have been forwarded, yet has no instructions?");
1172 ForwardOperand(treeNode, parent->parent(), operandNum);
1176 for (unsigned i=0, N=mvec.size(); i < N; i++)
1178 MachineInstr* minstr = mvec[i];
1179 for (unsigned i=0, numOps=minstr->getNumOperands(); i < numOps; ++i)
1181 const MachineOperand& mop = minstr->getOperand(i);
1182 if (mop.getOperandType() == MachineOperand::MO_VirtualRegister &&
1183 mop.getVRegValue() == unusedOp)
1184 minstr->SetMachineOperandVal(i,
1185 MachineOperand::MO_VirtualRegister, fwdOp);
1188 for (unsigned i=0,numOps=minstr->getNumImplicitRefs(); i<numOps; ++i)
1189 if (minstr->getImplicitRef(i) == unusedOp)
1190 minstr->setImplicitRef(i, fwdOp,
1191 minstr->implicitRefIsDefined(i),
1192 minstr->implicitRefIsDefinedAndUsed(i));
1199 AllUsesAreBranches(const Instruction* setccI)
1201 for (Value::use_const_iterator UI=setccI->use_begin(), UE=setccI->use_end();
1203 if (! isa<TmpInstruction>(*UI) // ignore tmp instructions here
1204 && cast<Instruction>(*UI)->getOpcode() != Instruction::Br)
1209 //******************* Externally Visible Functions *************************/
1211 //------------------------------------------------------------------------
1212 // External Function: ThisIsAChainRule
1215 // Check if a given BURG rule is a chain rule.
1216 //------------------------------------------------------------------------
1219 ThisIsAChainRule(int eruleno)
1223 case 111: // stmt: reg
1224 case 113: // stmt: bool
1247 return false; break;
1252 //------------------------------------------------------------------------
1253 // External Function: GetInstructionsByRule
1256 // Choose machine instructions for the SPARC according to the
1257 // patterns chosen by the BURG-generated parser.
1258 //------------------------------------------------------------------------
1261 GetInstructionsByRule(InstructionNode* subtreeRoot,
1264 TargetMachine &target,
1265 vector<MachineInstr*>& mvec)
1267 bool checkCast = false; // initialize here to use fall-through
1269 int forwardOperandNum = -1;
1270 unsigned int allocaSize = 0;
1271 MachineInstr* M, *M2;
1276 // If the code for this instruction was folded into the parent (user),
1278 if (subtreeRoot->isFoldedIntoParent())
1282 // Let's check for chain rules outside the switch so that we don't have
1283 // to duplicate the list of chain rule production numbers here again
1285 if (ThisIsAChainRule(ruleForNode))
1287 // Chain rules have a single nonterminal on the RHS.
1288 // Get the rule that matches the RHS non-terminal and use that instead.
1290 assert(nts[0] && ! nts[1]
1291 && "A chain rule should have only one RHS non-terminal!");
1292 nextRule = burm_rule(subtreeRoot->state, nts[0]);
1293 nts = burm_nts[nextRule];
1294 GetInstructionsByRule(subtreeRoot, nextRule, nts, target, mvec);
1298 switch(ruleForNode) {
1299 case 1: // stmt: Ret
1300 case 2: // stmt: RetValue(reg)
1301 { // NOTE: Prepass of register allocation is responsible
1302 // for moving return value to appropriate register.
1303 // Mark the return-address register as a hidden virtual reg.
1304 // Mark the return value register as an implicit ref of
1305 // the machine instruction.
1306 // Finally put a NOP in the delay slot.
1307 ReturnInst *returnInstr =
1308 cast<ReturnInst>(subtreeRoot->getInstruction());
1309 assert(returnInstr->getOpcode() == Instruction::Ret);
1311 Instruction* returnReg = new TmpInstruction(returnInstr);
1312 MachineCodeForInstruction::get(returnInstr).addTemp(returnReg);
1314 M = new MachineInstr(JMPLRET);
1315 M->SetMachineOperandReg(0, MachineOperand::MO_VirtualRegister,
1317 M->SetMachineOperandConst(1,MachineOperand::MO_SignExtendedImmed,
1319 M->SetMachineOperandReg(2, target.getRegInfo().getZeroRegNum());
1321 if (returnInstr->getReturnValue() != NULL)
1322 M->addImplicitRef(returnInstr->getReturnValue());
1325 mvec.push_back(new MachineInstr(NOP));
1330 case 3: // stmt: Store(reg,reg)
1331 case 4: // stmt: Store(reg,ptrreg)
1332 mvec.push_back(new MachineInstr(
1333 ChooseStoreInstruction(
1334 subtreeRoot->leftChild()->getValue()->getType())));
1335 SetOperandsForMemInstr(mvec, mvec.end()-1, subtreeRoot, target);
1338 case 5: // stmt: BrUncond
1339 M = new MachineInstr(BA);
1340 M->SetMachineOperandVal(0, MachineOperand::MO_PCRelativeDisp,
1341 cast<BranchInst>(subtreeRoot->getInstruction())->getSuccessor(0));
1345 mvec.push_back(new MachineInstr(NOP));
1348 case 206: // stmt: BrCond(setCCconst)
1349 { // setCCconst => boolean was computed with `%b = setCC type reg1 const'
1350 // If the constant is ZERO, we can use the branch-on-integer-register
1351 // instructions and avoid the SUBcc instruction entirely.
1352 // Otherwise this is just the same as case 5, so just fall through.
1354 InstrTreeNode* constNode = subtreeRoot->leftChild()->rightChild();
1356 constNode->getNodeType() ==InstrTreeNode::NTConstNode);
1357 Constant *constVal = cast<Constant>(constNode->getValue());
1360 if ((constVal->getType()->isIntegral()
1361 || isa<PointerType>(constVal->getType()))
1362 && GetConstantValueAsSignedInt(constVal, isValidConst) == 0
1365 // That constant is a zero after all...
1366 // Use the left child of setCC as the first argument!
1367 // Mark the setCC node so that no code is generated for it.
1368 InstructionNode* setCCNode = (InstructionNode*)
1369 subtreeRoot->leftChild();
1370 assert(setCCNode->getOpLabel() == SetCCOp);
1371 setCCNode->markFoldedIntoParent();
1373 BranchInst* brInst=cast<BranchInst>(subtreeRoot->getInstruction());
1375 M = new MachineInstr(ChooseBprInstruction(subtreeRoot));
1376 M->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister,
1377 setCCNode->leftChild()->getValue());
1378 M->SetMachineOperandVal(1, MachineOperand::MO_PCRelativeDisp,
1379 brInst->getSuccessor(0));
1383 mvec.push_back(new MachineInstr(NOP));
1386 M = new MachineInstr(BA);
1387 M->SetMachineOperandVal(0, MachineOperand::MO_PCRelativeDisp,
1388 brInst->getSuccessor(1));
1392 mvec.push_back(new MachineInstr(NOP));
1396 // ELSE FALL THROUGH
1399 case 6: // stmt: BrCond(bool)
1400 { // bool => boolean was computed with some boolean operator
1401 // (SetCC, Not, ...). We need to check whether the type was a FP,
1402 // signed int or unsigned int, and check the branching condition in
1403 // order to choose the branch to use.
1404 // If it is an integer CC, we also need to find the unique
1405 // TmpInstruction representing that CC.
1407 BranchInst* brInst = cast<BranchInst>(subtreeRoot->getInstruction());
1409 M = new MachineInstr(ChooseBccInstruction(subtreeRoot, isFPBranch));
1411 Value* ccValue = GetTmpForCC(subtreeRoot->leftChild()->getValue(),
1412 brInst->getParent()->getParent(),
1413 isFPBranch? Type::FloatTy : Type::IntTy);
1415 M->SetMachineOperandVal(0, MachineOperand::MO_CCRegister, ccValue);
1416 M->SetMachineOperandVal(1, MachineOperand::MO_PCRelativeDisp,
1417 brInst->getSuccessor(0));
1421 mvec.push_back(new MachineInstr(NOP));
1424 M = new MachineInstr(BA);
1425 M->SetMachineOperandVal(0, MachineOperand::MO_PCRelativeDisp,
1426 brInst->getSuccessor(1));
1430 mvec.push_back(new MachineInstr(NOP));
1434 case 208: // stmt: BrCond(boolconst)
1436 // boolconst => boolean is a constant; use BA to first or second label
1437 Constant* constVal =
1438 cast<Constant>(subtreeRoot->leftChild()->getValue());
1439 unsigned dest = cast<ConstantBool>(constVal)->getValue()? 0 : 1;
1441 M = new MachineInstr(BA);
1442 M->SetMachineOperandVal(0, MachineOperand::MO_PCRelativeDisp,
1443 cast<BranchInst>(subtreeRoot->getInstruction())->getSuccessor(dest));
1447 mvec.push_back(new MachineInstr(NOP));
1451 case 8: // stmt: BrCond(boolreg)
1452 { // boolreg => boolean is stored in an existing register.
1453 // Just use the branch-on-integer-register instruction!
1455 M = new MachineInstr(BRNZ);
1456 M->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister,
1457 subtreeRoot->leftChild()->getValue());
1458 M->SetMachineOperandVal(1, MachineOperand::MO_PCRelativeDisp,
1459 cast<BranchInst>(subtreeRoot->getInstruction())->getSuccessor(0));
1463 mvec.push_back(new MachineInstr(NOP));
1466 M = new MachineInstr(BA);
1467 M->SetMachineOperandVal(0, MachineOperand::MO_PCRelativeDisp,
1468 cast<BranchInst>(subtreeRoot->getInstruction())->getSuccessor(1));
1472 mvec.push_back(new MachineInstr(NOP));
1476 case 9: // stmt: Switch(reg)
1477 assert(0 && "*** SWITCH instruction is not implemented yet.");
1480 case 10: // reg: VRegList(reg, reg)
1481 assert(0 && "VRegList should never be the topmost non-chain rule");
1484 case 21: // bool: Not(bool): Both these are implemented as:
1485 case 421: // reg: BNot(reg) : reg = reg XOR-NOT 0
1486 M = new MachineInstr(XNOR);
1487 M->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister,
1488 subtreeRoot->leftChild()->getValue());
1489 M->SetMachineOperandReg(1, target.getRegInfo().getZeroRegNum());
1490 M->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister,
1491 subtreeRoot->getValue());
1495 case 322: // reg: ToBoolTy(bool):
1496 case 22: // reg: ToBoolTy(reg):
1498 const Type* opType = subtreeRoot->leftChild()->getValue()->getType();
1499 assert(opType->isIntegral() || isa<PointerType>(opType)
1500 || opType == Type::BoolTy);
1501 forwardOperandNum = 0; // forward first operand to user
1505 case 23: // reg: ToUByteTy(reg)
1506 case 25: // reg: ToUShortTy(reg)
1507 case 27: // reg: ToUIntTy(reg)
1508 case 29: // reg: ToULongTy(reg)
1510 Instruction* destI = subtreeRoot->getInstruction();
1511 Value* opVal = subtreeRoot->leftChild()->getValue();
1512 const Type* opType = subtreeRoot->leftChild()->getValue()->getType();
1513 if (opType->isIntegral()
1514 || isa<PointerType>(opType)
1515 || opType == Type::BoolTy)
1517 unsigned opSize = target.DataLayout.getTypeSize(opType);
1518 unsigned destSize = target.DataLayout.getTypeSize(destI->getType());
1519 if (opSize > destSize ||
1521 && destSize < target.DataLayout.getIntegerRegize()))
1522 { // operand is larger than dest,
1523 // OR both are equal but smaller than the full register size
1524 // AND operand is signed, so it may have extra sign bits:
1525 // mask high bits using AND
1526 M = Create3OperandInstr(AND, opVal,
1527 ConstantUInt::get(Type::ULongTy,
1528 ((uint64_t) 1 << 8*destSize) - 1),
1533 forwardOperandNum = 0; // forward first operand to user
1535 else if (opType->isFloatingPoint())
1536 CreateCodeToConvertIntToFloat(target, opVal, destI, mvec,
1537 MachineCodeForInstruction::get(destI));
1539 assert(0 && "Unrecognized operand type for convert-to-unsigned");
1544 case 24: // reg: ToSByteTy(reg)
1545 case 26: // reg: ToShortTy(reg)
1546 case 28: // reg: ToIntTy(reg)
1547 case 30: // reg: ToLongTy(reg)
1549 Instruction* destI = subtreeRoot->getInstruction();
1550 Value* opVal = subtreeRoot->leftChild()->getValue();
1551 MachineCodeForInstruction& mcfi =MachineCodeForInstruction::get(destI);
1553 const Type* opType = opVal->getType();
1554 if (opType->isIntegral()
1555 || isa<PointerType>(opType)
1556 || opType == Type::BoolTy)
1558 // These operand types have the same format as the destination,
1559 // but may have different size: add sign bits or mask as needed.
1561 const Type* destType = destI->getType();
1562 unsigned opSize = target.DataLayout.getTypeSize(opType);
1563 unsigned destSize = target.DataLayout.getTypeSize(destType);
1564 if (opSize < destSize && !opType->isSigned())
1565 { // operand is unsigned and smaller than dest: sign-extend
1566 target.getInstrInfo().CreateSignExtensionInstructions(target, destI->getParent()->getParent(), opVal, 8*opSize, destI, mvec, mcfi);
1568 else if (opSize > destSize)
1569 { // operand is larger than dest: mask high bits using AND
1570 // and then sign-extend using SRA by 0!
1572 TmpInstruction *tmpI = new TmpInstruction(destType, opVal,
1575 M = Create3OperandInstr(AND, opVal,
1576 ConstantUInt::get(Type::UIntTy,
1577 ((uint64_t) 1 << 8*destSize)-1),
1581 target.getInstrInfo().CreateSignExtensionInstructions(target, destI->getParent()->getParent(), tmpI, 8*destSize, destI, mvec, mcfi);
1584 forwardOperandNum = 0; // forward first operand to user
1586 else if (opType->isFloatingPoint())
1587 CreateCodeToConvertIntToFloat(target, opVal, destI, mvec, mcfi);
1589 assert(0 && "Unrecognized operand type for convert-to-signed");
1594 case 31: // reg: ToFloatTy(reg):
1595 case 32: // reg: ToDoubleTy(reg):
1596 case 232: // reg: ToDoubleTy(Constant):
1598 // If this instruction has a parent (a user) in the tree
1599 // and the user is translated as an FsMULd instruction,
1600 // then the cast is unnecessary. So check that first.
1601 // In the future, we'll want to do the same for the FdMULq instruction,
1602 // so do the check here instead of only for ToFloatTy(reg).
1604 if (subtreeRoot->parent() != NULL &&
1605 MachineCodeForInstruction::get(((InstructionNode*)subtreeRoot->parent())->getInstruction())[0]->getOpCode() == FSMULD)
1607 forwardOperandNum = 0; // forward first operand to user
1611 Value* leftVal = subtreeRoot->leftChild()->getValue();
1612 const Type* opType = leftVal->getType();
1613 MachineOpCode opCode=ChooseConvertToFloatInstr(
1614 subtreeRoot->getOpLabel(), opType);
1615 if (opCode == INVALID_OPCODE) // no conversion needed
1617 forwardOperandNum = 0; // forward first operand to user
1621 // If the source operand is a non-FP type it must be
1622 // first copied from int to float register via memory!
1623 Instruction *dest = subtreeRoot->getInstruction();
1626 if (! opType->isFloatingPoint())
1628 // Create a temporary to represent the FP register
1629 // into which the integer will be copied via memory.
1630 // The type of this temporary will determine the FP
1631 // register used: single-prec for a 32-bit int or smaller,
1632 // double-prec for a 64-bit int.
1634 const Type* srcTypeToUse =
1635 (leftVal->getType() == Type::LongTy)? Type::DoubleTy
1638 srcForCast = new TmpInstruction(srcTypeToUse, dest);
1639 MachineCodeForInstruction &destMCFI =
1640 MachineCodeForInstruction::get(dest);
1641 destMCFI.addTemp(srcForCast);
1643 target.getInstrInfo().CreateCodeToCopyIntToFloat(target,
1644 dest->getParent()->getParent(),
1645 leftVal, (TmpInstruction*) srcForCast,
1649 srcForCast = leftVal;
1651 M = new MachineInstr(opCode);
1652 M->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister,
1654 M->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister,
1661 case 19: // reg: ToArrayTy(reg):
1662 case 20: // reg: ToPointerTy(reg):
1663 forwardOperandNum = 0; // forward first operand to user
1666 case 233: // reg: Add(reg, Constant)
1667 M = CreateAddConstInstruction(subtreeRoot);
1673 // ELSE FALL THROUGH
1675 case 33: // reg: Add(reg, reg)
1676 mvec.push_back(new MachineInstr(ChooseAddInstruction(subtreeRoot)));
1677 Set3OperandsFromInstr(mvec.back(), subtreeRoot, target);
1680 case 234: // reg: Sub(reg, Constant)
1681 M = CreateSubConstInstruction(subtreeRoot);
1687 // ELSE FALL THROUGH
1689 case 34: // reg: Sub(reg, reg)
1690 mvec.push_back(new MachineInstr(ChooseSubInstructionByType(
1691 subtreeRoot->getInstruction()->getType())));
1692 Set3OperandsFromInstr(mvec.back(), subtreeRoot, target);
1695 case 135: // reg: Mul(todouble, todouble)
1699 case 35: // reg: Mul(reg, reg)
1701 MachineOpCode forceOp = ((checkCast && BothFloatToDouble(subtreeRoot))
1703 : INVALID_MACHINE_OPCODE);
1704 Instruction* mulInstr = subtreeRoot->getInstruction();
1705 CreateMulInstruction(target, mulInstr->getParent()->getParent(),
1706 subtreeRoot->leftChild()->getValue(),
1707 subtreeRoot->rightChild()->getValue(),
1709 MachineCodeForInstruction::get(mulInstr),forceOp);
1712 case 335: // reg: Mul(todouble, todoubleConst)
1716 case 235: // reg: Mul(reg, Constant)
1718 MachineOpCode forceOp = ((checkCast && BothFloatToDouble(subtreeRoot))
1720 : INVALID_MACHINE_OPCODE);
1721 Instruction* mulInstr = subtreeRoot->getInstruction();
1722 CreateMulInstruction(target, mulInstr->getParent()->getParent(),
1723 subtreeRoot->leftChild()->getValue(),
1724 subtreeRoot->rightChild()->getValue(),
1726 MachineCodeForInstruction::get(mulInstr),
1730 case 236: // reg: Div(reg, Constant)
1732 CreateDivConstInstruction(target, subtreeRoot, mvec);
1733 if (mvec.size() > L)
1735 // ELSE FALL THROUGH
1737 case 36: // reg: Div(reg, reg)
1738 mvec.push_back(new MachineInstr(ChooseDivInstruction(target, subtreeRoot)));
1739 Set3OperandsFromInstr(mvec.back(), subtreeRoot, target);
1742 case 37: // reg: Rem(reg, reg)
1743 case 237: // reg: Rem(reg, Constant)
1745 Instruction* remInstr = subtreeRoot->getInstruction();
1747 TmpInstruction* quot = new TmpInstruction(
1748 subtreeRoot->leftChild()->getValue(),
1749 subtreeRoot->rightChild()->getValue());
1750 TmpInstruction* prod = new TmpInstruction(
1752 subtreeRoot->rightChild()->getValue());
1753 MachineCodeForInstruction::get(remInstr).addTemp(quot).addTemp(prod);
1755 M = new MachineInstr(ChooseDivInstruction(target, subtreeRoot));
1756 Set3OperandsFromInstr(M, subtreeRoot, target);
1757 M->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister,quot);
1760 M = new MachineInstr(ChooseMulInstructionByType(
1761 subtreeRoot->getInstruction()->getType()));
1762 M->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister,quot);
1763 M->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister,
1764 subtreeRoot->rightChild()->getValue());
1765 M->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister,prod);
1768 M = new MachineInstr(ChooseSubInstructionByType(
1769 subtreeRoot->getInstruction()->getType()));
1770 Set3OperandsFromInstr(M, subtreeRoot, target);
1771 M->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister,prod);
1777 case 38: // bool: And(bool, bool)
1778 case 238: // bool: And(bool, boolconst)
1779 case 338: // reg : BAnd(reg, reg)
1780 case 538: // reg : BAnd(reg, Constant)
1781 mvec.push_back(new MachineInstr(AND));
1782 Set3OperandsFromInstr(mvec.back(), subtreeRoot, target);
1785 case 138: // bool: And(bool, not)
1786 case 438: // bool: BAnd(bool, not)
1787 mvec.push_back(new MachineInstr(ANDN));
1788 Set3OperandsFromInstr(mvec.back(), subtreeRoot, target);
1791 case 39: // bool: Or(bool, bool)
1792 case 239: // bool: Or(bool, boolconst)
1793 case 339: // reg : BOr(reg, reg)
1794 case 539: // reg : BOr(reg, Constant)
1795 mvec.push_back(new MachineInstr(OR));
1796 Set3OperandsFromInstr(mvec.back(), subtreeRoot, target);
1799 case 139: // bool: Or(bool, not)
1800 case 439: // bool: BOr(bool, not)
1801 mvec.push_back(new MachineInstr(ORN));
1802 Set3OperandsFromInstr(mvec.back(), subtreeRoot, target);
1805 case 40: // bool: Xor(bool, bool)
1806 case 240: // bool: Xor(bool, boolconst)
1807 case 340: // reg : BXor(reg, reg)
1808 case 540: // reg : BXor(reg, Constant)
1809 mvec.push_back(new MachineInstr(XOR));
1810 Set3OperandsFromInstr(mvec.back(), subtreeRoot, target);
1813 case 140: // bool: Xor(bool, not)
1814 case 440: // bool: BXor(bool, not)
1815 mvec.push_back(new MachineInstr(XNOR));
1816 Set3OperandsFromInstr(mvec.back(), subtreeRoot, target);
1819 case 41: // boolconst: SetCC(reg, Constant)
1821 // If the SetCC was folded into the user (parent), it will be
1822 // caught above. All other cases are the same as case 42,
1823 // so just fall through.
1825 case 42: // bool: SetCC(reg, reg):
1827 // This generates a SUBCC instruction, putting the difference in
1828 // a result register, and setting a condition code.
1830 // If the boolean result of the SetCC is used by anything other
1831 // than a branch instruction, or if it is used outside the current
1832 // basic block, the boolean must be
1833 // computed and stored in the result register. Otherwise, discard
1834 // the difference (by using %g0) and keep only the condition code.
1836 // To compute the boolean result in a register we use a conditional
1837 // move, unless the result of the SUBCC instruction can be used as
1838 // the bool! This assumes that zero is FALSE and any non-zero
1841 InstructionNode* parentNode = (InstructionNode*) subtreeRoot->parent();
1842 Instruction* setCCInstr = subtreeRoot->getInstruction();
1844 bool keepBoolVal = parentNode == NULL ||
1845 ! AllUsesAreBranches(setCCInstr);
1846 bool subValIsBoolVal = setCCInstr->getOpcode() == Instruction::SetNE;
1847 bool keepSubVal = keepBoolVal && subValIsBoolVal;
1848 bool computeBoolVal = keepBoolVal && ! subValIsBoolVal;
1852 MachineOpCode movOpCode = 0;
1854 // Mark the 4th operand as being a CC register, and as a def
1855 // A TmpInstruction is created to represent the CC "result".
1856 // Unlike other instances of TmpInstruction, this one is used
1857 // by machine code of multiple LLVM instructions, viz.,
1858 // the SetCC and the branch. Make sure to get the same one!
1859 // Note that we do this even for FP CC registers even though they
1860 // are explicit operands, because the type of the operand
1861 // needs to be a floating point condition code, not an integer
1862 // condition code. Think of this as casting the bool result to
1863 // a FP condition code register.
1865 Value* leftVal = subtreeRoot->leftChild()->getValue();
1866 bool isFPCompare = leftVal->getType()->isFloatingPoint();
1868 TmpInstruction* tmpForCC = GetTmpForCC(setCCInstr,
1869 setCCInstr->getParent()->getParent(),
1870 isFPCompare ? Type::FloatTy : Type::IntTy);
1871 MachineCodeForInstruction::get(setCCInstr).addTemp(tmpForCC);
1875 // Integer condition: dest. should be %g0 or an integer register.
1876 // If result must be saved but condition is not SetEQ then we need
1877 // a separate instruction to compute the bool result, so discard
1878 // result of SUBcc instruction anyway.
1880 M = new MachineInstr(SUBcc);
1881 Set3OperandsFromInstr(M, subtreeRoot, target, ! keepSubVal);
1882 M->SetMachineOperandVal(3, MachineOperand::MO_CCRegister,
1883 tmpForCC, /*def*/true);
1887 { // recompute bool using the integer condition codes
1889 ChooseMovpccAfterSub(subtreeRoot,mustClearReg,valueToMove);
1894 // FP condition: dest of FCMP should be some FCCn register
1895 M = new MachineInstr(ChooseFcmpInstruction(subtreeRoot));
1896 M->SetMachineOperandVal(0, MachineOperand::MO_CCRegister,
1898 M->SetMachineOperandVal(1,MachineOperand::MO_VirtualRegister,
1899 subtreeRoot->leftChild()->getValue());
1900 M->SetMachineOperandVal(2,MachineOperand::MO_VirtualRegister,
1901 subtreeRoot->rightChild()->getValue());
1905 {// recompute bool using the FP condition codes
1906 mustClearReg = true;
1908 movOpCode = ChooseMovFpccInstruction(subtreeRoot);
1915 {// Unconditionally set register to 0
1916 M = new MachineInstr(SETHI);
1917 M->SetMachineOperandConst(0,MachineOperand::MO_UnextendedImmed,
1919 M->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister,
1924 // Now conditionally move `valueToMove' (0 or 1) into the register
1925 // Mark the register as a use (as well as a def) because the old
1926 // value should be retained if the condition is false.
1927 M = new MachineInstr(movOpCode);
1928 M->SetMachineOperandVal(0, MachineOperand::MO_CCRegister,
1930 M->SetMachineOperandConst(1, MachineOperand::MO_UnextendedImmed,
1932 M->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister,
1933 setCCInstr, /*isDef*/ true,
1934 /*isDefAndUse*/ true);
1940 case 43: // boolreg: VReg
1941 case 44: // boolreg: Constant
1944 case 51: // reg: Load(reg)
1945 case 52: // reg: Load(ptrreg)
1946 case 53: // reg: LoadIdx(reg,reg)
1947 case 54: // reg: LoadIdx(ptrreg,reg)
1948 mvec.push_back(new MachineInstr(ChooseLoadInstruction(
1949 subtreeRoot->getValue()->getType())));
1950 SetOperandsForMemInstr(mvec, mvec.end()-1, subtreeRoot, target);
1953 case 55: // reg: GetElemPtr(reg)
1954 case 56: // reg: GetElemPtrIdx(reg,reg)
1955 // If the GetElemPtr was folded into the user (parent), it will be
1956 // caught above. For other cases, we have to compute the address.
1957 mvec.push_back(new MachineInstr(ADD));
1958 SetOperandsForMemInstr(mvec, mvec.end()-1, subtreeRoot, target);
1961 case 57: // reg: Alloca: Implement as 1 instruction:
1962 { // add %fp, offsetFromFP -> result
1963 AllocationInst* instr =
1964 cast<AllocationInst>(subtreeRoot->getInstruction());
1965 unsigned int tsize =
1966 target.findOptimalStorageSize(instr->getAllocatedType());
1968 CreateCodeForFixedSizeAlloca(target, instr, tsize, 1, mvec);
1972 case 58: // reg: Alloca(reg): Implement as 3 instructions:
1973 // mul num, typeSz -> tmp
1974 // sub %sp, tmp -> %sp
1975 { // add %sp, frameSizeBelowDynamicArea -> result
1976 AllocationInst* instr =
1977 cast<AllocationInst>(subtreeRoot->getInstruction());
1978 const Type* eltType = instr->getAllocatedType();
1980 // If #elements is constant, use simpler code for fixed-size allocas
1981 int tsize = (int) target.findOptimalStorageSize(eltType);
1982 Value* numElementsVal = NULL;
1983 bool isArray = instr->isArrayAllocation();
1986 isa<Constant>(numElementsVal = instr->getArraySize()))
1987 { // total size is constant: generate code for fixed-size alloca
1988 unsigned int numElements = isArray?
1989 cast<ConstantUInt>(numElementsVal)->getValue() : 1;
1990 CreateCodeForFixedSizeAlloca(target, instr, tsize,
1993 else // total size is not constant.
1994 CreateCodeForVariableSizeAlloca(target, instr, tsize,
1995 numElementsVal, mvec);
1999 case 61: // reg: Call
2000 { // Generate a direct (CALL) or indirect (JMPL). depending
2001 // Mark the return-address register and the indirection
2002 // register (if any) as hidden virtual registers.
2003 // Also, mark the operands of the Call and return value (if
2004 // any) as implicit operands of the CALL machine instruction.
2006 // If this is a varargs function, floating point arguments
2007 // have to passed in integer registers so insert
2008 // copy-float-to-int instructions for each float operand.
2010 CallInst *callInstr = cast<CallInst>(subtreeRoot->getInstruction());
2011 Value *callee = callInstr->getCalledValue();
2013 // Create hidden virtual register for return address, with type void*.
2014 TmpInstruction* retAddrReg =
2015 new TmpInstruction(PointerType::get(Type::VoidTy), callInstr);
2016 MachineCodeForInstruction::get(callInstr).addTemp(retAddrReg);
2018 // Generate the machine instruction and its operands.
2019 // Use CALL for direct function calls; this optimistically assumes
2020 // the PC-relative address fits in the CALL address field (22 bits).
2021 // Use JMPL for indirect calls.
2023 if (isa<Function>(callee))
2024 { // direct function call
2025 M = new MachineInstr(CALL);
2026 M->SetMachineOperandVal(0, MachineOperand::MO_PCRelativeDisp,
2030 { // indirect function call
2031 M = new MachineInstr(JMPLCALL);
2032 M->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister,
2034 M->SetMachineOperandConst(1, MachineOperand::MO_SignExtendedImmed,
2036 M->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister,
2042 const FunctionType* funcType =
2043 cast<FunctionType>(cast<PointerType>(callee->getType())
2044 ->getElementType());
2045 bool isVarArgs = funcType->isVarArg();
2046 bool noPrototype = isVarArgs && funcType->getNumParams() == 0;
2048 // Use an annotation to pass information about call arguments
2049 // to the register allocator.
2050 CallArgsDescriptor* argDesc = new CallArgsDescriptor(callInstr,
2051 retAddrReg, isVarArgs, noPrototype);
2052 M->addAnnotation(argDesc);
2054 assert(callInstr->getOperand(0) == callee
2055 && "This is assumed in the loop below!");
2057 for (unsigned i=1, N=callInstr->getNumOperands(); i < N; ++i)
2059 Value* argVal = callInstr->getOperand(i);
2060 Instruction* intArgReg = NULL;
2062 // Check for FP arguments to varargs functions.
2063 // Any such argument in the first $K$ args must be passed in an
2064 // integer register, where K = #integer argument registers.
2065 if (isVarArgs && argVal->getType()->isFloatingPoint())
2067 // If it is a function with no prototype, pass value
2068 // as an FP value as well as a varargs value
2070 argDesc->getArgInfo(i-1).setUseFPArgReg();
2072 // If this arg. is in the first $K$ regs, add a copy
2073 // float-to-int instruction to pass the value as an integer.
2074 if (i < target.getRegInfo().GetNumOfIntArgRegs())
2076 MachineCodeForInstruction &destMCFI =
2077 MachineCodeForInstruction::get(callInstr);
2078 intArgReg = new TmpInstruction(Type::IntTy, argVal);
2079 destMCFI.addTemp(intArgReg);
2081 vector<MachineInstr*> copyMvec;
2082 target.getInstrInfo().CreateCodeToCopyFloatToInt(target,
2083 callInstr->getParent()->getParent(),
2084 argVal, (TmpInstruction*) intArgReg,
2085 copyMvec, destMCFI);
2086 mvec.insert(mvec.begin(),copyMvec.begin(),copyMvec.end());
2088 argDesc->getArgInfo(i-1).setUseIntArgReg();
2089 argDesc->getArgInfo(i-1).setArgCopy(intArgReg);
2092 // Cannot fit in first $K$ regs so pass the arg on the stack
2093 argDesc->getArgInfo(i-1).setUseStackSlot();
2097 mvec.back()->addImplicitRef(intArgReg);
2099 mvec.back()->addImplicitRef(argVal);
2102 // Add the return value as an implicit ref. The call operands
2103 // were added above.
2104 if (callInstr->getType() != Type::VoidTy)
2105 mvec.back()->addImplicitRef(callInstr, /*isDef*/ true);
2107 // For the CALL instruction, the ret. addr. reg. is also implicit
2108 if (isa<Function>(callee))
2109 mvec.back()->addImplicitRef(retAddrReg, /*isDef*/ true);
2112 mvec.push_back(new MachineInstr(NOP));
2116 case 62: // reg: Shl(reg, reg)
2118 Value* argVal1 = subtreeRoot->leftChild()->getValue();
2119 Value* argVal2 = subtreeRoot->rightChild()->getValue();
2120 Instruction* shlInstr = subtreeRoot->getInstruction();
2122 const Type* opType = argVal1->getType();
2123 assert(opType->isIntegral()
2124 || opType == Type::BoolTy
2125 || isa<PointerType>(opType)&&"Shl unsupported for other types");
2127 CreateShiftInstructions(target, shlInstr->getParent()->getParent(),
2128 (opType == Type::LongTy)? SLLX : SLL,
2129 argVal1, argVal2, 0, shlInstr, mvec,
2130 MachineCodeForInstruction::get(shlInstr));
2134 case 63: // reg: Shr(reg, reg)
2135 { const Type* opType = subtreeRoot->leftChild()->getValue()->getType();
2136 assert(opType->isIntegral()
2137 || isa<PointerType>(opType)&&"Shr unsupported for other types");
2138 mvec.push_back(new MachineInstr((opType->isSigned()
2139 ? ((opType == Type::LongTy)? SRAX : SRA)
2140 : ((opType == Type::LongTy)? SRLX : SRL))));
2141 Set3OperandsFromInstr(mvec.back(), subtreeRoot, target);
2145 case 64: // reg: Phi(reg,reg)
2146 break; // don't forward the value
2148 #undef NEED_PHI_MACHINE_INSTRS
2149 #ifdef NEED_PHI_MACHINE_INSTRS
2150 { // This instruction has variable #operands, so resultPos is 0.
2151 Instruction* phi = subtreeRoot->getInstruction();
2152 M = new MachineInstr(PHI, 1 + phi->getNumOperands());
2153 M->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister,
2154 subtreeRoot->getValue());
2155 for (unsigned i=0, N=phi->getNumOperands(); i < N; i++)
2156 M->SetMachineOperandVal(i+1, MachineOperand::MO_VirtualRegister,
2157 phi->getOperand(i));
2161 #endif // NEED_PHI_MACHINE_INSTRS
2164 case 71: // reg: VReg
2165 case 72: // reg: Constant
2166 break; // don't forward the value
2169 assert(0 && "Unrecognized BURG rule");
2174 if (forwardOperandNum >= 0)
2175 { // We did not generate a machine instruction but need to use operand.
2176 // If user is in the same tree, replace Value in its machine operand.
2177 // If not, insert a copy instruction which should get coalesced away
2178 // by register allocation.
2179 if (subtreeRoot->parent() != NULL)
2180 ForwardOperand(subtreeRoot, subtreeRoot->parent(), forwardOperandNum);
2183 vector<MachineInstr*> minstrVec;
2184 Instruction* instr = subtreeRoot->getInstruction();
2185 target.getInstrInfo().
2186 CreateCopyInstructionsByType(target,
2187 instr->getParent()->getParent(),
2188 instr->getOperand(forwardOperandNum),
2190 MachineCodeForInstruction::get(instr));
2191 assert(minstrVec.size() > 0);
2192 mvec.insert(mvec.end(), minstrVec.begin(), minstrVec.end());