2 //***************************************************************************
4 // SparcInstrSelection.cpp
7 // BURS instruction selection for SPARC V9 architecture.
10 // 7/02/01 - Vikram Adve - Created
11 //**************************************************************************/
13 #include "SparcInternals.h"
14 #include "SparcInstrSelectionSupport.h"
15 #include "llvm/CodeGen/InstrSelectionSupport.h"
16 #include "llvm/CodeGen/MachineInstr.h"
17 #include "llvm/CodeGen/InstrForest.h"
18 #include "llvm/CodeGen/InstrSelection.h"
19 #include "llvm/DerivedTypes.h"
20 #include "llvm/iTerminators.h"
21 #include "llvm/iMemory.h"
22 #include "llvm/iOther.h"
23 #include "llvm/BasicBlock.h"
24 #include "llvm/Method.h"
25 #include "llvm/ConstPoolVals.h"
26 #include "Support/MathExtras.h"
30 //************************* Forward Declarations ***************************/
33 static void SetMemOperands_Internal (MachineInstr* minstr,
34 const InstructionNode* vmInstrNode,
36 Value* arrayOffsetVal,
37 const vector<ConstPoolVal*>& idxVec,
38 const TargetMachine& target);
41 //************************ Internal Functions ******************************/
44 static inline MachineOpCode
45 ChooseBprInstruction(const InstructionNode* instrNode)
49 Instruction* setCCInstr =
50 ((InstructionNode*) instrNode->leftChild())->getInstruction();
52 switch(setCCInstr->getOpcode())
54 case Instruction::SetEQ: opCode = BRZ; break;
55 case Instruction::SetNE: opCode = BRNZ; break;
56 case Instruction::SetLE: opCode = BRLEZ; break;
57 case Instruction::SetGE: opCode = BRGEZ; break;
58 case Instruction::SetLT: opCode = BRLZ; break;
59 case Instruction::SetGT: opCode = BRGZ; break;
61 assert(0 && "Unrecognized VM instruction!");
62 opCode = INVALID_OPCODE;
70 static inline MachineOpCode
71 ChooseBpccInstruction(const InstructionNode* instrNode,
72 const BinaryOperator* setCCInstr)
74 MachineOpCode opCode = INVALID_OPCODE;
76 bool isSigned = setCCInstr->getOperand(0)->getType()->isSigned();
80 switch(setCCInstr->getOpcode())
82 case Instruction::SetEQ: opCode = BE; break;
83 case Instruction::SetNE: opCode = BNE; break;
84 case Instruction::SetLE: opCode = BLE; break;
85 case Instruction::SetGE: opCode = BGE; break;
86 case Instruction::SetLT: opCode = BL; break;
87 case Instruction::SetGT: opCode = BG; break;
89 assert(0 && "Unrecognized VM instruction!");
95 switch(setCCInstr->getOpcode())
97 case Instruction::SetEQ: opCode = BE; break;
98 case Instruction::SetNE: opCode = BNE; break;
99 case Instruction::SetLE: opCode = BLEU; break;
100 case Instruction::SetGE: opCode = BCC; break;
101 case Instruction::SetLT: opCode = BCS; break;
102 case Instruction::SetGT: opCode = BGU; break;
104 assert(0 && "Unrecognized VM instruction!");
112 static inline MachineOpCode
113 ChooseBFpccInstruction(const InstructionNode* instrNode,
114 const BinaryOperator* setCCInstr)
116 MachineOpCode opCode = INVALID_OPCODE;
118 switch(setCCInstr->getOpcode())
120 case Instruction::SetEQ: opCode = FBE; break;
121 case Instruction::SetNE: opCode = FBNE; break;
122 case Instruction::SetLE: opCode = FBLE; break;
123 case Instruction::SetGE: opCode = FBGE; break;
124 case Instruction::SetLT: opCode = FBL; break;
125 case Instruction::SetGT: opCode = FBG; break;
127 assert(0 && "Unrecognized VM instruction!");
135 // Create a unique TmpInstruction for a boolean value,
136 // representing the CC register used by a branch on that value.
137 // For now, hack this using a little static cache of TmpInstructions.
138 // Eventually the entire BURG instruction selection should be put
139 // into a separate class that can hold such information.
140 // The static cache is not too bad because the memory for these
141 // TmpInstructions will be freed along with the rest of the Method anyway.
143 static TmpInstruction*
144 GetTmpForCC(Value* boolVal, const Method* method, const Type* ccType)
146 typedef hash_map<const Value*, TmpInstruction*> BoolTmpCache;
147 static BoolTmpCache boolToTmpCache; // Map boolVal -> TmpInstruction*
148 static const Method* lastMethod = NULL; // Use to flush cache between methods
150 assert(boolVal->getType() == Type::BoolTy && "Weird but ok! Delete assert");
152 if (lastMethod != method)
155 boolToTmpCache.clear();
158 // Look for tmpI and create a new one otherwise. The new value is
159 // directly written to map using the ref returned by operator[].
160 TmpInstruction*& tmpI = boolToTmpCache[boolVal];
162 tmpI = new TmpInstruction(TMP_INSTRUCTION_OPCODE, ccType, boolVal, NULL);
168 static inline MachineOpCode
169 ChooseBccInstruction(const InstructionNode* instrNode,
172 InstructionNode* setCCNode = (InstructionNode*) instrNode->leftChild();
173 BinaryOperator* setCCInstr = (BinaryOperator*) setCCNode->getInstruction();
174 const Type* setCCType = setCCInstr->getOperand(0)->getType();
176 isFPBranch = (setCCType == Type::FloatTy || setCCType == Type::DoubleTy);
179 return ChooseBFpccInstruction(instrNode, setCCInstr);
181 return ChooseBpccInstruction(instrNode, setCCInstr);
185 static inline MachineOpCode
186 ChooseMovFpccInstruction(const InstructionNode* instrNode)
188 MachineOpCode opCode = INVALID_OPCODE;
190 switch(instrNode->getInstruction()->getOpcode())
192 case Instruction::SetEQ: opCode = MOVFE; break;
193 case Instruction::SetNE: opCode = MOVFNE; break;
194 case Instruction::SetLE: opCode = MOVFLE; break;
195 case Instruction::SetGE: opCode = MOVFGE; break;
196 case Instruction::SetLT: opCode = MOVFL; break;
197 case Instruction::SetGT: opCode = MOVFG; break;
199 assert(0 && "Unrecognized VM instruction!");
207 // Assumes that SUBcc v1, v2 -> v3 has been executed.
208 // In most cases, we want to clear v3 and then follow it by instruction
210 // Set mustClearReg=false if v3 need not be cleared before conditional move.
211 // Set valueToMove=0 if we want to conditionally move 0 instead of 1
212 // (i.e., we want to test inverse of a condition)
213 // (The latter two cases do not seem to arise because SetNE needs nothing.)
216 ChooseMovpccAfterSub(const InstructionNode* instrNode,
220 MachineOpCode opCode = INVALID_OPCODE;
224 switch(instrNode->getInstruction()->getOpcode())
226 case Instruction::SetEQ: opCode = MOVE; break;
227 case Instruction::SetLE: opCode = MOVLE; break;
228 case Instruction::SetGE: opCode = MOVGE; break;
229 case Instruction::SetLT: opCode = MOVL; break;
230 case Instruction::SetGT: opCode = MOVG; break;
231 case Instruction::SetNE: assert(0 && "No move required!"); break;
232 default: assert(0 && "Unrecognized VM instr!"); break;
238 static inline MachineOpCode
239 ChooseConvertToFloatInstr(const InstructionNode* instrNode,
242 MachineOpCode opCode = INVALID_OPCODE;
244 switch(instrNode->getOpLabel())
247 if (opType == Type::SByteTy || opType == Type::ShortTy || opType == Type::IntTy)
249 else if (opType == Type::LongTy)
251 else if (opType == Type::DoubleTy)
253 else if (opType == Type::FloatTy)
256 assert(0 && "Cannot convert this type to FLOAT on SPARC");
260 // Use FXTOD for all integer-to-double conversions. This has to be
261 // consistent with the code in CreateCodeToCopyIntToFloat() since
262 // that will be used to load the integer into an FP register.
264 if (opType == Type::SByteTy || opType == Type::ShortTy ||
265 opType == Type::IntTy || opType == Type::LongTy)
267 else if (opType == Type::FloatTy)
269 else if (opType == Type::DoubleTy)
272 assert(0 && "Cannot convert this type to DOUBLE on SPARC");
282 static inline MachineOpCode
283 ChooseConvertToIntInstr(const InstructionNode* instrNode,
286 MachineOpCode opCode = INVALID_OPCODE;;
288 int instrType = (int) instrNode->getOpLabel();
290 if (instrType == ToSByteTy || instrType == ToShortTy || instrType == ToIntTy)
292 switch (opType->getPrimitiveID())
294 case Type::FloatTyID: opCode = FSTOI; break;
295 case Type::DoubleTyID: opCode = FDTOI; break;
297 assert(0 && "Non-numeric non-bool type cannot be converted to Int");
301 else if (instrType == ToLongTy)
303 switch (opType->getPrimitiveID())
305 case Type::FloatTyID: opCode = FSTOX; break;
306 case Type::DoubleTyID: opCode = FDTOX; break;
308 assert(0 && "Non-numeric non-bool type cannot be converted to Long");
313 assert(0 && "Should not get here, Mo!");
319 static inline MachineOpCode
320 ChooseAddInstructionByType(const Type* resultType)
322 MachineOpCode opCode = INVALID_OPCODE;
324 if (resultType->isIntegral() ||
325 resultType->isPointerType() ||
326 resultType->isLabelType() ||
327 isa<MethodType>(resultType) ||
328 resultType == Type::BoolTy)
333 switch(resultType->getPrimitiveID())
335 case Type::FloatTyID: opCode = FADDS; break;
336 case Type::DoubleTyID: opCode = FADDD; break;
337 default: assert(0 && "Invalid type for ADD instruction"); break;
344 static inline MachineOpCode
345 ChooseAddInstruction(const InstructionNode* instrNode)
347 return ChooseAddInstructionByType(instrNode->getInstruction()->getType());
351 static inline MachineInstr*
352 CreateMovFloatInstruction(const InstructionNode* instrNode,
353 const Type* resultType)
355 MachineInstr* minstr = new MachineInstr((resultType == Type::FloatTy)
357 minstr->SetMachineOperand(0, MachineOperand::MO_VirtualRegister,
358 instrNode->leftChild()->getValue());
359 minstr->SetMachineOperand(1, MachineOperand::MO_VirtualRegister,
360 instrNode->getValue());
364 static inline MachineInstr*
365 CreateAddConstInstruction(const InstructionNode* instrNode)
367 MachineInstr* minstr = NULL;
369 Value* constOp = ((InstrTreeNode*) instrNode->rightChild())->getValue();
370 assert(isa<ConstPoolVal>(constOp));
372 // Cases worth optimizing are:
373 // (1) Add with 0 for float or double: use an FMOV of appropriate type,
374 // instead of an FADD (1 vs 3 cycles). There is no integer MOV.
376 const Type* resultType = instrNode->getInstruction()->getType();
378 if (resultType == Type::FloatTy ||
379 resultType == Type::DoubleTy)
381 double dval = ((ConstPoolFP*) constOp)->getValue();
383 minstr = CreateMovFloatInstruction(instrNode, resultType);
390 static inline MachineOpCode
391 ChooseSubInstructionByType(const Type* resultType)
393 MachineOpCode opCode = INVALID_OPCODE;
395 if (resultType->isIntegral() ||
396 resultType->isPointerType())
401 switch(resultType->getPrimitiveID())
403 case Type::FloatTyID: opCode = FSUBS; break;
404 case Type::DoubleTyID: opCode = FSUBD; break;
405 default: assert(0 && "Invalid type for SUB instruction"); break;
412 static inline MachineInstr*
413 CreateSubConstInstruction(const InstructionNode* instrNode)
415 MachineInstr* minstr = NULL;
417 Value* constOp = ((InstrTreeNode*) instrNode->rightChild())->getValue();
418 assert(isa<ConstPoolVal>(constOp));
420 // Cases worth optimizing are:
421 // (1) Sub with 0 for float or double: use an FMOV of appropriate type,
422 // instead of an FSUB (1 vs 3 cycles). There is no integer MOV.
424 const Type* resultType = instrNode->getInstruction()->getType();
426 if (resultType == Type::FloatTy ||
427 resultType == Type::DoubleTy)
429 double dval = ((ConstPoolFP*) constOp)->getValue();
431 minstr = CreateMovFloatInstruction(instrNode, resultType);
438 static inline MachineOpCode
439 ChooseFcmpInstruction(const InstructionNode* instrNode)
441 MachineOpCode opCode = INVALID_OPCODE;
443 Value* operand = ((InstrTreeNode*) instrNode->leftChild())->getValue();
444 switch(operand->getType()->getPrimitiveID()) {
445 case Type::FloatTyID: opCode = FCMPS; break;
446 case Type::DoubleTyID: opCode = FCMPD; break;
447 default: assert(0 && "Invalid type for FCMP instruction"); break;
454 // Assumes that leftArg and rightArg are both cast instructions.
457 BothFloatToDouble(const InstructionNode* instrNode)
459 InstrTreeNode* leftArg = instrNode->leftChild();
460 InstrTreeNode* rightArg = instrNode->rightChild();
461 InstrTreeNode* leftArgArg = leftArg->leftChild();
462 InstrTreeNode* rightArgArg = rightArg->leftChild();
463 assert(leftArg->getValue()->getType() == rightArg->getValue()->getType());
465 // Check if both arguments are floats cast to double
466 return (leftArg->getValue()->getType() == Type::DoubleTy &&
467 leftArgArg->getValue()->getType() == Type::FloatTy &&
468 rightArgArg->getValue()->getType() == Type::FloatTy);
472 static inline MachineOpCode
473 ChooseMulInstructionByType(const Type* resultType)
475 MachineOpCode opCode = INVALID_OPCODE;
477 if (resultType->isIntegral())
480 switch(resultType->getPrimitiveID())
482 case Type::FloatTyID: opCode = FMULS; break;
483 case Type::DoubleTyID: opCode = FMULD; break;
484 default: assert(0 && "Invalid type for MUL instruction"); break;
491 static inline MachineOpCode
492 ChooseMulInstruction(const InstructionNode* instrNode,
495 if (checkCasts && BothFloatToDouble(instrNode))
498 // else use the regular multiply instructions
499 return ChooseMulInstructionByType(instrNode->getInstruction()->getType());
503 static inline MachineInstr*
504 CreateIntNegInstruction(TargetMachine& target,
507 MachineInstr* minstr = new MachineInstr(SUB);
508 minstr->SetMachineOperand(0, target.getRegInfo().getZeroRegNum());
509 minstr->SetMachineOperand(1, MachineOperand::MO_VirtualRegister, vreg);
510 minstr->SetMachineOperand(2, MachineOperand::MO_VirtualRegister, vreg);
515 static inline MachineInstr*
516 CreateMulConstInstruction(TargetMachine &target,
517 const InstructionNode* instrNode,
518 MachineInstr*& getMinstr2)
520 MachineInstr* minstr = NULL; // return NULL if we cannot exploit constant
521 getMinstr2 = NULL; // to create a cheaper instruction
522 bool needNeg = false;
524 Value* constOp = ((InstrTreeNode*) instrNode->rightChild())->getValue();
525 assert(isa<ConstPoolVal>(constOp));
527 // Cases worth optimizing are:
528 // (1) Multiply by 0 or 1 for any type: replace with copy (ADD or FMOV)
529 // (2) Multiply by 2^x for integer types: replace with Shift
531 const Type* resultType = instrNode->getInstruction()->getType();
533 if (resultType->isIntegral() || resultType->isPointerType())
537 int64_t C = GetConstantValueAsSignedInt(constOp, isValidConst);
540 bool needNeg = false;
547 if (C == 0 || C == 1)
549 minstr = new MachineInstr(ADD);
552 minstr->SetMachineOperand(0,
553 target.getRegInfo().getZeroRegNum());
555 minstr->SetMachineOperand(0,MachineOperand::MO_VirtualRegister,
556 instrNode->leftChild()->getValue());
557 minstr->SetMachineOperand(1,target.getRegInfo().getZeroRegNum());
559 else if (IsPowerOf2(C, pow))
561 minstr = new MachineInstr((resultType == Type::LongTy)
563 minstr->SetMachineOperand(0, MachineOperand::MO_VirtualRegister,
564 instrNode->leftChild()->getValue());
565 minstr->SetMachineOperand(1, MachineOperand::MO_UnextendedImmed,
569 if (minstr && needNeg)
570 { // insert <reg = SUB 0, reg> after the instr to flip the sign
571 getMinstr2 = CreateIntNegInstruction(target,
572 instrNode->getValue());
578 if (resultType == Type::FloatTy ||
579 resultType == Type::DoubleTy)
581 double dval = ((ConstPoolFP*) constOp)->getValue();
584 bool needNeg = (dval < 0);
586 MachineOpCode opCode = needNeg
587 ? (resultType == Type::FloatTy? FNEGS : FNEGD)
588 : (resultType == Type::FloatTy? FMOVS : FMOVD);
590 minstr = new MachineInstr(opCode);
591 minstr->SetMachineOperand(0,
592 MachineOperand::MO_VirtualRegister,
593 instrNode->leftChild()->getValue());
599 minstr->SetMachineOperand(2, MachineOperand::MO_VirtualRegister,
600 instrNode->getValue());
606 // Generate a divide instruction for Div or Rem.
607 // For Rem, this assumes that the operand type will be signed if the result
608 // type is signed. This is correct because they must have the same sign.
610 static inline MachineOpCode
611 ChooseDivInstruction(TargetMachine &target,
612 const InstructionNode* instrNode)
614 MachineOpCode opCode = INVALID_OPCODE;
616 const Type* resultType = instrNode->getInstruction()->getType();
618 if (resultType->isIntegral())
619 opCode = resultType->isSigned()? SDIVX : UDIVX;
621 switch(resultType->getPrimitiveID())
623 case Type::FloatTyID: opCode = FDIVS; break;
624 case Type::DoubleTyID: opCode = FDIVD; break;
625 default: assert(0 && "Invalid type for DIV instruction"); break;
632 static inline MachineInstr*
633 CreateDivConstInstruction(TargetMachine &target,
634 const InstructionNode* instrNode,
635 MachineInstr*& getMinstr2)
637 MachineInstr* minstr = NULL;
640 Value* constOp = ((InstrTreeNode*) instrNode->rightChild())->getValue();
641 assert(isa<ConstPoolVal>(constOp));
643 // Cases worth optimizing are:
644 // (1) Divide by 1 for any type: replace with copy (ADD or FMOV)
645 // (2) Divide by 2^x for integer types: replace with SR[L or A]{X}
647 const Type* resultType = instrNode->getInstruction()->getType();
649 if (resultType->isIntegral())
653 int64_t C = GetConstantValueAsSignedInt(constOp, isValidConst);
656 bool needNeg = false;
665 minstr = new MachineInstr(ADD);
666 minstr->SetMachineOperand(0,MachineOperand::MO_VirtualRegister,
667 instrNode->leftChild()->getValue());
668 minstr->SetMachineOperand(1,target.getRegInfo().getZeroRegNum());
670 else if (IsPowerOf2(C, pow))
672 MachineOpCode opCode= ((resultType->isSigned())
673 ? (resultType==Type::LongTy)? SRAX : SRA
674 : (resultType==Type::LongTy)? SRLX : SRL);
675 minstr = new MachineInstr(opCode);
676 minstr->SetMachineOperand(0, MachineOperand::MO_VirtualRegister,
677 instrNode->leftChild()->getValue());
678 minstr->SetMachineOperand(1, MachineOperand::MO_UnextendedImmed,
682 if (minstr && needNeg)
683 { // insert <reg = SUB 0, reg> after the instr to flip the sign
684 getMinstr2 = CreateIntNegInstruction(target,
685 instrNode->getValue());
691 if (resultType == Type::FloatTy ||
692 resultType == Type::DoubleTy)
694 double dval = ((ConstPoolFP*) constOp)->getValue();
697 bool needNeg = (dval < 0);
699 MachineOpCode opCode = needNeg
700 ? (resultType == Type::FloatTy? FNEGS : FNEGD)
701 : (resultType == Type::FloatTy? FMOVS : FMOVD);
703 minstr = new MachineInstr(opCode);
704 minstr->SetMachineOperand(0, MachineOperand::MO_VirtualRegister,
705 instrNode->leftChild()->getValue());
711 minstr->SetMachineOperand(2, MachineOperand::MO_VirtualRegister,
712 instrNode->getValue());
718 //------------------------------------------------------------------------
719 // Function SetOperandsForMemInstr
721 // Choose addressing mode for the given load or store instruction.
722 // Use [reg+reg] if it is an indexed reference, and the index offset is
723 // not a constant or if it cannot fit in the offset field.
724 // Use [reg+offset] in all other cases.
726 // This assumes that all array refs are "lowered" to one of these forms:
727 // %x = load (subarray*) ptr, constant ; single constant offset
728 // %x = load (subarray*) ptr, offsetVal ; single non-constant offset
729 // Generally, this should happen via strength reduction + LICM.
730 // Also, strength reduction should take care of using the same register for
731 // the loop index variable and an array index, when that is profitable.
732 //------------------------------------------------------------------------
735 SetOperandsForMemInstr(MachineInstr* minstr,
736 const InstructionNode* vmInstrNode,
737 const TargetMachine& target)
739 MemAccessInst* memInst = (MemAccessInst*) vmInstrNode->getInstruction();
741 // Variables to hold the index vector, ptr value, and offset value.
742 // The major work here is to extract these for all 3 instruction types
743 // and then call the common function SetMemOperands_Internal().
745 const vector<ConstPoolVal*> OLDIDXVEC = memInst->getIndicesBROKEN();
746 const vector<ConstPoolVal*>* idxVec = &OLDIDXVEC; //FIXME
747 vector<ConstPoolVal*>* newIdxVec = NULL;
749 Value* arrayOffsetVal = NULL;
751 // Test if a GetElemPtr instruction is being folded into this mem instrn.
752 // If so, it will be in the left child for Load and GetElemPtr,
753 // and in the right child for Store instructions.
755 InstrTreeNode* ptrChild = (vmInstrNode->getOpLabel() == Instruction::Store
756 ? vmInstrNode->rightChild()
757 : vmInstrNode->leftChild());
759 if (ptrChild->getOpLabel() == Instruction::GetElementPtr ||
760 ptrChild->getOpLabel() == GetElemPtrIdx)
762 // There is a GetElemPtr instruction and there may be a chain of
763 // more than one. Use the pointer value of the last one in the chain.
764 // Fold the index vectors from the entire chain and from the mem
765 // instruction into one single index vector.
766 // Finally, we never fold for an array instruction so make that NULL.
768 newIdxVec = new vector<ConstPoolVal*>;
769 ptrVal = FoldGetElemChain((InstructionNode*) ptrChild, *newIdxVec);
771 newIdxVec->insert(newIdxVec->end(), idxVec->begin(), idxVec->end());
774 assert(! ((PointerType*)ptrVal->getType())->getValueType()->isArrayType()
775 && "GetElemPtr cannot be folded into array refs in selection");
779 // There is no GetElemPtr instruction.
780 // Use the pointer value and the index vector from the Mem instruction.
781 // If it is an array reference, get the array offset value.
783 ptrVal = memInst->getPointerOperand();
785 const Type* opType = cast<PointerType>(ptrVal->getType())->getValueType();
786 if (opType->isArrayType())
788 assert((memInst->getNumOperands()
789 == (unsigned) 1 + memInst->getFirstIndexOperandNumber())
790 && "Array refs must be lowered before Instruction Selection");
792 arrayOffsetVal = memInst->getOperand(memInst->getFirstIndexOperandNumber());
796 SetMemOperands_Internal(minstr, vmInstrNode, ptrVal, arrayOffsetVal,
799 if (newIdxVec != NULL)
805 SetMemOperands_Internal(MachineInstr* minstr,
806 const InstructionNode* vmInstrNode,
808 Value* arrayOffsetVal,
809 const vector<ConstPoolVal*>& idxVec,
810 const TargetMachine& target)
812 MemAccessInst* memInst = (MemAccessInst*) vmInstrNode->getInstruction();
814 // Initialize so we default to storing the offset in a register.
815 int64_t smallConstOffset = 0;
816 Value* valueForRegOffset = NULL;
817 MachineOperand::MachineOperandType offsetOpType =MachineOperand::MO_VirtualRegister;
819 // Check if there is an index vector and if so, if it translates to
820 // a small enough constant to fit in the immediate-offset field.
822 if (idxVec.size() > 0)
824 bool isConstantOffset = false;
827 const PointerType* ptrType = (PointerType*) ptrVal->getType();
829 if (ptrType->getValueType()->isStructType())
831 // the offset is always constant for structs
832 isConstantOffset = true;
834 // Compute the offset value using the index vector
835 offset = target.DataLayout.getIndexedOffset(ptrType, idxVec);
839 // It must be an array ref. Check if the offset is a constant,
840 // and that the indexing has been lowered to a single offset.
842 assert(ptrType->getValueType()->isArrayType());
843 assert(arrayOffsetVal != NULL
844 && "Expect to be given Value* for array offsets");
846 if (ConstPoolVal *CPV = dyn_cast<ConstPoolVal>(arrayOffsetVal))
848 isConstantOffset = true; // always constant for structs
849 assert(arrayOffsetVal->getType()->isIntegral());
850 offset = (CPV->getType()->isSigned()
851 ? ((ConstPoolSInt*)CPV)->getValue()
852 : (int64_t) ((ConstPoolUInt*)CPV)->getValue());
856 valueForRegOffset = arrayOffsetVal;
860 if (isConstantOffset)
862 // create a virtual register for the constant
863 valueForRegOffset = ConstPoolSInt::get(Type::IntTy, offset);
868 offsetOpType = MachineOperand::MO_SignExtendedImmed;
869 smallConstOffset = 0;
872 // Operand 0 is value for STORE, ptr for LOAD or GET_ELEMENT_PTR
873 // It is the left child in the instruction tree in all cases.
874 Value* leftVal = vmInstrNode->leftChild()->getValue();
875 minstr->SetMachineOperand(0, MachineOperand::MO_VirtualRegister, leftVal);
877 // Operand 1 is ptr for STORE, offset for LOAD or GET_ELEMENT_PTR
878 // Operand 2 is offset for STORE, result reg for LOAD or GET_ELEMENT_PTR
880 unsigned offsetOpNum = (memInst->getOpcode() == Instruction::Store)? 2 : 1;
881 if (offsetOpType == MachineOperand::MO_VirtualRegister)
883 assert(valueForRegOffset != NULL);
884 minstr->SetMachineOperand(offsetOpNum, offsetOpType, valueForRegOffset);
887 minstr->SetMachineOperand(offsetOpNum, offsetOpType, smallConstOffset);
889 if (memInst->getOpcode() == Instruction::Store)
890 minstr->SetMachineOperand(1, MachineOperand::MO_VirtualRegister, ptrVal);
892 minstr->SetMachineOperand(2, MachineOperand::MO_VirtualRegister,
893 vmInstrNode->getValue());
898 // Substitute operand `operandNum' of the instruction in node `treeNode'
899 // in place of the use(s) of that instruction in node `parent'.
900 // Check both explicit and implicit operands!
903 ForwardOperand(InstructionNode* treeNode,
904 InstrTreeNode* parent,
907 assert(treeNode && parent && "Invalid invocation of ForwardOperand");
909 Instruction* unusedOp = treeNode->getInstruction();
910 Value* fwdOp = unusedOp->getOperand(operandNum);
912 // The parent itself may be a list node, so find the real parent instruction
913 while (parent->getNodeType() != InstrTreeNode::NTInstructionNode)
915 parent = parent->parent();
916 assert(parent && "ERROR: Non-instruction node has no parent in tree.");
918 InstructionNode* parentInstrNode = (InstructionNode*) parent;
920 Instruction* userInstr = parentInstrNode->getInstruction();
921 MachineCodeForVMInstr& mvec = userInstr->getMachineInstrVec();
922 for (unsigned i=0, N=mvec.size(); i < N; i++)
924 MachineInstr* minstr = mvec[i];
926 for (unsigned i=0, numOps=minstr->getNumOperands(); i < numOps; ++i)
928 const MachineOperand& mop = minstr->getOperand(i);
929 if (mop.getOperandType() == MachineOperand::MO_VirtualRegister &&
930 mop.getVRegValue() == unusedOp)
932 minstr->SetMachineOperand(i, MachineOperand::MO_VirtualRegister,
937 for (unsigned i=0, numOps=minstr->getNumImplicitRefs(); i < numOps; ++i)
938 if (minstr->getImplicitRef(i) == unusedOp)
939 minstr->setImplicitRef(i, fwdOp, minstr->implicitRefIsDefined(i));
945 void UltraSparcInstrInfo::
946 CreateCopyInstructionsByType(const TargetMachine& target,
949 vector<MachineInstr*>& minstrVec) const
951 bool loadConstantToReg = false;
953 const Type* resultType = dest->getType();
955 MachineOpCode opCode = ChooseAddInstructionByType(resultType);
956 if (opCode == INVALID_OPCODE)
958 assert(0 && "Unsupported result type in CreateCopyInstructionsByType()");
962 // if `src' is a constant that doesn't fit in the immed field or if it is
963 // a global variable (i.e., a constant address), generate a load
964 // instruction instead of an add
966 if (isa<ConstPoolVal>(src))
968 unsigned int machineRegNum;
970 MachineOperand::MachineOperandType opType =
971 ChooseRegOrImmed(src, opCode, target, /*canUseImmed*/ true,
972 machineRegNum, immedValue);
974 if (opType == MachineOperand::MO_VirtualRegister)
975 loadConstantToReg = true;
977 else if (isa<GlobalValue>(src))
978 loadConstantToReg = true;
980 if (loadConstantToReg)
981 { // `src' is constant and cannot fit in immed field for the ADD
982 // Insert instructions to "load" the constant into a register
983 vector<TmpInstruction*> tempVec;
984 target.getInstrInfo().CreateCodeToLoadConst(src,dest,minstrVec,tempVec);
985 for (unsigned i=0; i < tempVec.size(); i++)
986 dest->getMachineInstrVec().addTempValue(tempVec[i]);
989 { // Create the appropriate add instruction.
990 // Make `src' the second operand, in case it is a constant
991 // Use (unsigned long) 0 for a NULL pointer value.
993 const Type* nullValueType =
994 (resultType->getPrimitiveID() == Type::PointerTyID)? Type::ULongTy
996 MachineInstr* minstr = new MachineInstr(opCode);
997 minstr->SetMachineOperand(0, MachineOperand::MO_VirtualRegister,
998 ConstPoolVal::getNullConstant(nullValueType));
999 minstr->SetMachineOperand(1, MachineOperand::MO_VirtualRegister, src);
1000 minstr->SetMachineOperand(2, MachineOperand::MO_VirtualRegister, dest);
1001 minstrVec.push_back(minstr);
1007 //******************* Externally Visible Functions *************************/
1010 //------------------------------------------------------------------------
1011 // External Function: GetInstructionsForProlog
1012 // External Function: GetInstructionsForEpilog
1015 // Create prolog and epilog code for procedure entry and exit
1016 //------------------------------------------------------------------------
1019 GetInstructionsForProlog(BasicBlock* entryBB,
1020 TargetMachine &target,
1021 MachineInstr** mvec)
1023 int64_t s0=0; // used to avoid overloading ambiguity below
1025 const MachineFrameInfo& frameInfo = target.getFrameInfo();
1027 // The second operand is the stack size. If it does not fit in the
1028 // immediate field, we either have to find an unused register in the
1029 // caller's window or move some elements to the dynamically allocated
1030 // area of the stack frame (just above save area and method args).
1031 Method* method = entryBB->getParent();
1032 MachineCodeForMethod& mcInfo = MachineCodeForMethod::get(method);
1033 unsigned int staticStackSize = mcInfo.getStaticStackSize();
1035 if (staticStackSize < (unsigned) frameInfo.getMinStackFrameSize())
1036 staticStackSize = (unsigned) frameInfo.getMinStackFrameSize();
1038 if (unsigned padsz = (staticStackSize %
1039 (unsigned) frameInfo.getStackFrameSizeAlignment()))
1040 staticStackSize += frameInfo.getStackFrameSizeAlignment() - padsz;
1042 assert(target.getInstrInfo().constantFitsInImmedField(SAVE, staticStackSize)
1043 && "Stack size too large for immediate field of SAVE instruction. Need additional work as described in the comment above");
1045 mvec[0] = new MachineInstr(SAVE);
1046 mvec[0]->SetMachineOperand(0, target.getRegInfo().getStackPointer());
1047 mvec[0]->SetMachineOperand(1, MachineOperand::MO_SignExtendedImmed,
1048 - (int) staticStackSize);
1049 mvec[0]->SetMachineOperand(2, target.getRegInfo().getStackPointer());
1056 GetInstructionsForEpilog(BasicBlock* anExitBB,
1057 TargetMachine &target,
1058 MachineInstr** mvec)
1060 int64_t s0=0; // used to avoid overloading ambiguity below
1062 mvec[0] = new MachineInstr(RESTORE);
1063 mvec[0]->SetMachineOperand(0, target.getRegInfo().getZeroRegNum());
1064 mvec[0]->SetMachineOperand(1, MachineOperand::MO_SignExtendedImmed, s0);
1065 mvec[0]->SetMachineOperand(2, target.getRegInfo().getZeroRegNum());
1071 //------------------------------------------------------------------------
1072 // External Function: ThisIsAChainRule
1075 // Check if a given BURG rule is a chain rule.
1076 //------------------------------------------------------------------------
1079 ThisIsAChainRule(int eruleno)
1083 case 111: // stmt: reg
1084 case 113: // stmt: bool
1106 return false; break;
1111 //------------------------------------------------------------------------
1112 // External Function: GetInstructionsByRule
1115 // Choose machine instructions for the SPARC according to the
1116 // patterns chosen by the BURG-generated parser.
1117 //------------------------------------------------------------------------
1120 GetInstructionsByRule(InstructionNode* subtreeRoot,
1123 TargetMachine &target,
1124 MachineInstr** mvec)
1126 int numInstr = 1; // initialize for common case
1127 bool checkCast = false; // initialize here to use fall-through
1129 int forwardOperandNum = -1;
1130 int64_t s0=0, s8=8; // variables holding constants to avoid
1131 uint64_t u0=0; // overloading ambiguities below
1133 for (unsigned i=0; i < MAX_INSTR_PER_VMINSTR; i++)
1137 // Let's check for chain rules outside the switch so that we don't have
1138 // to duplicate the list of chain rule production numbers here again
1140 if (ThisIsAChainRule(ruleForNode))
1142 // Chain rules have a single nonterminal on the RHS.
1143 // Get the rule that matches the RHS non-terminal and use that instead.
1145 assert(nts[0] && ! nts[1]
1146 && "A chain rule should have only one RHS non-terminal!");
1147 nextRule = burm_rule(subtreeRoot->state, nts[0]);
1148 nts = burm_nts[nextRule];
1149 numInstr = GetInstructionsByRule(subtreeRoot, nextRule, nts,target,mvec);
1153 switch(ruleForNode) {
1154 case 1: // stmt: Ret
1155 case 2: // stmt: RetValue(reg)
1156 { // NOTE: Prepass of register allocation is responsible
1157 // for moving return value to appropriate register.
1158 // Mark the return-address register as a hidden virtual reg.
1159 // Mark the return value register as an implicit ref of
1160 // the machine instruction.
1161 // Finally put a NOP in the delay slot.
1162 ReturnInst* returnInstr = (ReturnInst*) subtreeRoot->getInstruction();
1163 assert(returnInstr->getOpcode() == Instruction::Ret);
1164 Method* method = returnInstr->getParent()->getParent();
1166 Instruction* returnReg = new TmpInstruction(TMP_INSTRUCTION_OPCODE,
1168 returnInstr->getMachineInstrVec().addTempValue(returnReg);
1170 mvec[0] = new MachineInstr(JMPLRET);
1171 mvec[0]->SetMachineOperand(0, MachineOperand::MO_VirtualRegister,
1173 mvec[0]->SetMachineOperand(1, MachineOperand::MO_SignExtendedImmed,s8);
1174 mvec[0]->SetMachineOperand(2, target.getRegInfo().getZeroRegNum());
1176 if (returnInstr->getReturnValue() != NULL)
1177 mvec[0]->addImplicitRef(returnInstr->getReturnValue());
1179 unsigned n = numInstr++; // delay slot
1180 mvec[n] = new MachineInstr(NOP);
1185 case 3: // stmt: Store(reg,reg)
1186 case 4: // stmt: Store(reg,ptrreg)
1187 mvec[0] = new MachineInstr(
1188 ChooseStoreInstruction(
1189 subtreeRoot->leftChild()->getValue()->getType()));
1190 SetOperandsForMemInstr(mvec[0], subtreeRoot, target);
1193 case 5: // stmt: BrUncond
1194 mvec[0] = new MachineInstr(BA);
1195 mvec[0]->SetMachineOperand(0, MachineOperand::MO_CCRegister,
1197 mvec[0]->SetMachineOperand(1, MachineOperand::MO_PCRelativeDisp,
1198 ((BranchInst*) subtreeRoot->getInstruction())->getSuccessor(0));
1201 mvec[numInstr++] = new MachineInstr(NOP);
1204 case 206: // stmt: BrCond(setCCconst)
1205 { // setCCconst => boolean was computed with `%b = setCC type reg1 const'
1206 // If the constant is ZERO, we can use the branch-on-integer-register
1207 // instructions and avoid the SUBcc instruction entirely.
1208 // Otherwise this is just the same as case 5, so just fall through.
1210 InstrTreeNode* constNode = subtreeRoot->leftChild()->rightChild();
1212 constNode->getNodeType() ==InstrTreeNode::NTConstNode);
1213 ConstPoolVal* constVal = (ConstPoolVal*) constNode->getValue();
1216 if ((constVal->getType()->isIntegral()
1217 || constVal->getType()->isPointerType())
1218 && GetConstantValueAsSignedInt(constVal, isValidConst) == 0
1221 BranchInst* brInst=cast<BranchInst>(subtreeRoot->getInstruction());
1223 // That constant is a zero after all...
1224 // Use the left child of setCC as the first argument!
1225 mvec[0] = new MachineInstr(ChooseBprInstruction(subtreeRoot));
1226 mvec[0]->SetMachineOperand(0, MachineOperand::MO_VirtualRegister,
1227 subtreeRoot->leftChild()->leftChild()->getValue());
1228 mvec[0]->SetMachineOperand(1, MachineOperand::MO_PCRelativeDisp,
1229 brInst->getSuccessor(0));
1232 mvec[numInstr++] = new MachineInstr(NOP);
1236 mvec[n] = new MachineInstr(BA);
1237 mvec[n]->SetMachineOperand(0, MachineOperand::MO_CCRegister,
1239 mvec[n]->SetMachineOperand(1, MachineOperand::MO_PCRelativeDisp,
1240 brInst->getSuccessor(1));
1243 mvec[numInstr++] = new MachineInstr(NOP);
1247 // ELSE FALL THROUGH
1250 case 6: // stmt: BrCond(bool)
1251 { // bool => boolean was computed with some boolean operator
1252 // (SetCC, Not, ...). We need to check whether the type was a FP,
1253 // signed int or unsigned int, and check the branching condition in
1254 // order to choose the branch to use.
1255 // If it is an integer CC, we also need to find the unique
1256 // TmpInstruction representing that CC.
1258 BranchInst* brInst = cast<BranchInst>(subtreeRoot->getInstruction());
1260 mvec[0] = new MachineInstr(ChooseBccInstruction(subtreeRoot,
1263 Value* ccValue = GetTmpForCC(subtreeRoot->leftChild()->getValue(),
1264 brInst->getParent()->getParent(),
1265 isFPBranch? Type::FloatTy : Type::IntTy);
1267 mvec[0]->SetMachineOperand(0, MachineOperand::MO_CCRegister, ccValue);
1268 mvec[0]->SetMachineOperand(1, MachineOperand::MO_PCRelativeDisp,
1269 brInst->getSuccessor(0));
1272 mvec[numInstr++] = new MachineInstr(NOP);
1276 mvec[n] = new MachineInstr(BA);
1277 mvec[n]->SetMachineOperand(0, MachineOperand::MO_CCRegister,
1279 mvec[n]->SetMachineOperand(1, MachineOperand::MO_PCRelativeDisp,
1280 brInst->getSuccessor(1));
1283 mvec[numInstr++] = new MachineInstr(NOP);
1287 case 208: // stmt: BrCond(boolconst)
1289 // boolconst => boolean is a constant; use BA to first or second label
1290 ConstPoolVal* constVal =
1291 cast<ConstPoolVal>(subtreeRoot->leftChild()->getValue());
1292 unsigned dest = ((ConstPoolBool*) constVal)->getValue()? 0 : 1;
1294 mvec[0] = new MachineInstr(BA);
1295 mvec[0]->SetMachineOperand(0, MachineOperand::MO_CCRegister,
1297 mvec[0]->SetMachineOperand(1, MachineOperand::MO_PCRelativeDisp,
1298 ((BranchInst*) subtreeRoot->getInstruction())->getSuccessor(dest));
1301 mvec[numInstr++] = new MachineInstr(NOP);
1305 case 8: // stmt: BrCond(boolreg)
1306 { // boolreg => boolean is stored in an existing register.
1307 // Just use the branch-on-integer-register instruction!
1309 mvec[0] = new MachineInstr(BRNZ);
1310 mvec[0]->SetMachineOperand(0, MachineOperand::MO_VirtualRegister,
1311 subtreeRoot->leftChild()->getValue());
1312 mvec[0]->SetMachineOperand(1, MachineOperand::MO_PCRelativeDisp,
1313 ((BranchInst*) subtreeRoot->getInstruction())->getSuccessor(0));
1316 mvec[numInstr++] = new MachineInstr(NOP); // delay slot
1320 mvec[n] = new MachineInstr(BA);
1321 mvec[n]->SetMachineOperand(0, MachineOperand::MO_CCRegister,
1323 mvec[n]->SetMachineOperand(1, MachineOperand::MO_PCRelativeDisp,
1324 ((BranchInst*) subtreeRoot->getInstruction())->getSuccessor(1));
1327 mvec[numInstr++] = new MachineInstr(NOP);
1331 case 9: // stmt: Switch(reg)
1332 assert(0 && "*** SWITCH instruction is not implemented yet.");
1336 case 10: // reg: VRegList(reg, reg)
1337 assert(0 && "VRegList should never be the topmost non-chain rule");
1340 case 21: // bool: Not(bool): Both these are implemented as:
1341 case 321: // reg: BNot(reg) : reg = reg XOR-NOT 0
1342 mvec[0] = new MachineInstr(XNOR);
1343 mvec[0]->SetMachineOperand(0, MachineOperand::MO_VirtualRegister,
1344 subtreeRoot->leftChild()->getValue());
1345 mvec[0]->SetMachineOperand(1, target.getRegInfo().getZeroRegNum());
1346 mvec[0]->SetMachineOperand(2, MachineOperand::MO_VirtualRegister,
1347 subtreeRoot->getValue());
1350 case 322: // reg: ToBoolTy(bool):
1351 case 22: // reg: ToBoolTy(reg):
1353 const Type* opType = subtreeRoot->leftChild()->getValue()->getType();
1354 assert(opType->isIntegral() || opType->isPointerType()
1355 || opType == Type::BoolTy);
1357 forwardOperandNum = 0;
1361 case 23: // reg: ToUByteTy(reg)
1362 case 25: // reg: ToUShortTy(reg)
1363 case 27: // reg: ToUIntTy(reg)
1364 case 29: // reg: ToULongTy(reg)
1366 const Type* opType = subtreeRoot->leftChild()->getValue()->getType();
1367 assert(opType->isIntegral() ||
1368 opType->isPointerType() ||
1369 opType == Type::BoolTy && "Cast is illegal for other types");
1371 forwardOperandNum = 0;
1375 case 24: // reg: ToSByteTy(reg)
1376 case 26: // reg: ToShortTy(reg)
1377 case 28: // reg: ToIntTy(reg)
1378 case 30: // reg: ToLongTy(reg)
1380 const Type* opType = subtreeRoot->leftChild()->getValue()->getType();
1381 if (opType->isIntegral()
1382 || opType->isPointerType()
1383 || opType == Type::BoolTy)
1386 forwardOperandNum = 0;
1390 // If the source operand is an FP type, the int result must be
1391 // copied from float to int register via memory!
1392 Instruction *dest = subtreeRoot->getInstruction();
1393 Value* leftVal = subtreeRoot->leftChild()->getValue();
1395 vector<MachineInstr*> minstrVec;
1397 if (opType == Type::FloatTy || opType == Type::DoubleTy)
1399 // Create a temporary to represent the INT register
1400 // into which the FP value will be copied via memory.
1401 // The type of this temporary will determine the FP
1402 // register used: single-prec for a 32-bit int or smaller,
1403 // double-prec for a 64-bit int.
1405 const Type* destTypeToUse =
1406 (dest->getType() == Type::LongTy)? Type::DoubleTy
1408 destForCast = new TmpInstruction(TMP_INSTRUCTION_OPCODE,
1409 destTypeToUse, leftVal, NULL);
1410 dest->getMachineInstrVec().addTempValue(destForCast);
1412 vector<TmpInstruction*> tempVec;
1413 target.getInstrInfo().CreateCodeToCopyFloatToInt(
1414 dest->getParent()->getParent(),
1415 (TmpInstruction*) destForCast, dest,
1416 minstrVec, tempVec, target);
1418 for (unsigned i=0; i < tempVec.size(); ++i)
1419 dest->getMachineInstrVec().addTempValue(tempVec[i]);
1422 destForCast = leftVal;
1424 MachineOpCode opCode=ChooseConvertToIntInstr(subtreeRoot, opType);
1425 assert(opCode != INVALID_OPCODE && "Expected to need conversion!");
1427 mvec[0] = new MachineInstr(opCode);
1428 mvec[0]->SetMachineOperand(0, MachineOperand::MO_VirtualRegister,
1430 mvec[0]->SetMachineOperand(1, MachineOperand::MO_VirtualRegister,
1433 assert(numInstr == 1 && "Should be initialized to 1 at the top");
1434 for (unsigned i=0; i < minstrVec.size(); ++i)
1435 mvec[numInstr++] = minstrVec[i];
1440 case 31: // reg: ToFloatTy(reg):
1441 case 32: // reg: ToDoubleTy(reg):
1442 case 232: // reg: ToDoubleTy(Constant):
1444 // If this instruction has a parent (a user) in the tree
1445 // and the user is translated as an FsMULd instruction,
1446 // then the cast is unnecessary. So check that first.
1447 // In the future, we'll want to do the same for the FdMULq instruction,
1448 // so do the check here instead of only for ToFloatTy(reg).
1450 if (subtreeRoot->parent() != NULL &&
1451 ((InstructionNode*) subtreeRoot->parent())->getInstruction()->getMachineInstrVec()[0]->getOpCode() == FSMULD)
1454 forwardOperandNum = 0;
1458 Value* leftVal = subtreeRoot->leftChild()->getValue();
1459 const Type* opType = leftVal->getType();
1460 MachineOpCode opCode=ChooseConvertToFloatInstr(subtreeRoot,opType);
1461 if (opCode == INVALID_OPCODE) // no conversion needed
1464 forwardOperandNum = 0;
1468 // If the source operand is a non-FP type it must be
1469 // first copied from int to float register via memory!
1470 Instruction *dest = subtreeRoot->getInstruction();
1473 if (opType != Type::FloatTy && opType != Type::DoubleTy)
1475 // Create a temporary to represent the FP register
1476 // into which the integer will be copied via memory.
1477 // The type of this temporary will determine the FP
1478 // register used: single-prec for a 32-bit int or smaller,
1479 // double-prec for a 64-bit int.
1481 const Type* srcTypeToUse =
1482 (leftVal->getType() == Type::LongTy)? Type::DoubleTy
1485 srcForCast = new TmpInstruction(TMP_INSTRUCTION_OPCODE,
1486 srcTypeToUse, dest, NULL);
1487 dest->getMachineInstrVec().addTempValue(srcForCast);
1489 vector<MachineInstr*> minstrVec;
1490 vector<TmpInstruction*> tempVec;
1491 target.getInstrInfo().CreateCodeToCopyIntToFloat(
1492 dest->getParent()->getParent(),
1493 leftVal, (TmpInstruction*) srcForCast,
1494 minstrVec, tempVec, target);
1496 for (unsigned i=0; i < minstrVec.size(); ++i)
1497 mvec[n++] = minstrVec[i];
1499 for (unsigned i=0; i < tempVec.size(); ++i)
1500 dest->getMachineInstrVec().addTempValue(tempVec[i]);
1503 srcForCast = leftVal;
1505 MachineInstr* castI = new MachineInstr(opCode);
1506 castI->SetMachineOperand(0, MachineOperand::MO_VirtualRegister,
1508 castI->SetMachineOperand(1, MachineOperand::MO_VirtualRegister,
1516 case 19: // reg: ToArrayTy(reg):
1517 case 20: // reg: ToPointerTy(reg):
1519 forwardOperandNum = 0;
1522 case 233: // reg: Add(reg, Constant)
1523 mvec[0] = CreateAddConstInstruction(subtreeRoot);
1524 if (mvec[0] != NULL)
1526 // ELSE FALL THROUGH
1528 case 33: // reg: Add(reg, reg)
1529 mvec[0] = new MachineInstr(ChooseAddInstruction(subtreeRoot));
1530 Set3OperandsFromInstr(mvec[0], subtreeRoot, target);
1533 case 234: // reg: Sub(reg, Constant)
1534 mvec[0] = CreateSubConstInstruction(subtreeRoot);
1535 if (mvec[0] != NULL)
1537 // ELSE FALL THROUGH
1539 case 34: // reg: Sub(reg, reg)
1540 mvec[0] = new MachineInstr(ChooseSubInstructionByType(
1541 subtreeRoot->getInstruction()->getType()));
1542 Set3OperandsFromInstr(mvec[0], subtreeRoot, target);
1545 case 135: // reg: Mul(todouble, todouble)
1549 case 35: // reg: Mul(reg, reg)
1550 mvec[0] =new MachineInstr(ChooseMulInstruction(subtreeRoot,checkCast));
1551 Set3OperandsFromInstr(mvec[0], subtreeRoot, target);
1554 case 335: // reg: Mul(todouble, todoubleConst)
1558 case 235: // reg: Mul(reg, Constant)
1559 mvec[0] = CreateMulConstInstruction(target, subtreeRoot, mvec[1]);
1560 if (mvec[0] == NULL)
1562 mvec[0] = new MachineInstr(ChooseMulInstruction(subtreeRoot,
1564 Set3OperandsFromInstr(mvec[0], subtreeRoot, target);
1567 if (mvec[1] != NULL)
1571 case 236: // reg: Div(reg, Constant)
1572 mvec[0] = CreateDivConstInstruction(target, subtreeRoot, mvec[1]);
1573 if (mvec[0] != NULL)
1575 if (mvec[1] != NULL)
1579 // ELSE FALL THROUGH
1581 case 36: // reg: Div(reg, reg)
1582 mvec[0] = new MachineInstr(ChooseDivInstruction(target, subtreeRoot));
1583 Set3OperandsFromInstr(mvec[0], subtreeRoot, target);
1586 case 37: // reg: Rem(reg, reg)
1587 case 237: // reg: Rem(reg, Constant)
1589 Instruction* remInstr = subtreeRoot->getInstruction();
1591 TmpInstruction* quot = new TmpInstruction(TMP_INSTRUCTION_OPCODE,
1592 subtreeRoot->leftChild()->getValue(),
1593 subtreeRoot->rightChild()->getValue());
1594 TmpInstruction* prod = new TmpInstruction(TMP_INSTRUCTION_OPCODE,
1596 subtreeRoot->rightChild()->getValue());
1597 remInstr->getMachineInstrVec().addTempValue(quot);
1598 remInstr->getMachineInstrVec().addTempValue(prod);
1600 mvec[0] = new MachineInstr(ChooseDivInstruction(target, subtreeRoot));
1601 Set3OperandsFromInstr(mvec[0], subtreeRoot, target);
1602 mvec[0]->SetMachineOperand(2, MachineOperand::MO_VirtualRegister,quot);
1605 mvec[n] = new MachineInstr(ChooseMulInstructionByType(
1606 subtreeRoot->getInstruction()->getType()));
1607 mvec[n]->SetMachineOperand(0, MachineOperand::MO_VirtualRegister,quot);
1608 mvec[n]->SetMachineOperand(1, MachineOperand::MO_VirtualRegister,
1609 subtreeRoot->rightChild()->getValue());
1610 mvec[n]->SetMachineOperand(2, MachineOperand::MO_VirtualRegister,prod);
1613 mvec[n] = new MachineInstr(ChooseSubInstructionByType(
1614 subtreeRoot->getInstruction()->getType()));
1615 Set3OperandsFromInstr(mvec[n], subtreeRoot, target);
1616 mvec[n]->SetMachineOperand(1, MachineOperand::MO_VirtualRegister,prod);
1621 case 38: // bool: And(bool, bool)
1622 case 238: // bool: And(bool, boolconst)
1623 case 338: // reg : BAnd(reg, reg)
1624 case 538: // reg : BAnd(reg, Constant)
1625 mvec[0] = new MachineInstr(AND);
1626 Set3OperandsFromInstr(mvec[0], subtreeRoot, target);
1629 case 138: // bool: And(bool, not)
1630 case 438: // bool: BAnd(bool, not)
1631 mvec[0] = new MachineInstr(ANDN);
1632 Set3OperandsFromInstr(mvec[0], subtreeRoot, target);
1635 case 39: // bool: Or(bool, bool)
1636 case 239: // bool: Or(bool, boolconst)
1637 case 339: // reg : BOr(reg, reg)
1638 case 539: // reg : BOr(reg, Constant)
1639 mvec[0] = new MachineInstr(ORN);
1640 Set3OperandsFromInstr(mvec[0], subtreeRoot, target);
1643 case 139: // bool: Or(bool, not)
1644 case 439: // bool: BOr(bool, not)
1645 mvec[0] = new MachineInstr(ORN);
1646 Set3OperandsFromInstr(mvec[0], subtreeRoot, target);
1649 case 40: // bool: Xor(bool, bool)
1650 case 240: // bool: Xor(bool, boolconst)
1651 case 340: // reg : BXor(reg, reg)
1652 case 540: // reg : BXor(reg, Constant)
1653 mvec[0] = new MachineInstr(XOR);
1654 Set3OperandsFromInstr(mvec[0], subtreeRoot, target);
1657 case 140: // bool: Xor(bool, not)
1658 case 440: // bool: BXor(bool, not)
1659 mvec[0] = new MachineInstr(XNOR);
1660 Set3OperandsFromInstr(mvec[0], subtreeRoot, target);
1663 case 41: // boolconst: SetCC(reg, Constant)
1664 // Check if this is an integer comparison, and
1665 // there is a parent, and the parent decided to use
1666 // a branch-on-integer-register instead of branch-on-condition-code.
1667 // If so, the SUBcc instruction is not required.
1668 // (However, we must still check for constants to be loaded from
1669 // the constant pool so that such a load can be associated with
1670 // this instruction.)
1672 // Otherwise this is just the same as case 42, so just fall through.
1674 if ((subtreeRoot->leftChild()->getValue()->getType()->isIntegral() ||
1675 subtreeRoot->leftChild()->getValue()->getType()->isPointerType())
1676 && subtreeRoot->parent() != NULL)
1678 InstructionNode* parent = (InstructionNode*) subtreeRoot->parent();
1679 assert(parent->getNodeType() == InstrTreeNode::NTInstructionNode);
1680 const vector<MachineInstr*>&
1681 minstrVec = parent->getInstruction()->getMachineInstrVec();
1682 MachineOpCode parentOpCode;
1683 if (parent->getInstruction()->getOpcode() == Instruction::Br &&
1684 (parentOpCode = minstrVec[0]->getOpCode()) >= BRZ &&
1685 parentOpCode <= BRGEZ)
1687 numInstr = 0; // don't forward the operand!
1691 // ELSE FALL THROUGH
1693 case 42: // bool: SetCC(reg, reg):
1695 // This generates a SUBCC instruction, putting the difference in
1696 // a result register, and setting a condition code.
1698 // If the boolean result of the SetCC is used by anything other
1699 // than a single branch instruction, the boolean must be
1700 // computed and stored in the result register. Otherwise, discard
1701 // the difference (by using %g0) and keep only the condition code.
1703 // To compute the boolean result in a register we use a conditional
1704 // move, unless the result of the SUBCC instruction can be used as
1705 // the bool! This assumes that zero is FALSE and any non-zero
1708 InstructionNode* parentNode = (InstructionNode*) subtreeRoot->parent();
1709 Instruction* setCCInstr = subtreeRoot->getInstruction();
1710 bool keepBoolVal = (parentNode == NULL ||
1711 parentNode->getInstruction()->getOpcode()
1712 != Instruction::Br);
1713 bool subValIsBoolVal = setCCInstr->getOpcode() == Instruction::SetNE;
1714 bool keepSubVal = keepBoolVal && subValIsBoolVal;
1715 bool computeBoolVal = keepBoolVal && ! subValIsBoolVal;
1719 MachineOpCode movOpCode = 0;
1721 // Mark the 4th operand as being a CC register, and as a def
1722 // A TmpInstruction is created to represent the CC "result".
1723 // Unlike other instances of TmpInstruction, this one is used
1724 // by machine code of multiple LLVM instructions, viz.,
1725 // the SetCC and the branch. Make sure to get the same one!
1726 // Note that we do this even for FP CC registers even though they
1727 // are explicit operands, because the type of the operand
1728 // needs to be a floating point condition code, not an integer
1729 // condition code. Think of this as casting the bool result to
1730 // a FP condition code register.
1732 Value* leftVal = subtreeRoot->leftChild()->getValue();
1733 bool isFPCompare = (leftVal->getType() == Type::FloatTy ||
1734 leftVal->getType() == Type::DoubleTy);
1736 TmpInstruction* tmpForCC = GetTmpForCC(setCCInstr,
1737 setCCInstr->getParent()->getParent(),
1738 isFPCompare? Type::FloatTy : Type::IntTy);
1739 setCCInstr->getMachineInstrVec().addTempValue(tmpForCC);
1743 // Integer condition: dest. should be %g0 or an integer register.
1744 // If result must be saved but condition is not SetEQ then we need
1745 // a separate instruction to compute the bool result, so discard
1746 // result of SUBcc instruction anyway.
1748 mvec[0] = new MachineInstr(SUBcc);
1749 Set3OperandsFromInstr(mvec[0], subtreeRoot, target, ! keepSubVal);
1751 mvec[0]->SetMachineOperand(3, MachineOperand::MO_CCRegister,
1752 tmpForCC, /*def*/true);
1755 { // recompute bool using the integer condition codes
1757 ChooseMovpccAfterSub(subtreeRoot,mustClearReg,valueToMove);
1762 // FP condition: dest of FCMP should be some FCCn register
1763 mvec[0] = new MachineInstr(ChooseFcmpInstruction(subtreeRoot));
1764 mvec[0]->SetMachineOperand(0, MachineOperand::MO_CCRegister,
1766 mvec[0]->SetMachineOperand(1,MachineOperand::MO_VirtualRegister,
1767 subtreeRoot->leftChild()->getValue());
1768 mvec[0]->SetMachineOperand(2,MachineOperand::MO_VirtualRegister,
1769 subtreeRoot->rightChild()->getValue());
1772 {// recompute bool using the FP condition codes
1773 mustClearReg = true;
1775 movOpCode = ChooseMovFpccInstruction(subtreeRoot);
1782 {// Unconditionally set register to 0
1784 mvec[n] = new MachineInstr(SETHI);
1785 mvec[n]->SetMachineOperand(0,MachineOperand::MO_UnextendedImmed,
1787 mvec[n]->SetMachineOperand(1,MachineOperand::MO_VirtualRegister,
1791 // Now conditionally move `valueToMove' (0 or 1) into the register
1793 mvec[n] = new MachineInstr(movOpCode);
1794 mvec[n]->SetMachineOperand(0, MachineOperand::MO_CCRegister,
1796 mvec[n]->SetMachineOperand(1, MachineOperand::MO_UnextendedImmed,
1798 mvec[n]->SetMachineOperand(2, MachineOperand::MO_VirtualRegister,
1804 case 43: // boolreg: VReg
1805 case 44: // boolreg: Constant
1809 case 51: // reg: Load(reg)
1810 case 52: // reg: Load(ptrreg)
1811 case 53: // reg: LoadIdx(reg,reg)
1812 case 54: // reg: LoadIdx(ptrreg,reg)
1813 mvec[0] = new MachineInstr(ChooseLoadInstruction(
1814 subtreeRoot->getValue()->getType()));
1815 SetOperandsForMemInstr(mvec[0], subtreeRoot, target);
1818 case 55: // reg: GetElemPtr(reg)
1819 case 56: // reg: GetElemPtrIdx(reg,reg)
1820 if (subtreeRoot->parent() != NULL)
1822 // If the parent was a memory operation and not an array access,
1823 // the parent will fold this instruction in so generate nothing.
1825 Instruction* parent =
1826 cast<Instruction>(subtreeRoot->parent()->getValue());
1827 if (parent->getOpcode() == Instruction::Load ||
1828 parent->getOpcode() == Instruction::Store ||
1829 parent->getOpcode() == Instruction::GetElementPtr)
1831 // Check if the parent is an array access,
1832 // If so, we still need to generate this instruction.
1833 GetElementPtrInst* getElemInst =
1834 cast<GetElementPtrInst>(subtreeRoot->getInstruction());
1835 const PointerType* ptrType =
1836 cast<PointerType>(getElemInst->getPointerOperand()->getType());
1837 if (! ptrType->getValueType()->isArrayType())
1838 {// we don't need a separate instr
1839 numInstr = 0; // don't forward operand!
1844 // else in all other cases we need to a separate ADD instruction
1845 mvec[0] = new MachineInstr(ADD);
1846 SetOperandsForMemInstr(mvec[0], subtreeRoot, target);
1849 case 57: // reg: Alloca: Implement as 1 instruction:
1850 { // add %fp, offsetFromFP -> result
1851 Instruction* instr = subtreeRoot->getInstruction();
1852 const PointerType* instrType = (const PointerType*) instr->getType();
1853 assert(instrType->isPointerType());
1855 target.findOptimalStorageSize(instrType->getValueType());
1856 assert(tsize != 0 && "Just to check when this can happen");
1858 Method* method = instr->getParent()->getParent();
1859 MachineCodeForMethod& mcInfo = MachineCodeForMethod::get(method);
1860 int offsetFromFP = mcInfo.allocateLocalVar(target, instr, (unsigned int) tsize);
1862 // Create a temporary Value to hold the constant offset.
1863 // This is needed because it may not fit in the immediate field.
1864 ConstPoolSInt* offsetVal=ConstPoolSInt::get(Type::IntTy, offsetFromFP);
1866 // Instruction 1: add %fp, offsetFromFP -> result
1867 mvec[0] = new MachineInstr(ADD);
1868 mvec[0]->SetMachineOperand(0, target.getRegInfo().getFramePointer());
1869 mvec[0]->SetMachineOperand(1, MachineOperand::MO_VirtualRegister,
1871 mvec[0]->SetMachineOperand(2, MachineOperand::MO_VirtualRegister,
1876 case 58: // reg: Alloca(reg): Implement as 3 instructions:
1877 // mul num, typeSz -> tmp
1878 // sub %sp, tmp -> %sp
1879 { // add %sp, frameSizeBelowDynamicArea -> result
1880 Instruction* instr = subtreeRoot->getInstruction();
1881 const PointerType* instrType = (const PointerType*) instr->getType();
1882 assert(instrType->isPointerType() &&
1883 instrType->getValueType()->isArrayType());
1884 const Type* eltType =
1885 ((ArrayType*) instrType->getValueType())->getElementType();
1886 int tsize = (int) target.findOptimalStorageSize(eltType);
1888 assert(tsize != 0 && "Just to check when this can happen");
1890 // Create a temporary Value to hold the constant type-size
1891 ConstPoolSInt* tsizeVal = ConstPoolSInt::get(Type::IntTy, tsize);
1893 // Create a temporary Value to hold the constant offset from SP
1894 Method* method = instr->getParent()->getParent();
1895 bool ignore; // we don't need this
1896 ConstPoolSInt* dynamicAreaOffset = ConstPoolSInt::get(Type::IntTy,
1897 target.getFrameInfo().getDynamicAreaOffset(MachineCodeForMethod::get(method),
1900 // Create a temporary value to hold `tmp'
1901 Instruction* tmpInstr = new TmpInstruction(TMP_INSTRUCTION_OPCODE,
1902 subtreeRoot->leftChild()->getValue(),
1903 NULL /*could insert tsize here*/);
1904 subtreeRoot->getInstruction()->getMachineInstrVec().addTempValue(tmpInstr);
1906 // Instruction 1: mul numElements, typeSize -> tmp
1907 mvec[0] = new MachineInstr(MULX);
1908 mvec[0]->SetMachineOperand(0, MachineOperand::MO_VirtualRegister,
1909 subtreeRoot->leftChild()->getValue());
1910 mvec[0]->SetMachineOperand(1, MachineOperand::MO_VirtualRegister,
1912 mvec[0]->SetMachineOperand(2, MachineOperand::MO_VirtualRegister,
1915 // Instruction 2: sub %sp, tmp -> %sp
1917 mvec[1] = new MachineInstr(SUB);
1918 mvec[1]->SetMachineOperand(0, target.getRegInfo().getStackPointer());
1919 mvec[1]->SetMachineOperand(1, MachineOperand::MO_VirtualRegister,
1921 mvec[1]->SetMachineOperand(2, target.getRegInfo().getStackPointer());
1923 // Instruction 3: add %sp, frameSizeBelowDynamicArea -> result
1925 mvec[2] = new MachineInstr(ADD);
1926 mvec[2]->SetMachineOperand(0, target.getRegInfo().getStackPointer());
1927 mvec[2]->SetMachineOperand(1, MachineOperand::MO_VirtualRegister,
1929 mvec[2]->SetMachineOperand(2,MachineOperand::MO_VirtualRegister,instr);
1933 case 61: // reg: Call
1934 { // Generate a call-indirect (i.e., jmpl) for now to expose
1935 // the potential need for registers. If an absolute address
1936 // is available, replace this with a CALL instruction.
1937 // Mark both the indirection register and the return-address
1938 // register as hidden virtual registers.
1939 // Also, mark the operands of the Call and return value (if
1940 // any) as implicit operands of the CALL machine instruction.
1942 CallInst *callInstr = cast<CallInst>(subtreeRoot->getInstruction());
1943 Value *callee = callInstr->getCalledValue();
1945 Instruction* retAddrReg = new TmpInstruction(TMP_INSTRUCTION_OPCODE,
1948 // Note temporary values in the machineInstrVec for the VM instr.
1950 // WARNING: Operands 0..N-1 must go in slots 0..N-1 of implicitUses.
1951 // The result value must go in slot N. This is assumed
1952 // in register allocation.
1954 callInstr->getMachineInstrVec().addTempValue(retAddrReg);
1957 // Generate the machine instruction and its operands.
1958 // Use CALL for direct function calls; this optimistically assumes
1959 // the PC-relative address fits in the CALL address field (22 bits).
1960 // Use JMPL for indirect calls.
1962 if (callee->getValueType() == Value::MethodVal)
1963 { // direct function call
1964 mvec[0] = new MachineInstr(CALL);
1965 mvec[0]->SetMachineOperand(0, MachineOperand::MO_PCRelativeDisp,
1969 { // indirect function call
1970 mvec[0] = new MachineInstr(JMPLCALL);
1971 mvec[0]->SetMachineOperand(0, MachineOperand::MO_VirtualRegister,
1973 mvec[0]->SetMachineOperand(1, MachineOperand::MO_SignExtendedImmed,
1975 mvec[0]->SetMachineOperand(2, MachineOperand::MO_VirtualRegister,
1979 // Add the call operands and return value as implicit refs
1980 for (unsigned i=0, N=callInstr->getNumOperands(); i < N; ++i)
1981 if (callInstr->getOperand(i) != callee)
1982 mvec[0]->addImplicitRef(callInstr->getOperand(i));
1984 if (callInstr->getType() != Type::VoidTy)
1985 mvec[0]->addImplicitRef(callInstr, /*isDef*/ true);
1987 // For the CALL instruction, the ret. addr. reg. is also implicit
1988 if (callee->getValueType() == Value::MethodVal)
1989 mvec[0]->addImplicitRef(retAddrReg, /*isDef*/ true);
1991 mvec[numInstr++] = new MachineInstr(NOP); // delay slot
1995 case 62: // reg: Shl(reg, reg)
1996 { const Type* opType = subtreeRoot->leftChild()->getValue()->getType();
1997 assert(opType->isIntegral()
1998 || opType == Type::BoolTy
1999 || opType->isPointerType()&& "Shl unsupported for other types");
2000 mvec[0] = new MachineInstr((opType == Type::LongTy)? SLLX : SLL);
2001 Set3OperandsFromInstr(mvec[0], subtreeRoot, target);
2005 case 63: // reg: Shr(reg, reg)
2006 { const Type* opType = subtreeRoot->leftChild()->getValue()->getType();
2007 assert(opType->isIntegral()
2008 || opType == Type::BoolTy
2009 || opType->isPointerType() &&"Shr unsupported for other types");
2010 mvec[0] = new MachineInstr((opType->isSigned()
2011 ? ((opType == Type::LongTy)? SRAX : SRA)
2012 : ((opType == Type::LongTy)? SRLX : SRL)));
2013 Set3OperandsFromInstr(mvec[0], subtreeRoot, target);
2017 case 64: // reg: Phi(reg,reg)
2018 numInstr = 0; // don't forward the value
2020 #undef NEED_PHI_MACHINE_INSTRS
2021 #ifdef NEED_PHI_MACHINE_INSTRS
2022 { // This instruction has variable #operands, so resultPos is 0.
2023 Instruction* phi = subtreeRoot->getInstruction();
2024 mvec[0] = new MachineInstr(PHI, 1 + phi->getNumOperands());
2025 mvec[0]->SetMachineOperand(0, MachineOperand::MO_VirtualRegister,
2026 subtreeRoot->getValue());
2027 for (unsigned i=0, N=phi->getNumOperands(); i < N; i++)
2028 mvec[0]->SetMachineOperand(i+1, MachineOperand::MO_VirtualRegister,
2029 phi->getOperand(i));
2032 #endif NEED_PHI_MACHINE_INSTRS
2034 case 71: // reg: VReg
2035 case 72: // reg: Constant
2036 numInstr = 0; // don't forward the value
2040 assert(0 && "Unrecognized BURG rule");
2046 if (forwardOperandNum >= 0)
2047 { // We did not generate a machine instruction but need to use operand.
2048 // If user is in the same tree, replace Value in its machine operand.
2049 // If not, insert a copy instruction which should get coalesced away
2050 // by register allocation.
2051 if (subtreeRoot->parent() != NULL)
2052 ForwardOperand(subtreeRoot, subtreeRoot->parent(), forwardOperandNum);
2055 vector<MachineInstr*> minstrVec;
2056 target.getInstrInfo().CreateCopyInstructionsByType(target,
2057 subtreeRoot->getInstruction()->getOperand(forwardOperandNum),
2058 subtreeRoot->getInstruction(), minstrVec);
2059 assert(minstrVec.size() > 0);
2060 for (unsigned i=0; i < minstrVec.size(); ++i)
2061 mvec[numInstr++] = minstrVec[i];