2 //***************************************************************************
4 // SparcInstrSelection.cpp
7 // BURS instruction selection for SPARC V9 architecture.
10 // 7/02/01 - Vikram Adve - Created
11 //**************************************************************************/
13 #include "SparcInternals.h"
14 #include "SparcInstrSelectionSupport.h"
15 #include "SparcRegClassInfo.h"
16 #include "llvm/CodeGen/InstrSelectionSupport.h"
17 #include "llvm/CodeGen/MachineInstr.h"
18 #include "llvm/CodeGen/InstrForest.h"
19 #include "llvm/CodeGen/InstrSelection.h"
20 #include "llvm/CodeGen/MachineCodeForMethod.h"
21 #include "llvm/CodeGen/MachineCodeForInstruction.h"
22 #include "llvm/DerivedTypes.h"
23 #include "llvm/iTerminators.h"
24 #include "llvm/iMemory.h"
25 #include "llvm/iOther.h"
26 #include "llvm/BasicBlock.h"
27 #include "llvm/Function.h"
28 #include "llvm/ConstantVals.h"
29 #include "Support/MathExtras.h"
33 //************************* Forward Declarations ***************************/
36 static void SetMemOperands_Internal (vector<MachineInstr*>& mvec,
37 vector<MachineInstr*>::iterator mvecI,
38 const InstructionNode* vmInstrNode,
40 std::vector<Value*>& idxVec,
41 const TargetMachine& target);
44 //************************ Internal Functions ******************************/
47 static inline MachineOpCode
48 ChooseBprInstruction(const InstructionNode* instrNode)
52 Instruction* setCCInstr =
53 ((InstructionNode*) instrNode->leftChild())->getInstruction();
55 switch(setCCInstr->getOpcode())
57 case Instruction::SetEQ: opCode = BRZ; break;
58 case Instruction::SetNE: opCode = BRNZ; break;
59 case Instruction::SetLE: opCode = BRLEZ; break;
60 case Instruction::SetGE: opCode = BRGEZ; break;
61 case Instruction::SetLT: opCode = BRLZ; break;
62 case Instruction::SetGT: opCode = BRGZ; break;
64 assert(0 && "Unrecognized VM instruction!");
65 opCode = INVALID_OPCODE;
73 static inline MachineOpCode
74 ChooseBpccInstruction(const InstructionNode* instrNode,
75 const BinaryOperator* setCCInstr)
77 MachineOpCode opCode = INVALID_OPCODE;
79 bool isSigned = setCCInstr->getOperand(0)->getType()->isSigned();
83 switch(setCCInstr->getOpcode())
85 case Instruction::SetEQ: opCode = BE; break;
86 case Instruction::SetNE: opCode = BNE; break;
87 case Instruction::SetLE: opCode = BLE; break;
88 case Instruction::SetGE: opCode = BGE; break;
89 case Instruction::SetLT: opCode = BL; break;
90 case Instruction::SetGT: opCode = BG; break;
92 assert(0 && "Unrecognized VM instruction!");
98 switch(setCCInstr->getOpcode())
100 case Instruction::SetEQ: opCode = BE; break;
101 case Instruction::SetNE: opCode = BNE; break;
102 case Instruction::SetLE: opCode = BLEU; break;
103 case Instruction::SetGE: opCode = BCC; break;
104 case Instruction::SetLT: opCode = BCS; break;
105 case Instruction::SetGT: opCode = BGU; break;
107 assert(0 && "Unrecognized VM instruction!");
115 static inline MachineOpCode
116 ChooseBFpccInstruction(const InstructionNode* instrNode,
117 const BinaryOperator* setCCInstr)
119 MachineOpCode opCode = INVALID_OPCODE;
121 switch(setCCInstr->getOpcode())
123 case Instruction::SetEQ: opCode = FBE; break;
124 case Instruction::SetNE: opCode = FBNE; break;
125 case Instruction::SetLE: opCode = FBLE; break;
126 case Instruction::SetGE: opCode = FBGE; break;
127 case Instruction::SetLT: opCode = FBL; break;
128 case Instruction::SetGT: opCode = FBG; break;
130 assert(0 && "Unrecognized VM instruction!");
138 // Create a unique TmpInstruction for a boolean value,
139 // representing the CC register used by a branch on that value.
140 // For now, hack this using a little static cache of TmpInstructions.
141 // Eventually the entire BURG instruction selection should be put
142 // into a separate class that can hold such information.
143 // The static cache is not too bad because the memory for these
144 // TmpInstructions will be freed along with the rest of the Function anyway.
146 static TmpInstruction*
147 GetTmpForCC(Value* boolVal, const Function *F, const Type* ccType)
149 typedef std::hash_map<const Value*, TmpInstruction*> BoolTmpCache;
150 static BoolTmpCache boolToTmpCache; // Map boolVal -> TmpInstruction*
151 static const Function *lastFunction = 0;// Use to flush cache between funcs
153 assert(boolVal->getType() == Type::BoolTy && "Weird but ok! Delete assert");
155 if (lastFunction != F)
158 boolToTmpCache.clear();
161 // Look for tmpI and create a new one otherwise. The new value is
162 // directly written to map using the ref returned by operator[].
163 TmpInstruction*& tmpI = boolToTmpCache[boolVal];
165 tmpI = new TmpInstruction(ccType, boolVal);
171 static inline MachineOpCode
172 ChooseBccInstruction(const InstructionNode* instrNode,
175 InstructionNode* setCCNode = (InstructionNode*) instrNode->leftChild();
176 BinaryOperator* setCCInstr = (BinaryOperator*) setCCNode->getInstruction();
177 const Type* setCCType = setCCInstr->getOperand(0)->getType();
179 isFPBranch = (setCCType == Type::FloatTy || setCCType == Type::DoubleTy);
182 return ChooseBFpccInstruction(instrNode, setCCInstr);
184 return ChooseBpccInstruction(instrNode, setCCInstr);
188 static inline MachineOpCode
189 ChooseMovFpccInstruction(const InstructionNode* instrNode)
191 MachineOpCode opCode = INVALID_OPCODE;
193 switch(instrNode->getInstruction()->getOpcode())
195 case Instruction::SetEQ: opCode = MOVFE; break;
196 case Instruction::SetNE: opCode = MOVFNE; break;
197 case Instruction::SetLE: opCode = MOVFLE; break;
198 case Instruction::SetGE: opCode = MOVFGE; break;
199 case Instruction::SetLT: opCode = MOVFL; break;
200 case Instruction::SetGT: opCode = MOVFG; break;
202 assert(0 && "Unrecognized VM instruction!");
210 // Assumes that SUBcc v1, v2 -> v3 has been executed.
211 // In most cases, we want to clear v3 and then follow it by instruction
213 // Set mustClearReg=false if v3 need not be cleared before conditional move.
214 // Set valueToMove=0 if we want to conditionally move 0 instead of 1
215 // (i.e., we want to test inverse of a condition)
216 // (The latter two cases do not seem to arise because SetNE needs nothing.)
219 ChooseMovpccAfterSub(const InstructionNode* instrNode,
223 MachineOpCode opCode = INVALID_OPCODE;
227 switch(instrNode->getInstruction()->getOpcode())
229 case Instruction::SetEQ: opCode = MOVE; break;
230 case Instruction::SetLE: opCode = MOVLE; break;
231 case Instruction::SetGE: opCode = MOVGE; break;
232 case Instruction::SetLT: opCode = MOVL; break;
233 case Instruction::SetGT: opCode = MOVG; break;
234 case Instruction::SetNE: assert(0 && "No move required!"); break;
235 default: assert(0 && "Unrecognized VM instr!"); break;
241 static inline MachineOpCode
242 ChooseConvertToFloatInstr(OpLabel vopCode, const Type* opType)
244 MachineOpCode opCode = INVALID_OPCODE;
249 if (opType == Type::SByteTy || opType == Type::ShortTy || opType == Type::IntTy)
251 else if (opType == Type::LongTy)
253 else if (opType == Type::DoubleTy)
255 else if (opType == Type::FloatTy)
258 assert(0 && "Cannot convert this type to FLOAT on SPARC");
262 // This is usually used in conjunction with CreateCodeToCopyIntToFloat().
263 // Both functions should treat the integer as a 32-bit value for types
264 // of 4 bytes or less, and as a 64-bit value otherwise.
265 if (opType == Type::SByteTy || opType == Type::UByteTy ||
266 opType == Type::ShortTy || opType == Type::UShortTy ||
267 opType == Type::IntTy || opType == Type::UIntTy)
269 else if (opType == Type::LongTy || opType == Type::ULongTy)
271 else if (opType == Type::FloatTy)
273 else if (opType == Type::DoubleTy)
276 assert(0 && "Cannot convert this type to DOUBLE on SPARC");
286 static inline MachineOpCode
287 ChooseConvertToIntInstr(OpLabel vopCode, const Type* opType)
289 MachineOpCode opCode = INVALID_OPCODE;;
291 if (vopCode == ToSByteTy || vopCode == ToShortTy || vopCode == ToIntTy)
293 switch (opType->getPrimitiveID())
295 case Type::FloatTyID: opCode = FSTOI; break;
296 case Type::DoubleTyID: opCode = FDTOI; break;
298 assert(0 && "Non-numeric non-bool type cannot be converted to Int");
302 else if (vopCode == ToLongTy)
304 switch (opType->getPrimitiveID())
306 case Type::FloatTyID: opCode = FSTOX; break;
307 case Type::DoubleTyID: opCode = FDTOX; break;
309 assert(0 && "Non-numeric non-bool type cannot be converted to Long");
314 assert(0 && "Should not get here, Mo!");
320 CreateConvertToIntInstr(OpLabel vopCode, Value* srcVal, Value* destVal)
322 MachineOpCode opCode = ChooseConvertToIntInstr(vopCode, srcVal->getType());
323 assert(opCode != INVALID_OPCODE && "Expected to need conversion!");
325 MachineInstr* M = new MachineInstr(opCode);
326 M->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister, srcVal);
327 M->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister, destVal);
331 static inline MachineOpCode
332 ChooseAddInstructionByType(const Type* resultType)
334 MachineOpCode opCode = INVALID_OPCODE;
336 if (resultType->isIntegral() ||
337 isa<PointerType>(resultType) ||
338 isa<FunctionType>(resultType) ||
339 resultType == Type::LabelTy ||
340 resultType == Type::BoolTy)
345 switch(resultType->getPrimitiveID())
347 case Type::FloatTyID: opCode = FADDS; break;
348 case Type::DoubleTyID: opCode = FADDD; break;
349 default: assert(0 && "Invalid type for ADD instruction"); break;
356 static inline MachineOpCode
357 ChooseAddInstruction(const InstructionNode* instrNode)
359 return ChooseAddInstructionByType(instrNode->getInstruction()->getType());
363 static inline MachineInstr*
364 CreateMovFloatInstruction(const InstructionNode* instrNode,
365 const Type* resultType)
367 MachineInstr* minstr = new MachineInstr((resultType == Type::FloatTy)
369 minstr->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister,
370 instrNode->leftChild()->getValue());
371 minstr->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister,
372 instrNode->getValue());
376 static inline MachineInstr*
377 CreateAddConstInstruction(const InstructionNode* instrNode)
379 MachineInstr* minstr = NULL;
381 Value* constOp = ((InstrTreeNode*) instrNode->rightChild())->getValue();
382 assert(isa<Constant>(constOp));
384 // Cases worth optimizing are:
385 // (1) Add with 0 for float or double: use an FMOV of appropriate type,
386 // instead of an FADD (1 vs 3 cycles). There is no integer MOV.
388 const Type* resultType = instrNode->getInstruction()->getType();
390 if (resultType == Type::FloatTy ||
391 resultType == Type::DoubleTy)
393 double dval = cast<ConstantFP>(constOp)->getValue();
395 minstr = CreateMovFloatInstruction(instrNode, resultType);
402 static inline MachineOpCode
403 ChooseSubInstructionByType(const Type* resultType)
405 MachineOpCode opCode = INVALID_OPCODE;
407 if (resultType->isIntegral() ||
408 resultType->isPointerType())
413 switch(resultType->getPrimitiveID())
415 case Type::FloatTyID: opCode = FSUBS; break;
416 case Type::DoubleTyID: opCode = FSUBD; break;
417 default: assert(0 && "Invalid type for SUB instruction"); break;
424 static inline MachineInstr*
425 CreateSubConstInstruction(const InstructionNode* instrNode)
427 MachineInstr* minstr = NULL;
429 Value* constOp = ((InstrTreeNode*) instrNode->rightChild())->getValue();
430 assert(isa<Constant>(constOp));
432 // Cases worth optimizing are:
433 // (1) Sub with 0 for float or double: use an FMOV of appropriate type,
434 // instead of an FSUB (1 vs 3 cycles). There is no integer MOV.
436 const Type* resultType = instrNode->getInstruction()->getType();
438 if (resultType == Type::FloatTy ||
439 resultType == Type::DoubleTy)
441 double dval = cast<ConstantFP>(constOp)->getValue();
443 minstr = CreateMovFloatInstruction(instrNode, resultType);
450 static inline MachineOpCode
451 ChooseFcmpInstruction(const InstructionNode* instrNode)
453 MachineOpCode opCode = INVALID_OPCODE;
455 Value* operand = ((InstrTreeNode*) instrNode->leftChild())->getValue();
456 switch(operand->getType()->getPrimitiveID()) {
457 case Type::FloatTyID: opCode = FCMPS; break;
458 case Type::DoubleTyID: opCode = FCMPD; break;
459 default: assert(0 && "Invalid type for FCMP instruction"); break;
466 // Assumes that leftArg and rightArg are both cast instructions.
469 BothFloatToDouble(const InstructionNode* instrNode)
471 InstrTreeNode* leftArg = instrNode->leftChild();
472 InstrTreeNode* rightArg = instrNode->rightChild();
473 InstrTreeNode* leftArgArg = leftArg->leftChild();
474 InstrTreeNode* rightArgArg = rightArg->leftChild();
475 assert(leftArg->getValue()->getType() == rightArg->getValue()->getType());
477 // Check if both arguments are floats cast to double
478 return (leftArg->getValue()->getType() == Type::DoubleTy &&
479 leftArgArg->getValue()->getType() == Type::FloatTy &&
480 rightArgArg->getValue()->getType() == Type::FloatTy);
484 static inline MachineOpCode
485 ChooseMulInstructionByType(const Type* resultType)
487 MachineOpCode opCode = INVALID_OPCODE;
489 if (resultType->isIntegral())
492 switch(resultType->getPrimitiveID())
494 case Type::FloatTyID: opCode = FMULS; break;
495 case Type::DoubleTyID: opCode = FMULD; break;
496 default: assert(0 && "Invalid type for MUL instruction"); break;
504 static inline MachineInstr*
505 CreateIntNegInstruction(const TargetMachine& target,
508 MachineInstr* minstr = new MachineInstr(SUB);
509 minstr->SetMachineOperandReg(0, target.getRegInfo().getZeroRegNum());
510 minstr->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister, vreg);
511 minstr->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister, vreg);
516 // Does not create any instructions if we cannot exploit constant to
517 // create a cheaper instruction.
518 // This returns the approximate cost of the instructions generated,
519 // which is used to pick the cheapest when both operands are constant.
520 static inline unsigned int
521 CreateMulConstInstruction(const TargetMachine &target,
522 Value* lval, Value* rval, Value* destVal,
523 vector<MachineInstr*>& mvec)
525 /* An integer multiply is generally more costly than FP multiply */
526 unsigned int cost = target.getInstrInfo().minLatency(MULX);
527 MachineInstr* minstr1 = NULL;
528 MachineInstr* minstr2 = NULL;
530 Value* constOp = rval;
531 if (! isa<Constant>(constOp))
534 // Cases worth optimizing are:
535 // (1) Multiply by 0 or 1 for any type: replace with copy (ADD or FMOV)
536 // (2) Multiply by 2^x for integer types: replace with Shift
538 const Type* resultType = destVal->getType();
540 if (resultType->isIntegral() || resultType->isPointerType())
544 int64_t C = GetConstantValueAsSignedInt(constOp, isValidConst);
547 bool needNeg = false;
554 if (C == 0 || C == 1)
556 cost = target.getInstrInfo().minLatency(ADD);
557 minstr1 = new MachineInstr(ADD);
559 minstr1->SetMachineOperandReg(0,
560 target.getRegInfo().getZeroRegNum());
562 minstr1->SetMachineOperandVal(0,
563 MachineOperand::MO_VirtualRegister, lval);
564 minstr1->SetMachineOperandReg(1,
565 target.getRegInfo().getZeroRegNum());
567 else if (IsPowerOf2(C, pow))
569 minstr1 = new MachineInstr((resultType == Type::LongTy)
571 minstr1->SetMachineOperandVal(0,
572 MachineOperand::MO_VirtualRegister, lval);
573 minstr1->SetMachineOperandConst(1,
574 MachineOperand::MO_UnextendedImmed, pow);
577 if (minstr1 && needNeg)
578 { // insert <reg = SUB 0, reg> after the instr to flip the sign
579 minstr2 = CreateIntNegInstruction(target, destVal);
580 cost += target.getInstrInfo().minLatency(minstr2->getOpCode());
586 if (resultType == Type::FloatTy ||
587 resultType == Type::DoubleTy)
589 double dval = cast<ConstantFP>(constOp)->getValue();
592 bool needNeg = (dval < 0);
594 MachineOpCode opCode = needNeg
595 ? (resultType == Type::FloatTy? FNEGS : FNEGD)
596 : (resultType == Type::FloatTy? FMOVS : FMOVD);
598 minstr1 = new MachineInstr(opCode);
599 minstr1->SetMachineOperandVal(0,
600 MachineOperand::MO_VirtualRegister,
607 minstr1->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister,
612 mvec.push_back(minstr1);
613 cost = target.getInstrInfo().minLatency(minstr1->getOpCode());
617 assert(minstr1 && "Otherwise cost needs to be initialized to 0");
618 cost += target.getInstrInfo().minLatency(minstr2->getOpCode());
619 mvec.push_back(minstr2);
626 // Does not create any instructions if we cannot exploit constant to
627 // create a cheaper instruction.
630 CreateCheapestMulConstInstruction(const TargetMachine &target,
631 Value* lval, Value* rval, Value* destVal,
632 vector<MachineInstr*>& mvec)
635 if (isa<Constant>(lval) && isa<Constant>(rval))
636 { // both operands are constant: try both orders!
637 vector<MachineInstr*> mvec1, mvec2;
638 unsigned int lcost = CreateMulConstInstruction(target, lval, rval,
640 unsigned int rcost = CreateMulConstInstruction(target, rval, lval,
642 vector<MachineInstr*>& mincostMvec = (lcost <= rcost)? mvec1 : mvec2;
643 vector<MachineInstr*>& maxcostMvec = (lcost <= rcost)? mvec2 : mvec1;
644 mvec.insert(mvec.end(), mincostMvec.begin(), mincostMvec.end());
646 for (unsigned int i=0; i < maxcostMvec.size(); ++i)
647 delete maxcostMvec[i];
649 else if (isa<Constant>(rval)) // rval is constant, but not lval
650 CreateMulConstInstruction(target, lval, rval, destVal, mvec);
651 else if (isa<Constant>(lval)) // lval is constant, but not rval
652 CreateMulConstInstruction(target, lval, rval, destVal, mvec);
654 // else neither is constant
658 // Return NULL if we cannot exploit constant to create a cheaper instruction
660 CreateMulInstruction(const TargetMachine &target,
661 Value* lval, Value* rval, Value* destVal,
662 vector<MachineInstr*>& mvec,
663 MachineOpCode forceMulOp = INVALID_MACHINE_OPCODE)
665 unsigned int L = mvec.size();
666 CreateCheapestMulConstInstruction(target, lval, rval, destVal, mvec);
667 if (mvec.size() == L)
668 { // no instructions were added so create MUL reg, reg, reg.
669 // Use FSMULD if both operands are actually floats cast to doubles.
670 // Otherwise, use the default opcode for the appropriate type.
671 MachineOpCode mulOp = ((forceMulOp != INVALID_MACHINE_OPCODE)
673 : ChooseMulInstructionByType(destVal->getType()));
674 MachineInstr* M = new MachineInstr(mulOp);
675 M->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister, lval);
676 M->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister, rval);
677 M->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister, destVal);
683 // Generate a divide instruction for Div or Rem.
684 // For Rem, this assumes that the operand type will be signed if the result
685 // type is signed. This is correct because they must have the same sign.
687 static inline MachineOpCode
688 ChooseDivInstruction(TargetMachine &target,
689 const InstructionNode* instrNode)
691 MachineOpCode opCode = INVALID_OPCODE;
693 const Type* resultType = instrNode->getInstruction()->getType();
695 if (resultType->isIntegral())
696 opCode = resultType->isSigned()? SDIVX : UDIVX;
698 switch(resultType->getPrimitiveID())
700 case Type::FloatTyID: opCode = FDIVS; break;
701 case Type::DoubleTyID: opCode = FDIVD; break;
702 default: assert(0 && "Invalid type for DIV instruction"); break;
709 // Return NULL if we cannot exploit constant to create a cheaper instruction
711 CreateDivConstInstruction(TargetMachine &target,
712 const InstructionNode* instrNode,
713 vector<MachineInstr*>& mvec)
715 MachineInstr* minstr1 = NULL;
716 MachineInstr* minstr2 = NULL;
718 Value* constOp = ((InstrTreeNode*) instrNode->rightChild())->getValue();
719 if (! isa<Constant>(constOp))
722 // Cases worth optimizing are:
723 // (1) Divide by 1 for any type: replace with copy (ADD or FMOV)
724 // (2) Divide by 2^x for integer types: replace with SR[L or A]{X}
726 const Type* resultType = instrNode->getInstruction()->getType();
728 if (resultType->isIntegral())
732 int64_t C = GetConstantValueAsSignedInt(constOp, isValidConst);
735 bool needNeg = false;
744 minstr1 = new MachineInstr(ADD);
745 minstr1->SetMachineOperandVal(0,
746 MachineOperand::MO_VirtualRegister,
747 instrNode->leftChild()->getValue());
748 minstr1->SetMachineOperandReg(1,
749 target.getRegInfo().getZeroRegNum());
751 else if (IsPowerOf2(C, pow))
753 MachineOpCode opCode= ((resultType->isSigned())
754 ? (resultType==Type::LongTy)? SRAX : SRA
755 : (resultType==Type::LongTy)? SRLX : SRL);
756 minstr1 = new MachineInstr(opCode);
757 minstr1->SetMachineOperandVal(0,
758 MachineOperand::MO_VirtualRegister,
759 instrNode->leftChild()->getValue());
760 minstr1->SetMachineOperandConst(1,
761 MachineOperand::MO_UnextendedImmed,
765 if (minstr1 && needNeg)
766 { // insert <reg = SUB 0, reg> after the instr to flip the sign
767 minstr2 = CreateIntNegInstruction(target,
768 instrNode->getValue());
774 if (resultType == Type::FloatTy ||
775 resultType == Type::DoubleTy)
777 double dval = cast<ConstantFP>(constOp)->getValue();
780 bool needNeg = (dval < 0);
782 MachineOpCode opCode = needNeg
783 ? (resultType == Type::FloatTy? FNEGS : FNEGD)
784 : (resultType == Type::FloatTy? FMOVS : FMOVD);
786 minstr1 = new MachineInstr(opCode);
787 minstr1->SetMachineOperandVal(0,
788 MachineOperand::MO_VirtualRegister,
789 instrNode->leftChild()->getValue());
795 minstr1->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister,
796 instrNode->getValue());
799 mvec.push_back(minstr1);
801 mvec.push_back(minstr2);
806 CreateCodeForVariableSizeAlloca(const TargetMachine& target,
809 Value* numElementsVal,
810 vector<MachineInstr*>& getMvec)
814 // Create a Value to hold the (constant) element size
815 Value* tsizeVal = ConstantSInt::get(Type::IntTy, tsize);
817 // Get the constant offset from SP for dynamically allocated storage
818 // and create a temporary Value to hold it.
819 assert(result && result->getParent() && "Result value is not part of a fn?");
820 Function *F = result->getParent()->getParent();
821 MachineCodeForMethod& mcInfo = MachineCodeForMethod::get(F);
823 ConstantSInt* dynamicAreaOffset =
824 ConstantSInt::get(Type::IntTy,
825 target.getFrameInfo().getDynamicAreaOffset(mcInfo,growUp));
826 assert(! growUp && "Has SPARC v9 stack frame convention changed?");
828 // Create a temporary value to hold the result of MUL
829 TmpInstruction* tmpProd = new TmpInstruction(numElementsVal, tsizeVal);
830 MachineCodeForInstruction::get(result).addTemp(tmpProd);
832 // Instruction 1: mul numElements, typeSize -> tmpProd
833 M = new MachineInstr(MULX);
834 M->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister, numElementsVal);
835 M->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister, tsizeVal);
836 M->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister, tmpProd);
837 getMvec.push_back(M);
839 // Instruction 2: sub %sp, tmpProd -> %sp
840 M = new MachineInstr(SUB);
841 M->SetMachineOperandReg(0, target.getRegInfo().getStackPointer());
842 M->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister, tmpProd);
843 M->SetMachineOperandReg(2, target.getRegInfo().getStackPointer());
844 getMvec.push_back(M);
846 // Instruction 3: add %sp, frameSizeBelowDynamicArea -> result
847 M = new MachineInstr(ADD);
848 M->SetMachineOperandReg(0, target.getRegInfo().getStackPointer());
849 M->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister, dynamicAreaOffset);
850 M->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister, result);
851 getMvec.push_back(M);
856 CreateCodeForFixedSizeAlloca(const TargetMachine& target,
859 unsigned int numElements,
860 vector<MachineInstr*>& getMvec)
862 assert(result && result->getParent() &&
863 "Result value is not part of a function?");
864 Function *F = result->getParent()->getParent();
865 MachineCodeForMethod &mcInfo = MachineCodeForMethod::get(F);
867 // Check if the offset would small enough to use as an immediate in
868 // load/stores (check LDX because all load/stores have the same-size immediate
869 // field). If not, put the variable in the dynamically sized area of the
871 unsigned int paddedSizeIgnored;
872 int offsetFromFP = mcInfo.computeOffsetforLocalVar(target, result,
874 tsize * numElements);
875 if (! target.getInstrInfo().constantFitsInImmedField(LDX, offsetFromFP))
877 CreateCodeForVariableSizeAlloca(target, result, tsize,
878 ConstantSInt::get(Type::IntTy,numElements),
883 // else offset fits in immediate field so go ahead and allocate it.
884 offsetFromFP = mcInfo.allocateLocalVar(target, result, tsize * numElements);
886 // Create a temporary Value to hold the constant offset.
887 // This is needed because it may not fit in the immediate field.
888 ConstantSInt* offsetVal = ConstantSInt::get(Type::IntTy, offsetFromFP);
890 // Instruction 1: add %fp, offsetFromFP -> result
891 MachineInstr* M = new MachineInstr(ADD);
892 M->SetMachineOperandReg(0, target.getRegInfo().getFramePointer());
893 M->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister, offsetVal);
894 M->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister, result);
896 getMvec.push_back(M);
901 //------------------------------------------------------------------------
902 // Function SetOperandsForMemInstr
904 // Choose addressing mode for the given load or store instruction.
905 // Use [reg+reg] if it is an indexed reference, and the index offset is
906 // not a constant or if it cannot fit in the offset field.
907 // Use [reg+offset] in all other cases.
909 // This assumes that all array refs are "lowered" to one of these forms:
910 // %x = load (subarray*) ptr, constant ; single constant offset
911 // %x = load (subarray*) ptr, offsetVal ; single non-constant offset
912 // Generally, this should happen via strength reduction + LICM.
913 // Also, strength reduction should take care of using the same register for
914 // the loop index variable and an array index, when that is profitable.
915 //------------------------------------------------------------------------
918 SetOperandsForMemInstr(vector<MachineInstr*>& mvec,
919 vector<MachineInstr*>::iterator mvecI,
920 const InstructionNode* vmInstrNode,
921 const TargetMachine& target)
923 MemAccessInst* memInst = (MemAccessInst*) vmInstrNode->getInstruction();
925 // Variables to hold the index vector, ptr value, and offset value.
926 // The major work here is to extract these for all 3 instruction types
927 // and then call the common function SetMemOperands_Internal().
929 Value* ptrVal = memInst->getPointerOperand();
931 // Start with the index vector of this instruction, if any.
932 vector<Value*> idxVec;
933 idxVec.insert(idxVec.end(), memInst->idx_begin(), memInst->idx_end());
935 // If there is a GetElemPtr instruction to fold in to this instr,
936 // it must be in the left child for Load and GetElemPtr, and in the
937 // right child for Store instructions.
938 InstrTreeNode* ptrChild = (vmInstrNode->getOpLabel() == Instruction::Store
939 ? vmInstrNode->rightChild()
940 : vmInstrNode->leftChild());
942 // Fold chains of GetElemPtr instructions for structure references.
943 if (isa<StructType>(cast<PointerType>(ptrVal->getType())->getElementType())
944 && (ptrChild->getOpLabel() == Instruction::GetElementPtr ||
945 ptrChild->getOpLabel() == GetElemPtrIdx))
947 Value* newPtr = FoldGetElemChain((InstructionNode*) ptrChild, idxVec);
952 SetMemOperands_Internal(mvec, mvecI, vmInstrNode, ptrVal, idxVec, target);
956 // Generate the correct operands (and additional instructions if needed)
957 // for the given pointer and given index vector.
960 SetMemOperands_Internal(vector<MachineInstr*>& mvec,
961 vector<MachineInstr*>::iterator mvecI,
962 const InstructionNode* vmInstrNode,
964 vector<Value*>& idxVec,
965 const TargetMachine& target)
967 MemAccessInst* memInst = (MemAccessInst*) vmInstrNode->getInstruction();
969 // Initialize so we default to storing the offset in a register.
970 int64_t smallConstOffset = 0;
971 Value* valueForRegOffset = NULL;
972 MachineOperand::MachineOperandType offsetOpType =MachineOperand::MO_VirtualRegister;
974 // Check if there is an index vector and if so, compute the
975 // right offset for structures and for arrays
977 if (idxVec.size() > 0)
981 const PointerType* ptrType = cast<PointerType>(ptrVal->getType());
983 // Handle special common case of leading [0] index.
984 bool firstIndexIsZero =
985 bool(isa<ConstantUInt>(idxVec.front()) &&
986 cast<ConstantUInt>(idxVec.front())->getValue() == 0);
988 // This is a real structure reference if the ptr target is a
989 // structure type, and the first offset is [0] (eliminate that offset).
990 if (firstIndexIsZero && ptrType->getElementType()->isStructType())
992 // Compute the offset value using the index vector. Create a
993 // virtual reg. for it since it may not fit in the immed field.
994 assert(idxVec.size() >= 2);
995 idxVec.erase(idxVec.begin());
996 unsigned offset = target.DataLayout.getIndexedOffset(ptrType,idxVec);
997 valueForRegOffset = ConstantSInt::get(Type::IntTy, offset);
1001 // It is an array ref, and must have been lowered to a single offset.
1002 assert((memInst->getNumOperands()
1003 == (unsigned) 1 + memInst->getFirstIndexOperandNumber())
1004 && "Array refs must be lowered before Instruction Selection");
1006 Value* arrayOffsetVal = * memInst->idx_begin();
1008 // If index is 0, the offset value is just 0. Otherwise,
1009 // generate a MUL instruction to compute address from index.
1010 // The call to getTypeSize() will fail if size is not constant.
1011 // CreateMulInstruction() folds constants intelligently enough.
1013 if (firstIndexIsZero)
1015 offsetOpType = MachineOperand::MO_SignExtendedImmed;
1016 smallConstOffset = 0;
1020 vector<MachineInstr*> mulVec;
1021 Instruction* addr = new TmpInstruction(Type::UIntTy, memInst);
1022 MachineCodeForInstruction::get(memInst).addTemp(addr);
1024 unsigned int eltSize =
1025 target.DataLayout.getTypeSize(ptrType->getElementType());
1026 assert(eltSize > 0 && "Invalid or non-const array element size");
1027 ConstantUInt* eltVal = ConstantUInt::get(Type::UIntTy, eltSize);
1029 CreateMulInstruction(target,
1030 arrayOffsetVal, /* lval, not likely const */
1031 eltVal, /* rval, likely constant */
1033 mulVec, INVALID_MACHINE_OPCODE);
1034 assert(mulVec.size() > 0 && "No multiply instruction created?");
1035 for (vector<MachineInstr*>::const_iterator I = mulVec.begin();
1036 I != mulVec.end(); ++I)
1038 mvecI = mvec.insert(mvecI, *I); // ptr to inserted value
1039 ++mvecI; // ptr to mem. instr.
1042 valueForRegOffset = addr;
1048 offsetOpType = MachineOperand::MO_SignExtendedImmed;
1049 smallConstOffset = 0;
1053 // Operand 0 is value, operand 1 is ptr, operand 2 is offset
1054 // For LOAD or GET_ELEMENT_PTR,
1055 // Operand 0 is ptr, operand 1 is offset, operand 2 is result.
1057 unsigned offsetOpNum, ptrOpNum;
1058 if (memInst->getOpcode() == Instruction::Store)
1060 (*mvecI)->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister,
1061 vmInstrNode->leftChild()->getValue());
1069 (*mvecI)->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister,
1073 (*mvecI)->SetMachineOperandVal(ptrOpNum, MachineOperand::MO_VirtualRegister,
1076 if (offsetOpType == MachineOperand::MO_VirtualRegister)
1078 assert(valueForRegOffset != NULL);
1079 (*mvecI)->SetMachineOperandVal(offsetOpNum, offsetOpType,
1083 (*mvecI)->SetMachineOperandConst(offsetOpNum, offsetOpType,
1089 // Substitute operand `operandNum' of the instruction in node `treeNode'
1090 // in place of the use(s) of that instruction in node `parent'.
1091 // Check both explicit and implicit operands!
1092 // Also make sure to skip over a parent who:
1093 // (1) is a list node in the Burg tree, or
1094 // (2) itself had its results forwarded to its parent
1097 ForwardOperand(InstructionNode* treeNode,
1098 InstrTreeNode* parent,
1101 assert(treeNode && parent && "Invalid invocation of ForwardOperand");
1103 Instruction* unusedOp = treeNode->getInstruction();
1104 Value* fwdOp = unusedOp->getOperand(operandNum);
1106 // The parent itself may be a list node, so find the real parent instruction
1107 while (parent->getNodeType() != InstrTreeNode::NTInstructionNode)
1109 parent = parent->parent();
1110 assert(parent && "ERROR: Non-instruction node has no parent in tree.");
1112 InstructionNode* parentInstrNode = (InstructionNode*) parent;
1114 Instruction* userInstr = parentInstrNode->getInstruction();
1115 MachineCodeForInstruction &mvec = MachineCodeForInstruction::get(userInstr);
1117 // The parent's mvec would be empty if it was itself forwarded.
1118 // Recursively call ForwardOperand in that case...
1120 if (mvec.size() == 0)
1122 assert(parent->parent() != NULL &&
1123 "Parent could not have been forwarded, yet has no instructions?");
1124 ForwardOperand(treeNode, parent->parent(), operandNum);
1128 bool fwdSuccessful = false;
1129 for (unsigned i=0, N=mvec.size(); i < N; i++)
1131 MachineInstr* minstr = mvec[i];
1132 for (unsigned i=0, numOps=minstr->getNumOperands(); i < numOps; ++i)
1134 const MachineOperand& mop = minstr->getOperand(i);
1135 if (mop.getOperandType() == MachineOperand::MO_VirtualRegister &&
1136 mop.getVRegValue() == unusedOp)
1138 minstr->SetMachineOperandVal(i,
1139 MachineOperand::MO_VirtualRegister, fwdOp);
1140 fwdSuccessful = true;
1144 for (unsigned i=0,numOps=minstr->getNumImplicitRefs(); i<numOps; ++i)
1145 if (minstr->getImplicitRef(i) == unusedOp)
1147 minstr->setImplicitRef(i, fwdOp,
1148 minstr->implicitRefIsDefined(i));
1149 fwdSuccessful = true;
1152 assert(fwdSuccessful && "Value to be forwarded is never used!");
1157 void UltraSparcInstrInfo::
1158 CreateCopyInstructionsByType(const TargetMachine& target,
1162 vector<MachineInstr*>& minstrVec) const
1164 bool loadConstantToReg = false;
1166 const Type* resultType = dest->getType();
1168 MachineOpCode opCode = ChooseAddInstructionByType(resultType);
1169 if (opCode == INVALID_OPCODE)
1171 assert(0 && "Unsupported result type in CreateCopyInstructionsByType()");
1175 // if `src' is a constant that doesn't fit in the immed field or if it is
1176 // a global variable (i.e., a constant address), generate a load
1177 // instruction instead of an add
1179 if (isa<Constant>(src))
1181 unsigned int machineRegNum;
1183 MachineOperand::MachineOperandType opType =
1184 ChooseRegOrImmed(src, opCode, target, /*canUseImmed*/ true,
1185 machineRegNum, immedValue);
1187 if (opType == MachineOperand::MO_VirtualRegister)
1188 loadConstantToReg = true;
1190 else if (isa<GlobalValue>(src))
1191 loadConstantToReg = true;
1193 if (loadConstantToReg)
1194 { // `src' is constant and cannot fit in immed field for the ADD
1195 // Insert instructions to "load" the constant into a register
1196 vector<TmpInstruction*> tempVec;
1197 target.getInstrInfo().CreateCodeToLoadConst(F, src, dest,
1198 minstrVec, tempVec);
1199 for (unsigned i=0; i < tempVec.size(); i++)
1200 MachineCodeForInstruction::get(dest).addTemp(tempVec[i]);
1203 { // Create an add-with-0 instruction of the appropriate type.
1204 // Make `src' the second operand, in case it is a constant
1205 // Use (unsigned long) 0 for a NULL pointer value.
1207 const Type* zeroValueType =
1208 (resultType->getPrimitiveID() == Type::PointerTyID)? Type::ULongTy
1210 MachineInstr* minstr = new MachineInstr(opCode);
1211 minstr->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister,
1212 Constant::getNullConstant(zeroValueType));
1213 minstr->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister, src);
1214 minstr->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister,dest);
1215 minstrVec.push_back(minstr);
1221 //******************* Externally Visible Functions *************************/
1225 //------------------------------------------------------------------------
1226 // External Function: ThisIsAChainRule
1229 // Check if a given BURG rule is a chain rule.
1230 //------------------------------------------------------------------------
1233 ThisIsAChainRule(int eruleno)
1237 case 111: // stmt: reg
1238 case 113: // stmt: bool
1261 return false; break;
1266 //------------------------------------------------------------------------
1267 // External Function: GetInstructionsByRule
1270 // Choose machine instructions for the SPARC according to the
1271 // patterns chosen by the BURG-generated parser.
1272 //------------------------------------------------------------------------
1275 GetInstructionsByRule(InstructionNode* subtreeRoot,
1278 TargetMachine &target,
1279 vector<MachineInstr*>& mvec)
1281 bool checkCast = false; // initialize here to use fall-through
1283 int forwardOperandNum = -1;
1284 unsigned int allocaSize = 0;
1285 MachineInstr* M, *M2;
1290 // If the code for this instruction was folded into the parent (user),
1292 if (subtreeRoot->isFoldedIntoParent())
1296 // Let's check for chain rules outside the switch so that we don't have
1297 // to duplicate the list of chain rule production numbers here again
1299 if (ThisIsAChainRule(ruleForNode))
1301 // Chain rules have a single nonterminal on the RHS.
1302 // Get the rule that matches the RHS non-terminal and use that instead.
1304 assert(nts[0] && ! nts[1]
1305 && "A chain rule should have only one RHS non-terminal!");
1306 nextRule = burm_rule(subtreeRoot->state, nts[0]);
1307 nts = burm_nts[nextRule];
1308 GetInstructionsByRule(subtreeRoot, nextRule, nts, target, mvec);
1312 switch(ruleForNode) {
1313 case 1: // stmt: Ret
1314 case 2: // stmt: RetValue(reg)
1315 { // NOTE: Prepass of register allocation is responsible
1316 // for moving return value to appropriate register.
1317 // Mark the return-address register as a hidden virtual reg.
1318 // Mark the return value register as an implicit ref of
1319 // the machine instruction.
1320 // Finally put a NOP in the delay slot.
1321 ReturnInst *returnInstr =
1322 cast<ReturnInst>(subtreeRoot->getInstruction());
1323 assert(returnInstr->getOpcode() == Instruction::Ret);
1325 Instruction* returnReg = new TmpInstruction(returnInstr);
1326 MachineCodeForInstruction::get(returnInstr).addTemp(returnReg);
1328 M = new MachineInstr(JMPLRET);
1329 M->SetMachineOperandReg(0, MachineOperand::MO_VirtualRegister,
1331 M->SetMachineOperandConst(1,MachineOperand::MO_SignExtendedImmed,
1333 M->SetMachineOperandReg(2, target.getRegInfo().getZeroRegNum());
1335 if (returnInstr->getReturnValue() != NULL)
1336 M->addImplicitRef(returnInstr->getReturnValue());
1339 mvec.push_back(new MachineInstr(NOP));
1344 case 3: // stmt: Store(reg,reg)
1345 case 4: // stmt: Store(reg,ptrreg)
1346 mvec.push_back(new MachineInstr(
1347 ChooseStoreInstruction(
1348 subtreeRoot->leftChild()->getValue()->getType())));
1349 SetOperandsForMemInstr(mvec, mvec.end()-1, subtreeRoot, target);
1352 case 5: // stmt: BrUncond
1353 M = new MachineInstr(BA);
1354 M->SetMachineOperandVal(0, MachineOperand::MO_CCRegister,
1356 M->SetMachineOperandVal(1, MachineOperand::MO_PCRelativeDisp,
1357 cast<BranchInst>(subtreeRoot->getInstruction())->getSuccessor(0));
1361 mvec.push_back(new MachineInstr(NOP));
1364 case 206: // stmt: BrCond(setCCconst)
1365 { // setCCconst => boolean was computed with `%b = setCC type reg1 const'
1366 // If the constant is ZERO, we can use the branch-on-integer-register
1367 // instructions and avoid the SUBcc instruction entirely.
1368 // Otherwise this is just the same as case 5, so just fall through.
1370 InstrTreeNode* constNode = subtreeRoot->leftChild()->rightChild();
1372 constNode->getNodeType() ==InstrTreeNode::NTConstNode);
1373 Constant *constVal = cast<Constant>(constNode->getValue());
1376 if ((constVal->getType()->isIntegral()
1377 || constVal->getType()->isPointerType())
1378 && GetConstantValueAsSignedInt(constVal, isValidConst) == 0
1381 // That constant is a zero after all...
1382 // Use the left child of setCC as the first argument!
1383 // Mark the setCC node so that no code is generated for it.
1384 InstructionNode* setCCNode = (InstructionNode*)
1385 subtreeRoot->leftChild();
1386 assert(setCCNode->getOpLabel() == SetCCOp);
1387 setCCNode->markFoldedIntoParent();
1389 BranchInst* brInst=cast<BranchInst>(subtreeRoot->getInstruction());
1391 M = new MachineInstr(ChooseBprInstruction(subtreeRoot));
1392 M->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister,
1393 setCCNode->leftChild()->getValue());
1394 M->SetMachineOperandVal(1, MachineOperand::MO_PCRelativeDisp,
1395 brInst->getSuccessor(0));
1399 mvec.push_back(new MachineInstr(NOP));
1402 M = new MachineInstr(BA);
1403 M->SetMachineOperandVal(0, MachineOperand::MO_CCRegister,
1405 M->SetMachineOperandVal(1, MachineOperand::MO_PCRelativeDisp,
1406 brInst->getSuccessor(1));
1410 mvec.push_back(new MachineInstr(NOP));
1414 // ELSE FALL THROUGH
1417 case 6: // stmt: BrCond(bool)
1418 { // bool => boolean was computed with some boolean operator
1419 // (SetCC, Not, ...). We need to check whether the type was a FP,
1420 // signed int or unsigned int, and check the branching condition in
1421 // order to choose the branch to use.
1422 // If it is an integer CC, we also need to find the unique
1423 // TmpInstruction representing that CC.
1425 BranchInst* brInst = cast<BranchInst>(subtreeRoot->getInstruction());
1427 M = new MachineInstr(ChooseBccInstruction(subtreeRoot, isFPBranch));
1429 Value* ccValue = GetTmpForCC(subtreeRoot->leftChild()->getValue(),
1430 brInst->getParent()->getParent(),
1431 isFPBranch? Type::FloatTy : Type::IntTy);
1433 M->SetMachineOperandVal(0, MachineOperand::MO_CCRegister, ccValue);
1434 M->SetMachineOperandVal(1, MachineOperand::MO_PCRelativeDisp,
1435 brInst->getSuccessor(0));
1439 mvec.push_back(new MachineInstr(NOP));
1442 M = new MachineInstr(BA);
1443 M->SetMachineOperandVal(0, MachineOperand::MO_CCRegister,
1445 M->SetMachineOperandVal(1, MachineOperand::MO_PCRelativeDisp,
1446 brInst->getSuccessor(1));
1450 mvec.push_back(new MachineInstr(NOP));
1454 case 208: // stmt: BrCond(boolconst)
1456 // boolconst => boolean is a constant; use BA to first or second label
1457 Constant* constVal =
1458 cast<Constant>(subtreeRoot->leftChild()->getValue());
1459 unsigned dest = cast<ConstantBool>(constVal)->getValue()? 0 : 1;
1461 M = new MachineInstr(BA);
1462 M->SetMachineOperandVal(0, MachineOperand::MO_CCRegister,
1464 M->SetMachineOperandVal(1, MachineOperand::MO_PCRelativeDisp,
1465 ((BranchInst*) subtreeRoot->getInstruction())->getSuccessor(dest));
1469 mvec.push_back(new MachineInstr(NOP));
1473 case 8: // stmt: BrCond(boolreg)
1474 { // boolreg => boolean is stored in an existing register.
1475 // Just use the branch-on-integer-register instruction!
1477 M = new MachineInstr(BRNZ);
1478 M->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister,
1479 subtreeRoot->leftChild()->getValue());
1480 M->SetMachineOperandVal(1, MachineOperand::MO_PCRelativeDisp,
1481 ((BranchInst*) subtreeRoot->getInstruction())->getSuccessor(0));
1485 mvec.push_back(new MachineInstr(NOP));
1488 M = new MachineInstr(BA);
1489 M->SetMachineOperandVal(0, MachineOperand::MO_CCRegister,
1491 M->SetMachineOperandVal(1, MachineOperand::MO_PCRelativeDisp,
1492 ((BranchInst*) subtreeRoot->getInstruction())->getSuccessor(1));
1496 mvec.push_back(new MachineInstr(NOP));
1500 case 9: // stmt: Switch(reg)
1501 assert(0 && "*** SWITCH instruction is not implemented yet.");
1504 case 10: // reg: VRegList(reg, reg)
1505 assert(0 && "VRegList should never be the topmost non-chain rule");
1508 case 21: // bool: Not(bool): Both these are implemented as:
1509 case 421: // reg: BNot(reg) : reg = reg XOR-NOT 0
1510 M = new MachineInstr(XNOR);
1511 M->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister,
1512 subtreeRoot->leftChild()->getValue());
1513 M->SetMachineOperandReg(1, target.getRegInfo().getZeroRegNum());
1514 M->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister,
1515 subtreeRoot->getValue());
1519 case 322: // reg: ToBoolTy(bool):
1520 case 22: // reg: ToBoolTy(reg):
1522 const Type* opType = subtreeRoot->leftChild()->getValue()->getType();
1523 assert(opType->isIntegral() || opType->isPointerType()
1524 || opType == Type::BoolTy);
1525 forwardOperandNum = 0; // forward first operand to user
1529 case 23: // reg: ToUByteTy(reg)
1530 case 25: // reg: ToUShortTy(reg)
1531 case 27: // reg: ToUIntTy(reg)
1532 case 29: // reg: ToULongTy(reg)
1534 const Type* opType = subtreeRoot->leftChild()->getValue()->getType();
1535 assert(opType->isIntegral() ||
1536 opType->isPointerType() ||
1537 opType == Type::BoolTy && "Cast is illegal for other types");
1538 forwardOperandNum = 0; // forward first operand to user
1542 case 24: // reg: ToSByteTy(reg)
1543 case 26: // reg: ToShortTy(reg)
1544 case 28: // reg: ToIntTy(reg)
1545 case 30: // reg: ToLongTy(reg)
1547 const Type* opType = subtreeRoot->leftChild()->getValue()->getType();
1548 if (opType->isIntegral()
1549 || opType->isPointerType()
1550 || opType == Type::BoolTy)
1552 forwardOperandNum = 0; // forward first operand to user
1556 // If the source operand is an FP type, the int result must be
1557 // copied from float to int register via memory!
1558 Instruction *dest = subtreeRoot->getInstruction();
1559 Value* leftVal = subtreeRoot->leftChild()->getValue();
1561 vector<MachineInstr*> minstrVec;
1563 if (opType == Type::FloatTy || opType == Type::DoubleTy)
1565 // Create a temporary to represent the INT register
1566 // into which the FP value will be copied via memory.
1567 // The type of this temporary will determine the FP
1568 // register used: single-prec for a 32-bit int or smaller,
1569 // double-prec for a 64-bit int.
1571 const Type* destTypeToUse =
1572 (dest->getType() == Type::LongTy)? Type::DoubleTy
1574 destForCast = new TmpInstruction(destTypeToUse, leftVal);
1575 MachineCodeForInstruction &destMCFI =
1576 MachineCodeForInstruction::get(dest);
1577 destMCFI.addTemp(destForCast);
1579 vector<TmpInstruction*> tempVec;
1580 target.getInstrInfo().CreateCodeToCopyFloatToInt(
1581 dest->getParent()->getParent(),
1582 (TmpInstruction*) destForCast, dest,
1583 minstrVec, tempVec, target);
1585 for (unsigned i=0; i < tempVec.size(); ++i)
1586 destMCFI.addTemp(tempVec[i]);
1589 destForCast = leftVal;
1591 M = CreateConvertToIntInstr(subtreeRoot->getOpLabel(),
1592 leftVal, destForCast);
1595 // Append the copy code, if any, after the conversion instr.
1596 mvec.insert(mvec.end(), minstrVec.begin(), minstrVec.end());
1601 case 31: // reg: ToFloatTy(reg):
1602 case 32: // reg: ToDoubleTy(reg):
1603 case 232: // reg: ToDoubleTy(Constant):
1605 // If this instruction has a parent (a user) in the tree
1606 // and the user is translated as an FsMULd instruction,
1607 // then the cast is unnecessary. So check that first.
1608 // In the future, we'll want to do the same for the FdMULq instruction,
1609 // so do the check here instead of only for ToFloatTy(reg).
1611 if (subtreeRoot->parent() != NULL &&
1612 MachineCodeForInstruction::get(((InstructionNode*)subtreeRoot->parent())->getInstruction())[0]->getOpCode() == FSMULD)
1614 forwardOperandNum = 0; // forward first operand to user
1618 Value* leftVal = subtreeRoot->leftChild()->getValue();
1619 const Type* opType = leftVal->getType();
1620 MachineOpCode opCode=ChooseConvertToFloatInstr(
1621 subtreeRoot->getOpLabel(), opType);
1622 if (opCode == INVALID_OPCODE) // no conversion needed
1624 forwardOperandNum = 0; // forward first operand to user
1628 // If the source operand is a non-FP type it must be
1629 // first copied from int to float register via memory!
1630 Instruction *dest = subtreeRoot->getInstruction();
1633 if (opType != Type::FloatTy && opType != Type::DoubleTy)
1635 // Create a temporary to represent the FP register
1636 // into which the integer will be copied via memory.
1637 // The type of this temporary will determine the FP
1638 // register used: single-prec for a 32-bit int or smaller,
1639 // double-prec for a 64-bit int.
1641 const Type* srcTypeToUse =
1642 (leftVal->getType() == Type::LongTy)? Type::DoubleTy
1645 srcForCast = new TmpInstruction(srcTypeToUse, dest);
1646 MachineCodeForInstruction &destMCFI =
1647 MachineCodeForInstruction::get(dest);
1648 destMCFI.addTemp(srcForCast);
1650 vector<MachineInstr*> minstrVec;
1651 vector<TmpInstruction*> tempVec;
1652 target.getInstrInfo().CreateCodeToCopyIntToFloat(
1653 dest->getParent()->getParent(),
1654 leftVal, (TmpInstruction*) srcForCast,
1655 minstrVec, tempVec, target);
1657 mvec.insert(mvec.end(), minstrVec.begin(),minstrVec.end());
1659 for (unsigned i=0; i < tempVec.size(); ++i)
1660 destMCFI.addTemp(tempVec[i]);
1663 srcForCast = leftVal;
1665 M = new MachineInstr(opCode);
1666 M->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister,
1668 M->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister,
1675 case 19: // reg: ToArrayTy(reg):
1676 case 20: // reg: ToPointerTy(reg):
1677 forwardOperandNum = 0; // forward first operand to user
1680 case 233: // reg: Add(reg, Constant)
1681 M = CreateAddConstInstruction(subtreeRoot);
1687 // ELSE FALL THROUGH
1689 case 33: // reg: Add(reg, reg)
1690 mvec.push_back(new MachineInstr(ChooseAddInstruction(subtreeRoot)));
1691 Set3OperandsFromInstr(mvec.back(), subtreeRoot, target);
1694 case 234: // reg: Sub(reg, Constant)
1695 M = CreateSubConstInstruction(subtreeRoot);
1701 // ELSE FALL THROUGH
1703 case 34: // reg: Sub(reg, reg)
1704 mvec.push_back(new MachineInstr(ChooseSubInstructionByType(
1705 subtreeRoot->getInstruction()->getType())));
1706 Set3OperandsFromInstr(mvec.back(), subtreeRoot, target);
1709 case 135: // reg: Mul(todouble, todouble)
1713 case 35: // reg: Mul(reg, reg)
1715 MachineOpCode forceOp = ((checkCast && BothFloatToDouble(subtreeRoot))
1717 : INVALID_MACHINE_OPCODE);
1718 CreateMulInstruction(target,
1719 subtreeRoot->leftChild()->getValue(),
1720 subtreeRoot->rightChild()->getValue(),
1721 subtreeRoot->getInstruction(),
1725 case 335: // reg: Mul(todouble, todoubleConst)
1729 case 235: // reg: Mul(reg, Constant)
1731 MachineOpCode forceOp = ((checkCast && BothFloatToDouble(subtreeRoot))
1733 : INVALID_MACHINE_OPCODE);
1734 CreateMulInstruction(target,
1735 subtreeRoot->leftChild()->getValue(),
1736 subtreeRoot->rightChild()->getValue(),
1737 subtreeRoot->getInstruction(),
1741 case 236: // reg: Div(reg, Constant)
1743 CreateDivConstInstruction(target, subtreeRoot, mvec);
1744 if (mvec.size() > L)
1746 // ELSE FALL THROUGH
1748 case 36: // reg: Div(reg, reg)
1749 mvec.push_back(new MachineInstr(ChooseDivInstruction(target, subtreeRoot)));
1750 Set3OperandsFromInstr(mvec.back(), subtreeRoot, target);
1753 case 37: // reg: Rem(reg, reg)
1754 case 237: // reg: Rem(reg, Constant)
1756 Instruction* remInstr = subtreeRoot->getInstruction();
1758 TmpInstruction* quot = new TmpInstruction(
1759 subtreeRoot->leftChild()->getValue(),
1760 subtreeRoot->rightChild()->getValue());
1761 TmpInstruction* prod = new TmpInstruction(
1763 subtreeRoot->rightChild()->getValue());
1764 MachineCodeForInstruction::get(remInstr).addTemp(quot).addTemp(prod);
1766 M = new MachineInstr(ChooseDivInstruction(target, subtreeRoot));
1767 Set3OperandsFromInstr(M, subtreeRoot, target);
1768 M->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister,quot);
1771 M = new MachineInstr(ChooseMulInstructionByType(
1772 subtreeRoot->getInstruction()->getType()));
1773 M->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister,quot);
1774 M->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister,
1775 subtreeRoot->rightChild()->getValue());
1776 M->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister,prod);
1779 M = new MachineInstr(ChooseSubInstructionByType(
1780 subtreeRoot->getInstruction()->getType()));
1781 Set3OperandsFromInstr(M, subtreeRoot, target);
1782 M->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister,prod);
1788 case 38: // bool: And(bool, bool)
1789 case 238: // bool: And(bool, boolconst)
1790 case 338: // reg : BAnd(reg, reg)
1791 case 538: // reg : BAnd(reg, Constant)
1792 mvec.push_back(new MachineInstr(AND));
1793 Set3OperandsFromInstr(mvec.back(), subtreeRoot, target);
1796 case 138: // bool: And(bool, not)
1797 case 438: // bool: BAnd(bool, not)
1798 mvec.push_back(new MachineInstr(ANDN));
1799 Set3OperandsFromInstr(mvec.back(), subtreeRoot, target);
1802 case 39: // bool: Or(bool, bool)
1803 case 239: // bool: Or(bool, boolconst)
1804 case 339: // reg : BOr(reg, reg)
1805 case 539: // reg : BOr(reg, Constant)
1806 mvec.push_back(new MachineInstr(ORN));
1807 Set3OperandsFromInstr(mvec.back(), subtreeRoot, target);
1810 case 139: // bool: Or(bool, not)
1811 case 439: // bool: BOr(bool, not)
1812 mvec.push_back(new MachineInstr(ORN));
1813 Set3OperandsFromInstr(mvec.back(), subtreeRoot, target);
1816 case 40: // bool: Xor(bool, bool)
1817 case 240: // bool: Xor(bool, boolconst)
1818 case 340: // reg : BXor(reg, reg)
1819 case 540: // reg : BXor(reg, Constant)
1820 mvec.push_back(new MachineInstr(XOR));
1821 Set3OperandsFromInstr(mvec.back(), subtreeRoot, target);
1824 case 140: // bool: Xor(bool, not)
1825 case 440: // bool: BXor(bool, not)
1826 mvec.push_back(new MachineInstr(XNOR));
1827 Set3OperandsFromInstr(mvec.back(), subtreeRoot, target);
1830 case 41: // boolconst: SetCC(reg, Constant)
1832 // If the SetCC was folded into the user (parent), it will be
1833 // caught above. All other cases are the same as case 42,
1834 // so just fall through.
1836 case 42: // bool: SetCC(reg, reg):
1838 // This generates a SUBCC instruction, putting the difference in
1839 // a result register, and setting a condition code.
1841 // If the boolean result of the SetCC is used by anything other
1842 // than a single branch instruction, the boolean must be
1843 // computed and stored in the result register. Otherwise, discard
1844 // the difference (by using %g0) and keep only the condition code.
1846 // To compute the boolean result in a register we use a conditional
1847 // move, unless the result of the SUBCC instruction can be used as
1848 // the bool! This assumes that zero is FALSE and any non-zero
1851 InstructionNode* parentNode = (InstructionNode*) subtreeRoot->parent();
1852 Instruction* setCCInstr = subtreeRoot->getInstruction();
1853 bool keepBoolVal = (parentNode == NULL ||
1854 parentNode->getInstruction()->getOpcode()
1855 != Instruction::Br);
1856 bool subValIsBoolVal = setCCInstr->getOpcode() == Instruction::SetNE;
1857 bool keepSubVal = keepBoolVal && subValIsBoolVal;
1858 bool computeBoolVal = keepBoolVal && ! subValIsBoolVal;
1862 MachineOpCode movOpCode = 0;
1864 // Mark the 4th operand as being a CC register, and as a def
1865 // A TmpInstruction is created to represent the CC "result".
1866 // Unlike other instances of TmpInstruction, this one is used
1867 // by machine code of multiple LLVM instructions, viz.,
1868 // the SetCC and the branch. Make sure to get the same one!
1869 // Note that we do this even for FP CC registers even though they
1870 // are explicit operands, because the type of the operand
1871 // needs to be a floating point condition code, not an integer
1872 // condition code. Think of this as casting the bool result to
1873 // a FP condition code register.
1875 Value* leftVal = subtreeRoot->leftChild()->getValue();
1876 bool isFPCompare = (leftVal->getType() == Type::FloatTy ||
1877 leftVal->getType() == Type::DoubleTy);
1879 TmpInstruction* tmpForCC = GetTmpForCC(setCCInstr,
1880 setCCInstr->getParent()->getParent(),
1881 isFPCompare? Type::FloatTy : Type::IntTy);
1882 MachineCodeForInstruction::get(setCCInstr).addTemp(tmpForCC);
1886 // Integer condition: dest. should be %g0 or an integer register.
1887 // If result must be saved but condition is not SetEQ then we need
1888 // a separate instruction to compute the bool result, so discard
1889 // result of SUBcc instruction anyway.
1891 M = new MachineInstr(SUBcc);
1892 Set3OperandsFromInstr(M, subtreeRoot, target, ! keepSubVal);
1893 M->SetMachineOperandVal(3, MachineOperand::MO_CCRegister,
1894 tmpForCC, /*def*/true);
1898 { // recompute bool using the integer condition codes
1900 ChooseMovpccAfterSub(subtreeRoot,mustClearReg,valueToMove);
1905 // FP condition: dest of FCMP should be some FCCn register
1906 M = new MachineInstr(ChooseFcmpInstruction(subtreeRoot));
1907 M->SetMachineOperandVal(0, MachineOperand::MO_CCRegister,
1909 M->SetMachineOperandVal(1,MachineOperand::MO_VirtualRegister,
1910 subtreeRoot->leftChild()->getValue());
1911 M->SetMachineOperandVal(2,MachineOperand::MO_VirtualRegister,
1912 subtreeRoot->rightChild()->getValue());
1916 {// recompute bool using the FP condition codes
1917 mustClearReg = true;
1919 movOpCode = ChooseMovFpccInstruction(subtreeRoot);
1926 {// Unconditionally set register to 0
1927 M = new MachineInstr(SETHI);
1928 M->SetMachineOperandConst(0,MachineOperand::MO_UnextendedImmed,
1930 M->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister,
1935 // Now conditionally move `valueToMove' (0 or 1) into the register
1936 M = new MachineInstr(movOpCode);
1937 M->SetMachineOperandVal(0, MachineOperand::MO_CCRegister,
1939 M->SetMachineOperandConst(1, MachineOperand::MO_UnextendedImmed,
1941 M->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister,
1948 case 43: // boolreg: VReg
1949 case 44: // boolreg: Constant
1952 case 51: // reg: Load(reg)
1953 case 52: // reg: Load(ptrreg)
1954 case 53: // reg: LoadIdx(reg,reg)
1955 case 54: // reg: LoadIdx(ptrreg,reg)
1956 mvec.push_back(new MachineInstr(ChooseLoadInstruction(
1957 subtreeRoot->getValue()->getType())));
1958 SetOperandsForMemInstr(mvec, mvec.end()-1, subtreeRoot, target);
1961 case 55: // reg: GetElemPtr(reg)
1962 case 56: // reg: GetElemPtrIdx(reg,reg)
1963 // If the GetElemPtr was folded into the user (parent), it will be
1964 // caught above. For other cases, we have to compute the address.
1965 mvec.push_back(new MachineInstr(ADD));
1966 SetOperandsForMemInstr(mvec, mvec.end()-1, subtreeRoot, target);
1969 case 57: // reg: Alloca: Implement as 1 instruction:
1970 { // add %fp, offsetFromFP -> result
1971 AllocationInst* instr =
1972 cast<AllocationInst>(subtreeRoot->getInstruction());
1973 unsigned int tsize =
1974 target.findOptimalStorageSize(instr->getAllocatedType());
1976 CreateCodeForFixedSizeAlloca(target, instr, tsize, 1, mvec);
1980 case 58: // reg: Alloca(reg): Implement as 3 instructions:
1981 // mul num, typeSz -> tmp
1982 // sub %sp, tmp -> %sp
1983 { // add %sp, frameSizeBelowDynamicArea -> result
1984 AllocationInst* instr =
1985 cast<AllocationInst>(subtreeRoot->getInstruction());
1986 const Type* eltType = instr->getAllocatedType();
1988 // If #elements is constant, use simpler code for fixed-size allocas
1989 int tsize = (int) target.findOptimalStorageSize(eltType);
1990 Value* numElementsVal = NULL;
1991 bool isArray = instr->isArrayAllocation();
1994 isa<Constant>(numElementsVal = instr->getArraySize()))
1995 { // total size is constant: generate code for fixed-size alloca
1996 unsigned int numElements = isArray?
1997 cast<ConstantUInt>(numElementsVal)->getValue() : 1;
1998 CreateCodeForFixedSizeAlloca(target, instr, tsize,
2001 else // total size is not constant.
2002 CreateCodeForVariableSizeAlloca(target, instr, tsize,
2003 numElementsVal, mvec);
2007 case 61: // reg: Call
2008 { // Generate a direct (CALL) or indirect (JMPL). depending
2009 // Mark the return-address register and the indirection
2010 // register (if any) as hidden virtual registers.
2011 // Also, mark the operands of the Call and return value (if
2012 // any) as implicit operands of the CALL machine instruction.
2014 // If this is a varargs function, floating point arguments
2015 // have to passed in integer registers so insert
2016 // copy-float-to-int instructions for each float operand.
2018 CallInst *callInstr = cast<CallInst>(subtreeRoot->getInstruction());
2019 Value *callee = callInstr->getCalledValue();
2021 // Create hidden virtual register for return address, with type void*.
2022 Instruction* retAddrReg =
2023 new TmpInstruction(PointerType::get(Type::VoidTy), callInstr);
2024 MachineCodeForInstruction::get(callInstr).addTemp(retAddrReg);
2026 // Generate the machine instruction and its operands.
2027 // Use CALL for direct function calls; this optimistically assumes
2028 // the PC-relative address fits in the CALL address field (22 bits).
2029 // Use JMPL for indirect calls.
2031 if (isa<Function>(callee))
2032 { // direct function call
2033 M = new MachineInstr(CALL);
2034 M->SetMachineOperandVal(0, MachineOperand::MO_PCRelativeDisp,
2038 { // indirect function call
2039 M = new MachineInstr(JMPLCALL);
2040 M->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister,
2042 M->SetMachineOperandConst(1, MachineOperand::MO_SignExtendedImmed,
2044 M->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister,
2050 // WARNING: Operands 0..N-1 must go in slots 0..N-1 of implicitUses.
2051 // The result value must go in slot N. This is assumed
2052 // in register allocation.
2054 // Add the call operands and return value as implicit refs
2055 // const Type* funcType = isa<Function>(callee)? callee->getType()
2056 // : cast<PointerType>(callee->getType())->getElementType();
2057 const Type* funcType = callee->getType();
2058 bool isVarArgs = cast<FunctionType>(cast<PointerType>(funcType)
2059 ->getElementType())->isVarArg();
2061 for (unsigned i=0, N=callInstr->getNumOperands(); i < N; ++i)
2062 if (callInstr->getOperand(i) != callee)
2064 Value* argVal = callInstr->getOperand(i);
2066 // Check for FP arguments to varargs functions
2067 if (isVarArgs && argVal->getType()->isFloatingPoint())
2068 { // Add a copy-float-to-int instruction
2069 MachineCodeForInstruction &destMCFI =
2070 MachineCodeForInstruction::get(callInstr);
2071 Instruction* intArgReg =
2072 new TmpInstruction(Type::IntTy, argVal);
2073 destMCFI.addTemp(intArgReg);
2075 vector<MachineInstr*> minstrVec;
2076 vector<TmpInstruction*> tempVec;
2077 target.getInstrInfo().CreateCodeToCopyFloatToInt(
2078 callInstr->getParent()->getParent(),
2079 argVal, (TmpInstruction*) intArgReg,
2080 minstrVec, tempVec, target);
2082 mvec.insert(mvec.begin(), minstrVec.begin(),minstrVec.end());
2084 for (unsigned i=0; i < tempVec.size(); ++i)
2085 destMCFI.addTemp(tempVec[i]);
2090 mvec.back()->addImplicitRef(argVal);
2093 if (callInstr->getType() != Type::VoidTy)
2094 mvec.back()->addImplicitRef(callInstr, /*isDef*/ true);
2096 // For the CALL instruction, the ret. addr. reg. is also implicit
2097 if (isa<Function>(callee))
2098 mvec.back()->addImplicitRef(retAddrReg, /*isDef*/ true);
2101 mvec.push_back(new MachineInstr(NOP));
2105 case 62: // reg: Shl(reg, reg)
2106 { const Type* opType = subtreeRoot->leftChild()->getValue()->getType();
2107 assert(opType->isIntegral()
2108 || opType == Type::BoolTy
2109 || opType->isPointerType()&& "Shl unsupported for other types");
2110 mvec.push_back(new MachineInstr((opType == Type::LongTy)? SLLX : SLL));
2111 Set3OperandsFromInstr(mvec.back(), subtreeRoot, target);
2115 case 63: // reg: Shr(reg, reg)
2116 { const Type* opType = subtreeRoot->leftChild()->getValue()->getType();
2117 assert(opType->isIntegral()
2118 || opType == Type::BoolTy
2119 || opType->isPointerType() &&"Shr unsupported for other types");
2120 mvec.push_back(new MachineInstr((opType->isSigned()
2121 ? ((opType == Type::LongTy)? SRAX : SRA)
2122 : ((opType == Type::LongTy)? SRLX : SRL))));
2123 Set3OperandsFromInstr(mvec.back(), subtreeRoot, target);
2127 case 64: // reg: Phi(reg,reg)
2128 break; // don't forward the value
2130 #undef NEED_PHI_MACHINE_INSTRS
2131 #ifdef NEED_PHI_MACHINE_INSTRS
2132 { // This instruction has variable #operands, so resultPos is 0.
2133 Instruction* phi = subtreeRoot->getInstruction();
2134 M = new MachineInstr(PHI, 1 + phi->getNumOperands());
2135 M->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister,
2136 subtreeRoot->getValue());
2137 for (unsigned i=0, N=phi->getNumOperands(); i < N; i++)
2138 M->SetMachineOperandVal(i+1, MachineOperand::MO_VirtualRegister,
2139 phi->getOperand(i));
2143 #endif // NEED_PHI_MACHINE_INSTRS
2146 case 71: // reg: VReg
2147 case 72: // reg: Constant
2148 break; // don't forward the value
2151 assert(0 && "Unrecognized BURG rule");
2156 if (forwardOperandNum >= 0)
2157 { // We did not generate a machine instruction but need to use operand.
2158 // If user is in the same tree, replace Value in its machine operand.
2159 // If not, insert a copy instruction which should get coalesced away
2160 // by register allocation.
2161 if (subtreeRoot->parent() != NULL)
2162 ForwardOperand(subtreeRoot, subtreeRoot->parent(), forwardOperandNum);
2165 vector<MachineInstr*> minstrVec;
2166 target.getInstrInfo().CreateCopyInstructionsByType(target,
2167 subtreeRoot->getInstruction()->getParent()->getParent(),
2168 subtreeRoot->getInstruction()->getOperand(forwardOperandNum),
2169 subtreeRoot->getInstruction(), minstrVec);
2170 assert(minstrVec.size() > 0);
2171 mvec.insert(mvec.end(), minstrVec.begin(), minstrVec.end());