2 //***************************************************************************
4 // SparcInstrSelection.cpp
7 // BURS instruction selection for SPARC V9 architecture.
10 // 7/02/01 - Vikram Adve - Created
11 //**************************************************************************/
13 #include "SparcInternals.h"
14 #include "SparcInstrSelectionSupport.h"
15 #include "SparcRegClassInfo.h"
16 #include "llvm/CodeGen/InstrSelectionSupport.h"
17 #include "llvm/CodeGen/MachineInstr.h"
18 #include "llvm/CodeGen/InstrForest.h"
19 #include "llvm/CodeGen/InstrSelection.h"
20 #include "llvm/CodeGen/MachineCodeForMethod.h"
21 #include "llvm/CodeGen/MachineCodeForInstruction.h"
22 #include "llvm/DerivedTypes.h"
23 #include "llvm/iTerminators.h"
24 #include "llvm/iMemory.h"
25 #include "llvm/iOther.h"
26 #include "llvm/BasicBlock.h"
27 #include "llvm/Method.h"
28 #include "llvm/ConstantVals.h"
29 #include "Support/MathExtras.h"
33 //************************* Forward Declarations ***************************/
36 static void SetMemOperands_Internal (vector<MachineInstr*>& mvec,
37 vector<MachineInstr*>::iterator mvecI,
38 const InstructionNode* vmInstrNode,
40 std::vector<Value*>& idxVec,
41 const TargetMachine& target);
44 //************************ Internal Functions ******************************/
47 static inline MachineOpCode
48 ChooseBprInstruction(const InstructionNode* instrNode)
52 Instruction* setCCInstr =
53 ((InstructionNode*) instrNode->leftChild())->getInstruction();
55 switch(setCCInstr->getOpcode())
57 case Instruction::SetEQ: opCode = BRZ; break;
58 case Instruction::SetNE: opCode = BRNZ; break;
59 case Instruction::SetLE: opCode = BRLEZ; break;
60 case Instruction::SetGE: opCode = BRGEZ; break;
61 case Instruction::SetLT: opCode = BRLZ; break;
62 case Instruction::SetGT: opCode = BRGZ; break;
64 assert(0 && "Unrecognized VM instruction!");
65 opCode = INVALID_OPCODE;
73 static inline MachineOpCode
74 ChooseBpccInstruction(const InstructionNode* instrNode,
75 const BinaryOperator* setCCInstr)
77 MachineOpCode opCode = INVALID_OPCODE;
79 bool isSigned = setCCInstr->getOperand(0)->getType()->isSigned();
83 switch(setCCInstr->getOpcode())
85 case Instruction::SetEQ: opCode = BE; break;
86 case Instruction::SetNE: opCode = BNE; break;
87 case Instruction::SetLE: opCode = BLE; break;
88 case Instruction::SetGE: opCode = BGE; break;
89 case Instruction::SetLT: opCode = BL; break;
90 case Instruction::SetGT: opCode = BG; break;
92 assert(0 && "Unrecognized VM instruction!");
98 switch(setCCInstr->getOpcode())
100 case Instruction::SetEQ: opCode = BE; break;
101 case Instruction::SetNE: opCode = BNE; break;
102 case Instruction::SetLE: opCode = BLEU; break;
103 case Instruction::SetGE: opCode = BCC; break;
104 case Instruction::SetLT: opCode = BCS; break;
105 case Instruction::SetGT: opCode = BGU; break;
107 assert(0 && "Unrecognized VM instruction!");
115 static inline MachineOpCode
116 ChooseBFpccInstruction(const InstructionNode* instrNode,
117 const BinaryOperator* setCCInstr)
119 MachineOpCode opCode = INVALID_OPCODE;
121 switch(setCCInstr->getOpcode())
123 case Instruction::SetEQ: opCode = FBE; break;
124 case Instruction::SetNE: opCode = FBNE; break;
125 case Instruction::SetLE: opCode = FBLE; break;
126 case Instruction::SetGE: opCode = FBGE; break;
127 case Instruction::SetLT: opCode = FBL; break;
128 case Instruction::SetGT: opCode = FBG; break;
130 assert(0 && "Unrecognized VM instruction!");
138 // Create a unique TmpInstruction for a boolean value,
139 // representing the CC register used by a branch on that value.
140 // For now, hack this using a little static cache of TmpInstructions.
141 // Eventually the entire BURG instruction selection should be put
142 // into a separate class that can hold such information.
143 // The static cache is not too bad because the memory for these
144 // TmpInstructions will be freed along with the rest of the Method anyway.
146 static TmpInstruction*
147 GetTmpForCC(Value* boolVal, const Method* method, const Type* ccType)
149 typedef std::hash_map<const Value*, TmpInstruction*> BoolTmpCache;
150 static BoolTmpCache boolToTmpCache; // Map boolVal -> TmpInstruction*
151 static const Method* lastMethod = NULL; // Use to flush cache between methods
153 assert(boolVal->getType() == Type::BoolTy && "Weird but ok! Delete assert");
155 if (lastMethod != method)
158 boolToTmpCache.clear();
161 // Look for tmpI and create a new one otherwise. The new value is
162 // directly written to map using the ref returned by operator[].
163 TmpInstruction*& tmpI = boolToTmpCache[boolVal];
165 tmpI = new TmpInstruction(ccType, boolVal);
171 static inline MachineOpCode
172 ChooseBccInstruction(const InstructionNode* instrNode,
175 InstructionNode* setCCNode = (InstructionNode*) instrNode->leftChild();
176 BinaryOperator* setCCInstr = (BinaryOperator*) setCCNode->getInstruction();
177 const Type* setCCType = setCCInstr->getOperand(0)->getType();
179 isFPBranch = (setCCType == Type::FloatTy || setCCType == Type::DoubleTy);
182 return ChooseBFpccInstruction(instrNode, setCCInstr);
184 return ChooseBpccInstruction(instrNode, setCCInstr);
188 static inline MachineOpCode
189 ChooseMovFpccInstruction(const InstructionNode* instrNode)
191 MachineOpCode opCode = INVALID_OPCODE;
193 switch(instrNode->getInstruction()->getOpcode())
195 case Instruction::SetEQ: opCode = MOVFE; break;
196 case Instruction::SetNE: opCode = MOVFNE; break;
197 case Instruction::SetLE: opCode = MOVFLE; break;
198 case Instruction::SetGE: opCode = MOVFGE; break;
199 case Instruction::SetLT: opCode = MOVFL; break;
200 case Instruction::SetGT: opCode = MOVFG; break;
202 assert(0 && "Unrecognized VM instruction!");
210 // Assumes that SUBcc v1, v2 -> v3 has been executed.
211 // In most cases, we want to clear v3 and then follow it by instruction
213 // Set mustClearReg=false if v3 need not be cleared before conditional move.
214 // Set valueToMove=0 if we want to conditionally move 0 instead of 1
215 // (i.e., we want to test inverse of a condition)
216 // (The latter two cases do not seem to arise because SetNE needs nothing.)
219 ChooseMovpccAfterSub(const InstructionNode* instrNode,
223 MachineOpCode opCode = INVALID_OPCODE;
227 switch(instrNode->getInstruction()->getOpcode())
229 case Instruction::SetEQ: opCode = MOVE; break;
230 case Instruction::SetLE: opCode = MOVLE; break;
231 case Instruction::SetGE: opCode = MOVGE; break;
232 case Instruction::SetLT: opCode = MOVL; break;
233 case Instruction::SetGT: opCode = MOVG; break;
234 case Instruction::SetNE: assert(0 && "No move required!"); break;
235 default: assert(0 && "Unrecognized VM instr!"); break;
241 static inline MachineOpCode
242 ChooseConvertToFloatInstr(const InstructionNode* instrNode,
245 MachineOpCode opCode = INVALID_OPCODE;
247 switch(instrNode->getOpLabel())
250 if (opType == Type::SByteTy || opType == Type::ShortTy || opType == Type::IntTy)
252 else if (opType == Type::LongTy)
254 else if (opType == Type::DoubleTy)
256 else if (opType == Type::FloatTy)
259 assert(0 && "Cannot convert this type to FLOAT on SPARC");
263 // This is usually used in conjunction with CreateCodeToCopyIntToFloat().
264 // Both functions should treat the integer as a 32-bit value for types
265 // of 4 bytes or less, and as a 64-bit value otherwise.
266 if (opType == Type::SByteTy || opType == Type::UByteTy ||
267 opType == Type::ShortTy || opType == Type::UShortTy ||
268 opType == Type::IntTy || opType == Type::UIntTy)
270 else if (opType == Type::LongTy || opType == Type::ULongTy)
272 else if (opType == Type::FloatTy)
274 else if (opType == Type::DoubleTy)
277 assert(0 && "Cannot convert this type to DOUBLE on SPARC");
287 static inline MachineOpCode
288 ChooseConvertToIntInstr(const InstructionNode* instrNode,
291 MachineOpCode opCode = INVALID_OPCODE;;
293 int instrType = (int) instrNode->getOpLabel();
295 if (instrType == ToSByteTy || instrType == ToShortTy || instrType == ToIntTy)
297 switch (opType->getPrimitiveID())
299 case Type::FloatTyID: opCode = FSTOI; break;
300 case Type::DoubleTyID: opCode = FDTOI; break;
302 assert(0 && "Non-numeric non-bool type cannot be converted to Int");
306 else if (instrType == ToLongTy)
308 switch (opType->getPrimitiveID())
310 case Type::FloatTyID: opCode = FSTOX; break;
311 case Type::DoubleTyID: opCode = FDTOX; break;
313 assert(0 && "Non-numeric non-bool type cannot be converted to Long");
318 assert(0 && "Should not get here, Mo!");
324 static inline MachineOpCode
325 ChooseAddInstructionByType(const Type* resultType)
327 MachineOpCode opCode = INVALID_OPCODE;
329 if (resultType->isIntegral() ||
330 resultType->isPointerType() ||
331 resultType->isLabelType() ||
332 isa<MethodType>(resultType) ||
333 resultType == Type::BoolTy)
338 switch(resultType->getPrimitiveID())
340 case Type::FloatTyID: opCode = FADDS; break;
341 case Type::DoubleTyID: opCode = FADDD; break;
342 default: assert(0 && "Invalid type for ADD instruction"); break;
349 static inline MachineOpCode
350 ChooseAddInstruction(const InstructionNode* instrNode)
352 return ChooseAddInstructionByType(instrNode->getInstruction()->getType());
356 static inline MachineInstr*
357 CreateMovFloatInstruction(const InstructionNode* instrNode,
358 const Type* resultType)
360 MachineInstr* minstr = new MachineInstr((resultType == Type::FloatTy)
362 minstr->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister,
363 instrNode->leftChild()->getValue());
364 minstr->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister,
365 instrNode->getValue());
369 static inline MachineInstr*
370 CreateAddConstInstruction(const InstructionNode* instrNode)
372 MachineInstr* minstr = NULL;
374 Value* constOp = ((InstrTreeNode*) instrNode->rightChild())->getValue();
375 assert(isa<Constant>(constOp));
377 // Cases worth optimizing are:
378 // (1) Add with 0 for float or double: use an FMOV of appropriate type,
379 // instead of an FADD (1 vs 3 cycles). There is no integer MOV.
381 const Type* resultType = instrNode->getInstruction()->getType();
383 if (resultType == Type::FloatTy ||
384 resultType == Type::DoubleTy)
386 double dval = cast<ConstantFP>(constOp)->getValue();
388 minstr = CreateMovFloatInstruction(instrNode, resultType);
395 static inline MachineOpCode
396 ChooseSubInstructionByType(const Type* resultType)
398 MachineOpCode opCode = INVALID_OPCODE;
400 if (resultType->isIntegral() ||
401 resultType->isPointerType())
406 switch(resultType->getPrimitiveID())
408 case Type::FloatTyID: opCode = FSUBS; break;
409 case Type::DoubleTyID: opCode = FSUBD; break;
410 default: assert(0 && "Invalid type for SUB instruction"); break;
417 static inline MachineInstr*
418 CreateSubConstInstruction(const InstructionNode* instrNode)
420 MachineInstr* minstr = NULL;
422 Value* constOp = ((InstrTreeNode*) instrNode->rightChild())->getValue();
423 assert(isa<Constant>(constOp));
425 // Cases worth optimizing are:
426 // (1) Sub with 0 for float or double: use an FMOV of appropriate type,
427 // instead of an FSUB (1 vs 3 cycles). There is no integer MOV.
429 const Type* resultType = instrNode->getInstruction()->getType();
431 if (resultType == Type::FloatTy ||
432 resultType == Type::DoubleTy)
434 double dval = cast<ConstantFP>(constOp)->getValue();
436 minstr = CreateMovFloatInstruction(instrNode, resultType);
443 static inline MachineOpCode
444 ChooseFcmpInstruction(const InstructionNode* instrNode)
446 MachineOpCode opCode = INVALID_OPCODE;
448 Value* operand = ((InstrTreeNode*) instrNode->leftChild())->getValue();
449 switch(operand->getType()->getPrimitiveID()) {
450 case Type::FloatTyID: opCode = FCMPS; break;
451 case Type::DoubleTyID: opCode = FCMPD; break;
452 default: assert(0 && "Invalid type for FCMP instruction"); break;
459 // Assumes that leftArg and rightArg are both cast instructions.
462 BothFloatToDouble(const InstructionNode* instrNode)
464 InstrTreeNode* leftArg = instrNode->leftChild();
465 InstrTreeNode* rightArg = instrNode->rightChild();
466 InstrTreeNode* leftArgArg = leftArg->leftChild();
467 InstrTreeNode* rightArgArg = rightArg->leftChild();
468 assert(leftArg->getValue()->getType() == rightArg->getValue()->getType());
470 // Check if both arguments are floats cast to double
471 return (leftArg->getValue()->getType() == Type::DoubleTy &&
472 leftArgArg->getValue()->getType() == Type::FloatTy &&
473 rightArgArg->getValue()->getType() == Type::FloatTy);
477 static inline MachineOpCode
478 ChooseMulInstructionByType(const Type* resultType)
480 MachineOpCode opCode = INVALID_OPCODE;
482 if (resultType->isIntegral())
485 switch(resultType->getPrimitiveID())
487 case Type::FloatTyID: opCode = FMULS; break;
488 case Type::DoubleTyID: opCode = FMULD; break;
489 default: assert(0 && "Invalid type for MUL instruction"); break;
497 static inline MachineInstr*
498 CreateIntNegInstruction(const TargetMachine& target,
501 MachineInstr* minstr = new MachineInstr(SUB);
502 minstr->SetMachineOperandReg(0, target.getRegInfo().getZeroRegNum());
503 minstr->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister, vreg);
504 minstr->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister, vreg);
509 // Does not create any instructions if we cannot exploit constant to
510 // create a cheaper instruction.
511 // This returns the approximate cost of the instructions generated,
512 // which is used to pick the cheapest when both operands are constant.
513 static inline unsigned int
514 CreateMulConstInstruction(const TargetMachine &target,
515 Value* lval, Value* rval, Value* destVal,
516 vector<MachineInstr*>& mvec)
518 /* An integer multiply is generally more costly than FP multiply */
519 unsigned int cost = target.getInstrInfo().minLatency(MULX);
520 MachineInstr* minstr1 = NULL;
521 MachineInstr* minstr2 = NULL;
523 Value* constOp = rval;
524 if (! isa<Constant>(constOp))
527 // Cases worth optimizing are:
528 // (1) Multiply by 0 or 1 for any type: replace with copy (ADD or FMOV)
529 // (2) Multiply by 2^x for integer types: replace with Shift
531 const Type* resultType = destVal->getType();
533 if (resultType->isIntegral() || resultType->isPointerType())
537 int64_t C = GetConstantValueAsSignedInt(constOp, isValidConst);
540 bool needNeg = false;
547 if (C == 0 || C == 1)
549 cost = target.getInstrInfo().minLatency(ADD);
550 minstr1 = new MachineInstr(ADD);
552 minstr1->SetMachineOperandReg(0,
553 target.getRegInfo().getZeroRegNum());
555 minstr1->SetMachineOperandVal(0,
556 MachineOperand::MO_VirtualRegister, lval);
557 minstr1->SetMachineOperandReg(1,
558 target.getRegInfo().getZeroRegNum());
560 else if (IsPowerOf2(C, pow))
562 minstr1 = new MachineInstr((resultType == Type::LongTy)
564 minstr1->SetMachineOperandVal(0,
565 MachineOperand::MO_VirtualRegister, lval);
566 minstr1->SetMachineOperandConst(1,
567 MachineOperand::MO_UnextendedImmed, pow);
570 if (minstr1 && needNeg)
571 { // insert <reg = SUB 0, reg> after the instr to flip the sign
572 minstr2 = CreateIntNegInstruction(target, destVal);
573 cost += target.getInstrInfo().minLatency(minstr2->getOpCode());
579 if (resultType == Type::FloatTy ||
580 resultType == Type::DoubleTy)
582 double dval = cast<ConstantFP>(constOp)->getValue();
585 bool needNeg = (dval < 0);
587 MachineOpCode opCode = needNeg
588 ? (resultType == Type::FloatTy? FNEGS : FNEGD)
589 : (resultType == Type::FloatTy? FMOVS : FMOVD);
591 minstr1 = new MachineInstr(opCode);
592 minstr1->SetMachineOperandVal(0,
593 MachineOperand::MO_VirtualRegister,
600 minstr1->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister,
605 mvec.push_back(minstr1);
606 cost = target.getInstrInfo().minLatency(minstr1->getOpCode());
610 assert(minstr1 && "Otherwise cost needs to be initialized to 0");
611 cost += target.getInstrInfo().minLatency(minstr2->getOpCode());
612 mvec.push_back(minstr2);
619 // Does not create any instructions if we cannot exploit constant to
620 // create a cheaper instruction.
623 CreateCheapestMulConstInstruction(const TargetMachine &target,
624 Value* lval, Value* rval, Value* destVal,
625 vector<MachineInstr*>& mvec)
628 if (isa<Constant>(lval) && isa<Constant>(rval))
629 { // both operands are constant: try both orders!
630 vector<MachineInstr*> mvec1, mvec2;
631 unsigned int lcost = CreateMulConstInstruction(target, lval, rval,
633 unsigned int rcost = CreateMulConstInstruction(target, rval, lval,
635 vector<MachineInstr*>& mincostMvec = (lcost <= rcost)? mvec1 : mvec2;
636 vector<MachineInstr*>& maxcostMvec = (lcost <= rcost)? mvec2 : mvec1;
637 mvec.insert(mvec.end(), mincostMvec.begin(), mincostMvec.end());
639 for (unsigned int i=0; i < maxcostMvec.size(); ++i)
640 delete maxcostMvec[i];
642 else if (isa<Constant>(rval)) // rval is constant, but not lval
643 CreateMulConstInstruction(target, lval, rval, destVal, mvec);
644 else if (isa<Constant>(lval)) // lval is constant, but not rval
645 CreateMulConstInstruction(target, lval, rval, destVal, mvec);
647 // else neither is constant
651 // Return NULL if we cannot exploit constant to create a cheaper instruction
653 CreateMulInstruction(const TargetMachine &target,
654 Value* lval, Value* rval, Value* destVal,
655 vector<MachineInstr*>& mvec,
656 MachineOpCode forceMulOp = INVALID_MACHINE_OPCODE)
658 unsigned int L = mvec.size();
659 CreateCheapestMulConstInstruction(target, lval, rval, destVal, mvec);
660 if (mvec.size() == L)
661 { // no instructions were added so create MUL reg, reg, reg.
662 // Use FSMULD if both operands are actually floats cast to doubles.
663 // Otherwise, use the default opcode for the appropriate type.
664 MachineOpCode mulOp = ((forceMulOp != INVALID_MACHINE_OPCODE)
666 : ChooseMulInstructionByType(destVal->getType()));
667 MachineInstr* M = new MachineInstr(mulOp);
668 M->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister, lval);
669 M->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister, rval);
670 M->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister, destVal);
676 // Generate a divide instruction for Div or Rem.
677 // For Rem, this assumes that the operand type will be signed if the result
678 // type is signed. This is correct because they must have the same sign.
680 static inline MachineOpCode
681 ChooseDivInstruction(TargetMachine &target,
682 const InstructionNode* instrNode)
684 MachineOpCode opCode = INVALID_OPCODE;
686 const Type* resultType = instrNode->getInstruction()->getType();
688 if (resultType->isIntegral())
689 opCode = resultType->isSigned()? SDIVX : UDIVX;
691 switch(resultType->getPrimitiveID())
693 case Type::FloatTyID: opCode = FDIVS; break;
694 case Type::DoubleTyID: opCode = FDIVD; break;
695 default: assert(0 && "Invalid type for DIV instruction"); break;
702 // Return NULL if we cannot exploit constant to create a cheaper instruction
704 CreateDivConstInstruction(TargetMachine &target,
705 const InstructionNode* instrNode,
706 vector<MachineInstr*>& mvec)
708 MachineInstr* minstr1 = NULL;
709 MachineInstr* minstr2 = NULL;
711 Value* constOp = ((InstrTreeNode*) instrNode->rightChild())->getValue();
712 if (! isa<Constant>(constOp))
715 // Cases worth optimizing are:
716 // (1) Divide by 1 for any type: replace with copy (ADD or FMOV)
717 // (2) Divide by 2^x for integer types: replace with SR[L or A]{X}
719 const Type* resultType = instrNode->getInstruction()->getType();
721 if (resultType->isIntegral())
725 int64_t C = GetConstantValueAsSignedInt(constOp, isValidConst);
728 bool needNeg = false;
737 minstr1 = new MachineInstr(ADD);
738 minstr1->SetMachineOperandVal(0,
739 MachineOperand::MO_VirtualRegister,
740 instrNode->leftChild()->getValue());
741 minstr1->SetMachineOperandReg(1,
742 target.getRegInfo().getZeroRegNum());
744 else if (IsPowerOf2(C, pow))
746 MachineOpCode opCode= ((resultType->isSigned())
747 ? (resultType==Type::LongTy)? SRAX : SRA
748 : (resultType==Type::LongTy)? SRLX : SRL);
749 minstr1 = new MachineInstr(opCode);
750 minstr1->SetMachineOperandVal(0,
751 MachineOperand::MO_VirtualRegister,
752 instrNode->leftChild()->getValue());
753 minstr1->SetMachineOperandConst(1,
754 MachineOperand::MO_UnextendedImmed,
758 if (minstr1 && needNeg)
759 { // insert <reg = SUB 0, reg> after the instr to flip the sign
760 minstr2 = CreateIntNegInstruction(target,
761 instrNode->getValue());
767 if (resultType == Type::FloatTy ||
768 resultType == Type::DoubleTy)
770 double dval = cast<ConstantFP>(constOp)->getValue();
773 bool needNeg = (dval < 0);
775 MachineOpCode opCode = needNeg
776 ? (resultType == Type::FloatTy? FNEGS : FNEGD)
777 : (resultType == Type::FloatTy? FMOVS : FMOVD);
779 minstr1 = new MachineInstr(opCode);
780 minstr1->SetMachineOperandVal(0,
781 MachineOperand::MO_VirtualRegister,
782 instrNode->leftChild()->getValue());
788 minstr1->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister,
789 instrNode->getValue());
792 mvec.push_back(minstr1);
794 mvec.push_back(minstr2);
799 CreateCodeForVariableSizeAlloca(const TargetMachine& target,
802 Value* numElementsVal,
803 vector<MachineInstr*>& getMvec)
807 // Create a Value to hold the (constant) element size
808 Value* tsizeVal = ConstantSInt::get(Type::IntTy, tsize);
810 // Get the constant offset from SP for dynamically allocated storage
811 // and create a temporary Value to hold it.
812 assert(result && result->getParent() && "Result value is not part of a method?");
813 Method* method = result->getParent()->getParent();
814 MachineCodeForMethod& mcInfo = MachineCodeForMethod::get(method);
816 ConstantSInt* dynamicAreaOffset =
817 ConstantSInt::get(Type::IntTy,
818 target.getFrameInfo().getDynamicAreaOffset(mcInfo,growUp));
819 assert(! growUp && "Has SPARC v9 stack frame convention changed?");
821 // Create a temporary value to hold the result of MUL
822 TmpInstruction* tmpProd = new TmpInstruction(numElementsVal, tsizeVal);
823 MachineCodeForInstruction::get(result).addTemp(tmpProd);
825 // Instruction 1: mul numElements, typeSize -> tmpProd
826 M = new MachineInstr(MULX);
827 M->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister, numElementsVal);
828 M->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister, tsizeVal);
829 M->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister, tmpProd);
830 getMvec.push_back(M);
832 // Instruction 2: sub %sp, tmpProd -> %sp
833 M = new MachineInstr(SUB);
834 M->SetMachineOperandReg(0, target.getRegInfo().getStackPointer());
835 M->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister, tmpProd);
836 M->SetMachineOperandReg(2, target.getRegInfo().getStackPointer());
837 getMvec.push_back(M);
839 // Instruction 3: add %sp, frameSizeBelowDynamicArea -> result
840 M = new MachineInstr(ADD);
841 M->SetMachineOperandReg(0, target.getRegInfo().getStackPointer());
842 M->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister, dynamicAreaOffset);
843 M->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister, result);
844 getMvec.push_back(M);
849 CreateCodeForFixedSizeAlloca(const TargetMachine& target,
852 unsigned int numElements,
853 vector<MachineInstr*>& getMvec)
855 assert(result && result->getParent() &&
856 "Result value is not part of a method?");
857 Method* method = result->getParent()->getParent();
858 MachineCodeForMethod& mcInfo = MachineCodeForMethod::get(method);
860 // Check if the offset would small enough to use as an immediate in load/stores
861 // (check LDX because all load/stores have the same-size immediate field).
862 // If not, put the variable in the dynamically sized area of the frame.
863 unsigned int paddedSizeIgnored;
864 int offsetFromFP = mcInfo.computeOffsetforLocalVar(target, result,
866 tsize * numElements);
867 if (! target.getInstrInfo().constantFitsInImmedField(LDX, offsetFromFP))
869 CreateCodeForVariableSizeAlloca(target, result, tsize,
870 ConstantSInt::get(Type::IntTy,numElements),
875 // else offset fits in immediate field so go ahead and allocate it.
876 offsetFromFP = mcInfo.allocateLocalVar(target, result, tsize * numElements);
878 // Create a temporary Value to hold the constant offset.
879 // This is needed because it may not fit in the immediate field.
880 ConstantSInt* offsetVal = ConstantSInt::get(Type::IntTy, offsetFromFP);
882 // Instruction 1: add %fp, offsetFromFP -> result
883 MachineInstr* M = new MachineInstr(ADD);
884 M->SetMachineOperandReg(0, target.getRegInfo().getFramePointer());
885 M->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister, offsetVal);
886 M->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister, result);
888 getMvec.push_back(M);
893 //------------------------------------------------------------------------
894 // Function SetOperandsForMemInstr
896 // Choose addressing mode for the given load or store instruction.
897 // Use [reg+reg] if it is an indexed reference, and the index offset is
898 // not a constant or if it cannot fit in the offset field.
899 // Use [reg+offset] in all other cases.
901 // This assumes that all array refs are "lowered" to one of these forms:
902 // %x = load (subarray*) ptr, constant ; single constant offset
903 // %x = load (subarray*) ptr, offsetVal ; single non-constant offset
904 // Generally, this should happen via strength reduction + LICM.
905 // Also, strength reduction should take care of using the same register for
906 // the loop index variable and an array index, when that is profitable.
907 //------------------------------------------------------------------------
910 SetOperandsForMemInstr(vector<MachineInstr*>& mvec,
911 vector<MachineInstr*>::iterator mvecI,
912 const InstructionNode* vmInstrNode,
913 const TargetMachine& target)
915 MemAccessInst* memInst = (MemAccessInst*) vmInstrNode->getInstruction();
917 // Variables to hold the index vector, ptr value, and offset value.
918 // The major work here is to extract these for all 3 instruction types
919 // and then call the common function SetMemOperands_Internal().
921 vector<Value*> idxVec;
922 Value* ptrVal = memInst->getPointerOperand();
924 // Test if a GetElemPtr instruction is being folded into this mem instrn.
925 // If so, it will be in the left child for Load and GetElemPtr,
926 // and in the right child for Store instructions.
928 InstrTreeNode* ptrChild = (vmInstrNode->getOpLabel() == Instruction::Store
929 ? vmInstrNode->rightChild()
930 : vmInstrNode->leftChild());
932 // Fold chains of GetElemPtr instructions for structure references.
934 if (isa<StructType>(cast<PointerType>(ptrVal->getType())->getElementType())
935 && (ptrChild->getOpLabel() == Instruction::GetElementPtr ||
936 ptrChild->getOpLabel() == GetElemPtrIdx))
938 Value* newPtr = FoldGetElemChain((InstructionNode*) ptrChild, idxVec);
943 // Append the index vector of this instruction (may be none) to the indexes
944 // folded in previous getElementPtr's (may be none)
945 idxVec.insert(idxVec.end(), memInst->idx_begin(), memInst->idx_end());
947 SetMemOperands_Internal(mvec, mvecI, vmInstrNode, ptrVal, idxVec, target);
951 // Generate the correct operands (and additional instructions if needed)
952 // for the given pointer and given index vector.
955 SetMemOperands_Internal(vector<MachineInstr*>& mvec,
956 vector<MachineInstr*>::iterator mvecI,
957 const InstructionNode* vmInstrNode,
959 vector<Value*>& idxVec,
960 const TargetMachine& target)
962 MemAccessInst* memInst = (MemAccessInst*) vmInstrNode->getInstruction();
964 // Initialize so we default to storing the offset in a register.
965 int64_t smallConstOffset = 0;
966 Value* valueForRegOffset = NULL;
967 MachineOperand::MachineOperandType offsetOpType =MachineOperand::MO_VirtualRegister;
969 // Check if there is an index vector and if so, compute the
970 // right offset for structures and for arrays
972 if (idxVec.size() > 0)
976 const PointerType* ptrType = cast<PointerType>(ptrVal->getType());
978 // Handle special common case of leading [0] index.
979 bool firstIndexIsZero =
980 bool(isa<ConstantUInt>(idxVec.front()) &&
981 cast<ConstantUInt>(idxVec.front())->getValue() == 0);
983 // This is a real structure reference if the ptr target is a
984 // structure type, and the first offset is [0] (eliminate that offset).
985 if (firstIndexIsZero && ptrType->getElementType()->isStructType())
987 // Compute the offset value using the index vector. Create a
988 // virtual reg. for it since it may not fit in the immed field.
989 assert(idxVec.size() >= 2);
990 idxVec.erase(idxVec.begin());
991 unsigned offset = target.DataLayout.getIndexedOffset(ptrType,idxVec);
992 valueForRegOffset = ConstantSInt::get(Type::IntTy, offset);
996 // It is an array ref, and must have been lowered to a single offset.
997 assert((memInst->getNumOperands()
998 == (unsigned) 1 + memInst->getFirstIndexOperandNumber())
999 && "Array refs must be lowered before Instruction Selection");
1001 Value* arrayOffsetVal = * memInst->idx_begin();
1003 // If index is 0, the offset value is just 0. Otherwise,
1004 // generate a MUL instruction to compute address from index.
1005 // The call to getTypeSize() will fail if size is not constant.
1006 // CreateMulInstruction() folds constants intelligently enough.
1008 if (firstIndexIsZero)
1010 offsetOpType = MachineOperand::MO_SignExtendedImmed;
1011 smallConstOffset = 0;
1015 vector<MachineInstr*> mulVec;
1016 Instruction* addr = new TmpInstruction(Type::UIntTy, memInst);
1017 MachineCodeForInstruction::get(memInst).addTemp(addr);
1019 unsigned int eltSize =
1020 target.DataLayout.getTypeSize(ptrType->getElementType());
1021 assert(eltSize > 0 && "Invalid or non-const array element size");
1022 ConstantUInt* eltVal = ConstantUInt::get(Type::UIntTy, eltSize);
1024 CreateMulInstruction(target,
1025 arrayOffsetVal, /* lval, not likely const */
1026 eltVal, /* rval, likely constant */
1028 mulVec, INVALID_MACHINE_OPCODE);
1029 assert(mulVec.size() > 0 && "No multiply instruction created?");
1030 for (vector<MachineInstr*>::const_iterator I = mulVec.begin();
1031 I != mulVec.end(); ++I)
1033 mvecI = mvec.insert(mvecI, *I); // ptr to inserted value
1034 ++mvecI; // ptr to mem. instr.
1037 valueForRegOffset = addr;
1043 offsetOpType = MachineOperand::MO_SignExtendedImmed;
1044 smallConstOffset = 0;
1047 // Operand 0 is value for STORE, ptr for LOAD or GET_ELEMENT_PTR
1048 // It is the left child in the instruction tree in all cases.
1049 Value* leftVal = vmInstrNode->leftChild()->getValue();
1050 (*mvecI)->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister,
1053 // Operand 1 is ptr for STORE, offset for LOAD or GET_ELEMENT_PTR
1054 // Operand 2 is offset for STORE, result reg for LOAD or GET_ELEMENT_PTR
1056 unsigned offsetOpNum = (memInst->getOpcode() == Instruction::Store)? 2 : 1;
1057 if (offsetOpType == MachineOperand::MO_VirtualRegister)
1059 assert(valueForRegOffset != NULL);
1060 (*mvecI)->SetMachineOperandVal(offsetOpNum, offsetOpType,
1064 (*mvecI)->SetMachineOperandConst(offsetOpNum, offsetOpType,
1067 if (memInst->getOpcode() == Instruction::Store)
1068 (*mvecI)->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister,
1071 (*mvecI)->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister,
1072 vmInstrNode->getValue());
1077 // Substitute operand `operandNum' of the instruction in node `treeNode'
1078 // in place of the use(s) of that instruction in node `parent'.
1079 // Check both explicit and implicit operands!
1080 // Also make sure to skip over a parent who:
1081 // (1) is a list node in the Burg tree, or
1082 // (2) itself had its results forwarded to its parent
1085 ForwardOperand(InstructionNode* treeNode,
1086 InstrTreeNode* parent,
1089 assert(treeNode && parent && "Invalid invocation of ForwardOperand");
1091 Instruction* unusedOp = treeNode->getInstruction();
1092 Value* fwdOp = unusedOp->getOperand(operandNum);
1094 // The parent itself may be a list node, so find the real parent instruction
1095 while (parent->getNodeType() != InstrTreeNode::NTInstructionNode)
1097 parent = parent->parent();
1098 assert(parent && "ERROR: Non-instruction node has no parent in tree.");
1100 InstructionNode* parentInstrNode = (InstructionNode*) parent;
1102 Instruction* userInstr = parentInstrNode->getInstruction();
1103 MachineCodeForInstruction &mvec = MachineCodeForInstruction::get(userInstr);
1105 // The parent's mvec would be empty if it was itself forwarded.
1106 // Recursively call ForwardOperand in that case...
1108 if (mvec.size() == 0)
1110 assert(parent->parent() != NULL &&
1111 "Parent could not have been forwarded, yet has no instructions?");
1112 ForwardOperand(treeNode, parent->parent(), operandNum);
1116 bool fwdSuccessful = false;
1117 for (unsigned i=0, N=mvec.size(); i < N; i++)
1119 MachineInstr* minstr = mvec[i];
1120 for (unsigned i=0, numOps=minstr->getNumOperands(); i < numOps; ++i)
1122 const MachineOperand& mop = minstr->getOperand(i);
1123 if (mop.getOperandType() == MachineOperand::MO_VirtualRegister &&
1124 mop.getVRegValue() == unusedOp)
1126 minstr->SetMachineOperandVal(i,
1127 MachineOperand::MO_VirtualRegister, fwdOp);
1128 fwdSuccessful = true;
1132 for (unsigned i=0,numOps=minstr->getNumImplicitRefs(); i<numOps; ++i)
1133 if (minstr->getImplicitRef(i) == unusedOp)
1135 minstr->setImplicitRef(i, fwdOp,
1136 minstr->implicitRefIsDefined(i));
1137 fwdSuccessful = true;
1140 assert(fwdSuccessful && "Value to be forwarded is never used!");
1145 void UltraSparcInstrInfo::
1146 CreateCopyInstructionsByType(const TargetMachine& target,
1150 vector<MachineInstr*>& minstrVec) const
1152 bool loadConstantToReg = false;
1154 const Type* resultType = dest->getType();
1156 MachineOpCode opCode = ChooseAddInstructionByType(resultType);
1157 if (opCode == INVALID_OPCODE)
1159 assert(0 && "Unsupported result type in CreateCopyInstructionsByType()");
1163 // if `src' is a constant that doesn't fit in the immed field or if it is
1164 // a global variable (i.e., a constant address), generate a load
1165 // instruction instead of an add
1167 if (isa<Constant>(src))
1169 unsigned int machineRegNum;
1171 MachineOperand::MachineOperandType opType =
1172 ChooseRegOrImmed(src, opCode, target, /*canUseImmed*/ true,
1173 machineRegNum, immedValue);
1175 if (opType == MachineOperand::MO_VirtualRegister)
1176 loadConstantToReg = true;
1178 else if (isa<GlobalValue>(src))
1179 loadConstantToReg = true;
1181 if (loadConstantToReg)
1182 { // `src' is constant and cannot fit in immed field for the ADD
1183 // Insert instructions to "load" the constant into a register
1184 vector<TmpInstruction*> tempVec;
1185 target.getInstrInfo().CreateCodeToLoadConst(method, src, dest,
1187 for (unsigned i=0; i < tempVec.size(); i++)
1188 MachineCodeForInstruction::get(dest).addTemp(tempVec[i]);
1191 { // Create an add-with-0 instruction of the appropriate type.
1192 // Make `src' the second operand, in case it is a constant
1193 // Use (unsigned long) 0 for a NULL pointer value.
1195 const Type* zeroValueType =
1196 (resultType->getPrimitiveID() == Type::PointerTyID)? Type::ULongTy
1198 MachineInstr* minstr = new MachineInstr(opCode);
1199 minstr->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister,
1200 Constant::getNullConstant(zeroValueType));
1201 minstr->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister, src);
1202 minstr->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister,dest);
1203 minstrVec.push_back(minstr);
1209 //******************* Externally Visible Functions *************************/
1212 //------------------------------------------------------------------------
1213 // External Function: GetInstructionsForProlog
1214 // External Function: GetInstructionsForEpilog
1217 // Create prolog and epilog code for procedure entry and exit
1218 //------------------------------------------------------------------------
1221 GetInstructionsForProlog(BasicBlock* entryBB,
1222 TargetMachine &target,
1223 MachineInstr** mvec)
1226 const MachineFrameInfo& frameInfo = target.getFrameInfo();
1229 // The second operand is the stack size. If it does not fit in the
1230 // immediate field, we have to use a free register to hold the size.
1231 // We will assume that local register `l0' is unused since the SAVE
1232 // instruction must be the first instruction in each procedure.
1234 Method* method = entryBB->getParent();
1235 MachineCodeForMethod& mcInfo = MachineCodeForMethod::get(method);
1236 unsigned int staticStackSize = mcInfo.getStaticStackSize();
1238 if (staticStackSize < (unsigned) frameInfo.getMinStackFrameSize())
1239 staticStackSize = (unsigned) frameInfo.getMinStackFrameSize();
1241 if (unsigned padsz = (staticStackSize %
1242 (unsigned) frameInfo.getStackFrameSizeAlignment()))
1243 staticStackSize += frameInfo.getStackFrameSizeAlignment() - padsz;
1245 if (target.getInstrInfo().constantFitsInImmedField(SAVE, staticStackSize))
1247 M = new MachineInstr(SAVE);
1248 M->SetMachineOperandReg(0, target.getRegInfo().getStackPointer());
1249 M->SetMachineOperandConst(1, MachineOperand::MO_SignExtendedImmed,
1250 - (int) staticStackSize);
1251 M->SetMachineOperandReg(2, target.getRegInfo().getStackPointer());
1256 M = new MachineInstr(SETSW);
1257 M->SetMachineOperandConst(0, MachineOperand::MO_SignExtendedImmed,
1258 - (int) staticStackSize);
1259 M->SetMachineOperandReg(1, MachineOperand::MO_MachineRegister,
1260 target.getRegInfo().getUnifiedRegNum(
1261 target.getRegInfo().getRegClassIDOfType(Type::IntTy),
1262 SparcIntRegOrder::l0));
1265 M = new MachineInstr(SAVE);
1266 M->SetMachineOperandReg(0, target.getRegInfo().getStackPointer());
1267 M->SetMachineOperandReg(1, MachineOperand::MO_MachineRegister,
1268 target.getRegInfo().getUnifiedRegNum(
1269 target.getRegInfo().getRegClassIDOfType(Type::IntTy),
1270 SparcIntRegOrder::l0));
1271 M->SetMachineOperandReg(2, target.getRegInfo().getStackPointer());
1280 GetInstructionsForEpilog(BasicBlock* anExitBB,
1281 TargetMachine &target,
1282 MachineInstr** mvec)
1284 mvec[0] = new MachineInstr(RESTORE);
1285 mvec[0]->SetMachineOperandReg(0, target.getRegInfo().getZeroRegNum());
1286 mvec[0]->SetMachineOperandConst(1, MachineOperand::MO_SignExtendedImmed,
1288 mvec[0]->SetMachineOperandReg(2, target.getRegInfo().getZeroRegNum());
1294 //------------------------------------------------------------------------
1295 // External Function: ThisIsAChainRule
1298 // Check if a given BURG rule is a chain rule.
1299 //------------------------------------------------------------------------
1302 ThisIsAChainRule(int eruleno)
1306 case 111: // stmt: reg
1307 case 113: // stmt: bool
1329 return false; break;
1334 //------------------------------------------------------------------------
1335 // External Function: GetInstructionsByRule
1338 // Choose machine instructions for the SPARC according to the
1339 // patterns chosen by the BURG-generated parser.
1340 //------------------------------------------------------------------------
1343 GetInstructionsByRule(InstructionNode* subtreeRoot,
1346 TargetMachine &target,
1347 vector<MachineInstr*>& mvec)
1349 bool checkCast = false; // initialize here to use fall-through
1351 int forwardOperandNum = -1;
1352 unsigned int allocaSize = 0;
1353 MachineInstr* M, *M2;
1358 // If the code for this instruction was folded into the parent (user),
1360 if (subtreeRoot->isFoldedIntoParent())
1364 // Let's check for chain rules outside the switch so that we don't have
1365 // to duplicate the list of chain rule production numbers here again
1367 if (ThisIsAChainRule(ruleForNode))
1369 // Chain rules have a single nonterminal on the RHS.
1370 // Get the rule that matches the RHS non-terminal and use that instead.
1372 assert(nts[0] && ! nts[1]
1373 && "A chain rule should have only one RHS non-terminal!");
1374 nextRule = burm_rule(subtreeRoot->state, nts[0]);
1375 nts = burm_nts[nextRule];
1376 GetInstructionsByRule(subtreeRoot, nextRule, nts, target, mvec);
1380 switch(ruleForNode) {
1381 case 1: // stmt: Ret
1382 case 2: // stmt: RetValue(reg)
1383 { // NOTE: Prepass of register allocation is responsible
1384 // for moving return value to appropriate register.
1385 // Mark the return-address register as a hidden virtual reg.
1386 // Mark the return value register as an implicit ref of
1387 // the machine instruction.
1388 // Finally put a NOP in the delay slot.
1389 ReturnInst *returnInstr =
1390 cast<ReturnInst>(subtreeRoot->getInstruction());
1391 assert(returnInstr->getOpcode() == Instruction::Ret);
1393 Instruction* returnReg = new TmpInstruction(returnInstr);
1394 MachineCodeForInstruction::get(returnInstr).addTemp(returnReg);
1396 M = new MachineInstr(JMPLRET);
1397 M->SetMachineOperandReg(0, MachineOperand::MO_VirtualRegister,
1399 M->SetMachineOperandConst(1,MachineOperand::MO_SignExtendedImmed,
1401 M->SetMachineOperandReg(2, target.getRegInfo().getZeroRegNum());
1403 if (returnInstr->getReturnValue() != NULL)
1404 M->addImplicitRef(returnInstr->getReturnValue());
1407 mvec.push_back(new MachineInstr(NOP));
1412 case 3: // stmt: Store(reg,reg)
1413 case 4: // stmt: Store(reg,ptrreg)
1414 mvec.push_back(new MachineInstr(
1415 ChooseStoreInstruction(
1416 subtreeRoot->leftChild()->getValue()->getType())));
1417 SetOperandsForMemInstr(mvec, mvec.end()-1, subtreeRoot, target);
1420 case 5: // stmt: BrUncond
1421 M = new MachineInstr(BA);
1422 M->SetMachineOperandVal(0, MachineOperand::MO_CCRegister,
1424 M->SetMachineOperandVal(1, MachineOperand::MO_PCRelativeDisp,
1425 cast<BranchInst>(subtreeRoot->getInstruction())->getSuccessor(0));
1429 mvec.push_back(new MachineInstr(NOP));
1432 case 206: // stmt: BrCond(setCCconst)
1433 { // setCCconst => boolean was computed with `%b = setCC type reg1 const'
1434 // If the constant is ZERO, we can use the branch-on-integer-register
1435 // instructions and avoid the SUBcc instruction entirely.
1436 // Otherwise this is just the same as case 5, so just fall through.
1438 InstrTreeNode* constNode = subtreeRoot->leftChild()->rightChild();
1440 constNode->getNodeType() ==InstrTreeNode::NTConstNode);
1441 Constant *constVal = cast<Constant>(constNode->getValue());
1444 if ((constVal->getType()->isIntegral()
1445 || constVal->getType()->isPointerType())
1446 && GetConstantValueAsSignedInt(constVal, isValidConst) == 0
1449 // That constant is a zero after all...
1450 // Use the left child of setCC as the first argument!
1451 // Mark the setCC node so that no code is generated for it.
1452 InstructionNode* setCCNode = (InstructionNode*)
1453 subtreeRoot->leftChild();
1454 assert(setCCNode->getOpLabel() == SetCCOp);
1455 setCCNode->markFoldedIntoParent();
1457 BranchInst* brInst=cast<BranchInst>(subtreeRoot->getInstruction());
1459 M = new MachineInstr(ChooseBprInstruction(subtreeRoot));
1460 M->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister,
1461 setCCNode->leftChild()->getValue());
1462 M->SetMachineOperandVal(1, MachineOperand::MO_PCRelativeDisp,
1463 brInst->getSuccessor(0));
1467 mvec.push_back(new MachineInstr(NOP));
1470 M = new MachineInstr(BA);
1471 M->SetMachineOperandVal(0, MachineOperand::MO_CCRegister,
1473 M->SetMachineOperandVal(1, MachineOperand::MO_PCRelativeDisp,
1474 brInst->getSuccessor(1));
1478 mvec.push_back(new MachineInstr(NOP));
1482 // ELSE FALL THROUGH
1485 case 6: // stmt: BrCond(bool)
1486 { // bool => boolean was computed with some boolean operator
1487 // (SetCC, Not, ...). We need to check whether the type was a FP,
1488 // signed int or unsigned int, and check the branching condition in
1489 // order to choose the branch to use.
1490 // If it is an integer CC, we also need to find the unique
1491 // TmpInstruction representing that CC.
1493 BranchInst* brInst = cast<BranchInst>(subtreeRoot->getInstruction());
1495 M = new MachineInstr(ChooseBccInstruction(subtreeRoot, isFPBranch));
1497 Value* ccValue = GetTmpForCC(subtreeRoot->leftChild()->getValue(),
1498 brInst->getParent()->getParent(),
1499 isFPBranch? Type::FloatTy : Type::IntTy);
1501 M->SetMachineOperandVal(0, MachineOperand::MO_CCRegister, ccValue);
1502 M->SetMachineOperandVal(1, MachineOperand::MO_PCRelativeDisp,
1503 brInst->getSuccessor(0));
1507 mvec.push_back(new MachineInstr(NOP));
1510 M = new MachineInstr(BA);
1511 M->SetMachineOperandVal(0, MachineOperand::MO_CCRegister,
1513 M->SetMachineOperandVal(1, MachineOperand::MO_PCRelativeDisp,
1514 brInst->getSuccessor(1));
1518 mvec.push_back(new MachineInstr(NOP));
1522 case 208: // stmt: BrCond(boolconst)
1524 // boolconst => boolean is a constant; use BA to first or second label
1525 Constant* constVal =
1526 cast<Constant>(subtreeRoot->leftChild()->getValue());
1527 unsigned dest = cast<ConstantBool>(constVal)->getValue()? 0 : 1;
1529 M = new MachineInstr(BA);
1530 M->SetMachineOperandVal(0, MachineOperand::MO_CCRegister,
1532 M->SetMachineOperandVal(1, MachineOperand::MO_PCRelativeDisp,
1533 ((BranchInst*) subtreeRoot->getInstruction())->getSuccessor(dest));
1537 mvec.push_back(new MachineInstr(NOP));
1541 case 8: // stmt: BrCond(boolreg)
1542 { // boolreg => boolean is stored in an existing register.
1543 // Just use the branch-on-integer-register instruction!
1545 M = new MachineInstr(BRNZ);
1546 M->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister,
1547 subtreeRoot->leftChild()->getValue());
1548 M->SetMachineOperandVal(1, MachineOperand::MO_PCRelativeDisp,
1549 ((BranchInst*) subtreeRoot->getInstruction())->getSuccessor(0));
1553 mvec.push_back(new MachineInstr(NOP));
1556 M = new MachineInstr(BA);
1557 M->SetMachineOperandVal(0, MachineOperand::MO_CCRegister,
1559 M->SetMachineOperandVal(1, MachineOperand::MO_PCRelativeDisp,
1560 ((BranchInst*) subtreeRoot->getInstruction())->getSuccessor(1));
1564 mvec.push_back(new MachineInstr(NOP));
1568 case 9: // stmt: Switch(reg)
1569 assert(0 && "*** SWITCH instruction is not implemented yet.");
1572 case 10: // reg: VRegList(reg, reg)
1573 assert(0 && "VRegList should never be the topmost non-chain rule");
1576 case 21: // bool: Not(bool): Both these are implemented as:
1577 case 321: // reg: BNot(reg) : reg = reg XOR-NOT 0
1578 M = new MachineInstr(XNOR);
1579 M->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister,
1580 subtreeRoot->leftChild()->getValue());
1581 M->SetMachineOperandReg(1, target.getRegInfo().getZeroRegNum());
1582 M->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister,
1583 subtreeRoot->getValue());
1587 case 322: // reg: ToBoolTy(bool):
1588 case 22: // reg: ToBoolTy(reg):
1590 const Type* opType = subtreeRoot->leftChild()->getValue()->getType();
1591 assert(opType->isIntegral() || opType->isPointerType()
1592 || opType == Type::BoolTy);
1593 forwardOperandNum = 0; // forward first operand to user
1597 case 23: // reg: ToUByteTy(reg)
1598 case 25: // reg: ToUShortTy(reg)
1599 case 27: // reg: ToUIntTy(reg)
1600 case 29: // reg: ToULongTy(reg)
1602 const Type* opType = subtreeRoot->leftChild()->getValue()->getType();
1603 assert(opType->isIntegral() ||
1604 opType->isPointerType() ||
1605 opType == Type::BoolTy && "Cast is illegal for other types");
1606 forwardOperandNum = 0; // forward first operand to user
1610 case 24: // reg: ToSByteTy(reg)
1611 case 26: // reg: ToShortTy(reg)
1612 case 28: // reg: ToIntTy(reg)
1613 case 30: // reg: ToLongTy(reg)
1615 const Type* opType = subtreeRoot->leftChild()->getValue()->getType();
1616 if (opType->isIntegral()
1617 || opType->isPointerType()
1618 || opType == Type::BoolTy)
1620 forwardOperandNum = 0; // forward first operand to user
1624 // If the source operand is an FP type, the int result must be
1625 // copied from float to int register via memory!
1626 Instruction *dest = subtreeRoot->getInstruction();
1627 Value* leftVal = subtreeRoot->leftChild()->getValue();
1629 vector<MachineInstr*> minstrVec;
1631 if (opType == Type::FloatTy || opType == Type::DoubleTy)
1633 // Create a temporary to represent the INT register
1634 // into which the FP value will be copied via memory.
1635 // The type of this temporary will determine the FP
1636 // register used: single-prec for a 32-bit int or smaller,
1637 // double-prec for a 64-bit int.
1639 const Type* destTypeToUse =
1640 (dest->getType() == Type::LongTy)? Type::DoubleTy
1642 destForCast = new TmpInstruction(destTypeToUse, leftVal);
1643 MachineCodeForInstruction &MCFI =
1644 MachineCodeForInstruction::get(dest);
1645 MCFI.addTemp(destForCast);
1647 vector<TmpInstruction*> tempVec;
1648 target.getInstrInfo().CreateCodeToCopyFloatToInt(
1649 dest->getParent()->getParent(),
1650 (TmpInstruction*) destForCast, dest,
1651 minstrVec, tempVec, target);
1653 for (unsigned i=0; i < tempVec.size(); ++i)
1654 MCFI.addTemp(tempVec[i]);
1657 destForCast = leftVal;
1659 MachineOpCode opCode=ChooseConvertToIntInstr(subtreeRoot, opType);
1660 assert(opCode != INVALID_OPCODE && "Expected to need conversion!");
1662 M = new MachineInstr(opCode);
1663 M->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister,
1665 M->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister,
1669 // Append the copy code, if any, after the conversion instr.
1670 mvec.insert(mvec.end(), minstrVec.begin(), minstrVec.end());
1675 case 31: // reg: ToFloatTy(reg):
1676 case 32: // reg: ToDoubleTy(reg):
1677 case 232: // reg: ToDoubleTy(Constant):
1679 // If this instruction has a parent (a user) in the tree
1680 // and the user is translated as an FsMULd instruction,
1681 // then the cast is unnecessary. So check that first.
1682 // In the future, we'll want to do the same for the FdMULq instruction,
1683 // so do the check here instead of only for ToFloatTy(reg).
1685 if (subtreeRoot->parent() != NULL &&
1686 MachineCodeForInstruction::get(((InstructionNode*)subtreeRoot->parent())->getInstruction())[0]->getOpCode() == FSMULD)
1688 forwardOperandNum = 0; // forward first operand to user
1692 Value* leftVal = subtreeRoot->leftChild()->getValue();
1693 const Type* opType = leftVal->getType();
1694 MachineOpCode opCode=ChooseConvertToFloatInstr(subtreeRoot,opType);
1695 if (opCode == INVALID_OPCODE) // no conversion needed
1697 forwardOperandNum = 0; // forward first operand to user
1701 // If the source operand is a non-FP type it must be
1702 // first copied from int to float register via memory!
1703 Instruction *dest = subtreeRoot->getInstruction();
1706 if (opType != Type::FloatTy && opType != Type::DoubleTy)
1708 // Create a temporary to represent the FP register
1709 // into which the integer will be copied via memory.
1710 // The type of this temporary will determine the FP
1711 // register used: single-prec for a 32-bit int or smaller,
1712 // double-prec for a 64-bit int.
1714 const Type* srcTypeToUse =
1715 (leftVal->getType() == Type::LongTy)? Type::DoubleTy
1718 srcForCast = new TmpInstruction(srcTypeToUse, dest);
1719 MachineCodeForInstruction &DestMCFI =
1720 MachineCodeForInstruction::get(dest);
1721 DestMCFI.addTemp(srcForCast);
1723 vector<MachineInstr*> minstrVec;
1724 vector<TmpInstruction*> tempVec;
1725 target.getInstrInfo().CreateCodeToCopyIntToFloat(
1726 dest->getParent()->getParent(),
1727 leftVal, (TmpInstruction*) srcForCast,
1728 minstrVec, tempVec, target);
1730 mvec.insert(mvec.end(), minstrVec.begin(),minstrVec.end());
1732 for (unsigned i=0; i < tempVec.size(); ++i)
1733 DestMCFI.addTemp(tempVec[i]);
1736 srcForCast = leftVal;
1738 M = new MachineInstr(opCode);
1739 M->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister,
1741 M->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister,
1748 case 19: // reg: ToArrayTy(reg):
1749 case 20: // reg: ToPointerTy(reg):
1750 forwardOperandNum = 0; // forward first operand to user
1753 case 233: // reg: Add(reg, Constant)
1754 M = CreateAddConstInstruction(subtreeRoot);
1760 // ELSE FALL THROUGH
1762 case 33: // reg: Add(reg, reg)
1763 mvec.push_back(new MachineInstr(ChooseAddInstruction(subtreeRoot)));
1764 Set3OperandsFromInstr(mvec.back(), subtreeRoot, target);
1767 case 234: // reg: Sub(reg, Constant)
1768 M = CreateSubConstInstruction(subtreeRoot);
1774 // ELSE FALL THROUGH
1776 case 34: // reg: Sub(reg, reg)
1777 mvec.push_back(new MachineInstr(ChooseSubInstructionByType(
1778 subtreeRoot->getInstruction()->getType())));
1779 Set3OperandsFromInstr(mvec.back(), subtreeRoot, target);
1782 case 135: // reg: Mul(todouble, todouble)
1786 case 35: // reg: Mul(reg, reg)
1788 MachineOpCode forceOp = ((checkCast && BothFloatToDouble(subtreeRoot))
1790 : INVALID_MACHINE_OPCODE);
1791 CreateMulInstruction(target,
1792 subtreeRoot->leftChild()->getValue(),
1793 subtreeRoot->rightChild()->getValue(),
1794 subtreeRoot->getInstruction(),
1798 case 335: // reg: Mul(todouble, todoubleConst)
1802 case 235: // reg: Mul(reg, Constant)
1804 MachineOpCode forceOp = ((checkCast && BothFloatToDouble(subtreeRoot))
1806 : INVALID_MACHINE_OPCODE);
1807 CreateMulInstruction(target,
1808 subtreeRoot->leftChild()->getValue(),
1809 subtreeRoot->rightChild()->getValue(),
1810 subtreeRoot->getInstruction(),
1814 case 236: // reg: Div(reg, Constant)
1816 CreateDivConstInstruction(target, subtreeRoot, mvec);
1817 if (mvec.size() > L)
1819 // ELSE FALL THROUGH
1821 case 36: // reg: Div(reg, reg)
1822 mvec.push_back(new MachineInstr(ChooseDivInstruction(target, subtreeRoot)));
1823 Set3OperandsFromInstr(mvec.back(), subtreeRoot, target);
1826 case 37: // reg: Rem(reg, reg)
1827 case 237: // reg: Rem(reg, Constant)
1829 Instruction* remInstr = subtreeRoot->getInstruction();
1831 TmpInstruction* quot = new TmpInstruction(
1832 subtreeRoot->leftChild()->getValue(),
1833 subtreeRoot->rightChild()->getValue());
1834 TmpInstruction* prod = new TmpInstruction(
1836 subtreeRoot->rightChild()->getValue());
1837 MachineCodeForInstruction::get(remInstr).addTemp(quot).addTemp(prod);
1839 M = new MachineInstr(ChooseDivInstruction(target, subtreeRoot));
1840 Set3OperandsFromInstr(M, subtreeRoot, target);
1841 M->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister,quot);
1844 M = new MachineInstr(ChooseMulInstructionByType(
1845 subtreeRoot->getInstruction()->getType()));
1846 M->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister,quot);
1847 M->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister,
1848 subtreeRoot->rightChild()->getValue());
1849 M->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister,prod);
1852 M = new MachineInstr(ChooseSubInstructionByType(
1853 subtreeRoot->getInstruction()->getType()));
1854 Set3OperandsFromInstr(M, subtreeRoot, target);
1855 M->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister,prod);
1861 case 38: // bool: And(bool, bool)
1862 case 238: // bool: And(bool, boolconst)
1863 case 338: // reg : BAnd(reg, reg)
1864 case 538: // reg : BAnd(reg, Constant)
1865 mvec.push_back(new MachineInstr(AND));
1866 Set3OperandsFromInstr(mvec.back(), subtreeRoot, target);
1869 case 138: // bool: And(bool, not)
1870 case 438: // bool: BAnd(bool, not)
1871 mvec.push_back(new MachineInstr(ANDN));
1872 Set3OperandsFromInstr(mvec.back(), subtreeRoot, target);
1875 case 39: // bool: Or(bool, bool)
1876 case 239: // bool: Or(bool, boolconst)
1877 case 339: // reg : BOr(reg, reg)
1878 case 539: // reg : BOr(reg, Constant)
1879 mvec.push_back(new MachineInstr(ORN));
1880 Set3OperandsFromInstr(mvec.back(), subtreeRoot, target);
1883 case 139: // bool: Or(bool, not)
1884 case 439: // bool: BOr(bool, not)
1885 mvec.push_back(new MachineInstr(ORN));
1886 Set3OperandsFromInstr(mvec.back(), subtreeRoot, target);
1889 case 40: // bool: Xor(bool, bool)
1890 case 240: // bool: Xor(bool, boolconst)
1891 case 340: // reg : BXor(reg, reg)
1892 case 540: // reg : BXor(reg, Constant)
1893 mvec.push_back(new MachineInstr(XOR));
1894 Set3OperandsFromInstr(mvec.back(), subtreeRoot, target);
1897 case 140: // bool: Xor(bool, not)
1898 case 440: // bool: BXor(bool, not)
1899 mvec.push_back(new MachineInstr(XNOR));
1900 Set3OperandsFromInstr(mvec.back(), subtreeRoot, target);
1903 case 41: // boolconst: SetCC(reg, Constant)
1905 // If the SetCC was folded into the user (parent), it will be
1906 // caught above. All other cases are the same as case 42,
1907 // so just fall through.
1909 case 42: // bool: SetCC(reg, reg):
1911 // This generates a SUBCC instruction, putting the difference in
1912 // a result register, and setting a condition code.
1914 // If the boolean result of the SetCC is used by anything other
1915 // than a single branch instruction, the boolean must be
1916 // computed and stored in the result register. Otherwise, discard
1917 // the difference (by using %g0) and keep only the condition code.
1919 // To compute the boolean result in a register we use a conditional
1920 // move, unless the result of the SUBCC instruction can be used as
1921 // the bool! This assumes that zero is FALSE and any non-zero
1924 InstructionNode* parentNode = (InstructionNode*) subtreeRoot->parent();
1925 Instruction* setCCInstr = subtreeRoot->getInstruction();
1926 bool keepBoolVal = (parentNode == NULL ||
1927 parentNode->getInstruction()->getOpcode()
1928 != Instruction::Br);
1929 bool subValIsBoolVal = setCCInstr->getOpcode() == Instruction::SetNE;
1930 bool keepSubVal = keepBoolVal && subValIsBoolVal;
1931 bool computeBoolVal = keepBoolVal && ! subValIsBoolVal;
1935 MachineOpCode movOpCode = 0;
1937 // Mark the 4th operand as being a CC register, and as a def
1938 // A TmpInstruction is created to represent the CC "result".
1939 // Unlike other instances of TmpInstruction, this one is used
1940 // by machine code of multiple LLVM instructions, viz.,
1941 // the SetCC and the branch. Make sure to get the same one!
1942 // Note that we do this even for FP CC registers even though they
1943 // are explicit operands, because the type of the operand
1944 // needs to be a floating point condition code, not an integer
1945 // condition code. Think of this as casting the bool result to
1946 // a FP condition code register.
1948 Value* leftVal = subtreeRoot->leftChild()->getValue();
1949 bool isFPCompare = (leftVal->getType() == Type::FloatTy ||
1950 leftVal->getType() == Type::DoubleTy);
1952 TmpInstruction* tmpForCC = GetTmpForCC(setCCInstr,
1953 setCCInstr->getParent()->getParent(),
1954 isFPCompare? Type::FloatTy : Type::IntTy);
1955 MachineCodeForInstruction::get(setCCInstr).addTemp(tmpForCC);
1959 // Integer condition: dest. should be %g0 or an integer register.
1960 // If result must be saved but condition is not SetEQ then we need
1961 // a separate instruction to compute the bool result, so discard
1962 // result of SUBcc instruction anyway.
1964 M = new MachineInstr(SUBcc);
1965 Set3OperandsFromInstr(M, subtreeRoot, target, ! keepSubVal);
1966 M->SetMachineOperandVal(3, MachineOperand::MO_CCRegister,
1967 tmpForCC, /*def*/true);
1971 { // recompute bool using the integer condition codes
1973 ChooseMovpccAfterSub(subtreeRoot,mustClearReg,valueToMove);
1978 // FP condition: dest of FCMP should be some FCCn register
1979 M = new MachineInstr(ChooseFcmpInstruction(subtreeRoot));
1980 M->SetMachineOperandVal(0, MachineOperand::MO_CCRegister,
1982 M->SetMachineOperandVal(1,MachineOperand::MO_VirtualRegister,
1983 subtreeRoot->leftChild()->getValue());
1984 M->SetMachineOperandVal(2,MachineOperand::MO_VirtualRegister,
1985 subtreeRoot->rightChild()->getValue());
1989 {// recompute bool using the FP condition codes
1990 mustClearReg = true;
1992 movOpCode = ChooseMovFpccInstruction(subtreeRoot);
1999 {// Unconditionally set register to 0
2000 M = new MachineInstr(SETHI);
2001 M->SetMachineOperandConst(0,MachineOperand::MO_UnextendedImmed,
2003 M->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister,
2008 // Now conditionally move `valueToMove' (0 or 1) into the register
2009 M = new MachineInstr(movOpCode);
2010 M->SetMachineOperandVal(0, MachineOperand::MO_CCRegister,
2012 M->SetMachineOperandConst(1, MachineOperand::MO_UnextendedImmed,
2014 M->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister,
2021 case 43: // boolreg: VReg
2022 case 44: // boolreg: Constant
2025 case 51: // reg: Load(reg)
2026 case 52: // reg: Load(ptrreg)
2027 case 53: // reg: LoadIdx(reg,reg)
2028 case 54: // reg: LoadIdx(ptrreg,reg)
2029 mvec.push_back(new MachineInstr(ChooseLoadInstruction(
2030 subtreeRoot->getValue()->getType())));
2031 SetOperandsForMemInstr(mvec, mvec.end()-1, subtreeRoot, target);
2034 case 55: // reg: GetElemPtr(reg)
2035 case 56: // reg: GetElemPtrIdx(reg,reg)
2036 // If the GetElemPtr was folded into the user (parent), it will be
2037 // caught above. For other cases, we have to compute the address.
2038 mvec.push_back(new MachineInstr(ADD));
2039 SetOperandsForMemInstr(mvec, mvec.end()-1, subtreeRoot, target);
2042 case 57: // reg: Alloca: Implement as 1 instruction:
2043 { // add %fp, offsetFromFP -> result
2044 AllocationInst* instr =
2045 cast<AllocationInst>(subtreeRoot->getInstruction());
2046 unsigned int tsize =
2047 target.findOptimalStorageSize(instr->getAllocatedType());
2049 CreateCodeForFixedSizeAlloca(target, instr, tsize, 1, mvec);
2053 case 58: // reg: Alloca(reg): Implement as 3 instructions:
2054 // mul num, typeSz -> tmp
2055 // sub %sp, tmp -> %sp
2056 { // add %sp, frameSizeBelowDynamicArea -> result
2057 AllocationInst* instr =
2058 cast<AllocationInst>(subtreeRoot->getInstruction());
2059 const Type* eltType = instr->getAllocatedType();
2061 // If #elements is constant, use simpler code for fixed-size allocas
2062 int tsize = (int) target.findOptimalStorageSize(eltType);
2063 Value* numElementsVal = NULL;
2064 bool isArray = instr->isArrayAllocation();
2067 isa<Constant>(numElementsVal = instr->getArraySize()))
2068 { // total size is constant: generate code for fixed-size alloca
2069 unsigned int numElements = isArray?
2070 cast<ConstantUInt>(numElementsVal)->getValue() : 1;
2071 CreateCodeForFixedSizeAlloca(target, instr, tsize,
2074 else // total size is not constant.
2075 CreateCodeForVariableSizeAlloca(target, instr, tsize,
2076 numElementsVal, mvec);
2080 case 61: // reg: Call
2081 { // Generate a call-indirect (i.e., jmpl) for now to expose
2082 // the potential need for registers. If an absolute address
2083 // is available, replace this with a CALL instruction.
2084 // Mark both the indirection register and the return-address
2085 // register as hidden virtual registers.
2086 // Also, mark the operands of the Call and return value (if
2087 // any) as implicit operands of the CALL machine instruction.
2089 CallInst *callInstr = cast<CallInst>(subtreeRoot->getInstruction());
2090 Value *callee = callInstr->getCalledValue();
2092 Instruction* retAddrReg = new TmpInstruction(callInstr);
2094 // Note temporary values in the machineInstrVec for the VM instr.
2096 // WARNING: Operands 0..N-1 must go in slots 0..N-1 of implicitUses.
2097 // The result value must go in slot N. This is assumed
2098 // in register allocation.
2100 MachineCodeForInstruction::get(callInstr).addTemp(retAddrReg);
2103 // Generate the machine instruction and its operands.
2104 // Use CALL for direct function calls; this optimistically assumes
2105 // the PC-relative address fits in the CALL address field (22 bits).
2106 // Use JMPL for indirect calls.
2108 if (callee->getValueType() == Value::MethodVal)
2109 { // direct function call
2110 M = new MachineInstr(CALL);
2111 M->SetMachineOperandVal(0, MachineOperand::MO_PCRelativeDisp,
2115 { // indirect function call
2116 M = new MachineInstr(JMPLCALL);
2117 M->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister,
2119 M->SetMachineOperandConst(1, MachineOperand::MO_SignExtendedImmed,
2121 M->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister,
2127 // Add the call operands and return value as implicit refs
2128 for (unsigned i=0, N=callInstr->getNumOperands(); i < N; ++i)
2129 if (callInstr->getOperand(i) != callee)
2130 mvec.back()->addImplicitRef(callInstr->getOperand(i));
2132 if (callInstr->getType() != Type::VoidTy)
2133 mvec.back()->addImplicitRef(callInstr, /*isDef*/ true);
2135 // For the CALL instruction, the ret. addr. reg. is also implicit
2136 if (callee->getValueType() == Value::MethodVal)
2137 mvec.back()->addImplicitRef(retAddrReg, /*isDef*/ true);
2140 mvec.push_back(new MachineInstr(NOP));
2144 case 62: // reg: Shl(reg, reg)
2145 { const Type* opType = subtreeRoot->leftChild()->getValue()->getType();
2146 assert(opType->isIntegral()
2147 || opType == Type::BoolTy
2148 || opType->isPointerType()&& "Shl unsupported for other types");
2149 mvec.push_back(new MachineInstr((opType == Type::LongTy)? SLLX : SLL));
2150 Set3OperandsFromInstr(mvec.back(), subtreeRoot, target);
2154 case 63: // reg: Shr(reg, reg)
2155 { const Type* opType = subtreeRoot->leftChild()->getValue()->getType();
2156 assert(opType->isIntegral()
2157 || opType == Type::BoolTy
2158 || opType->isPointerType() &&"Shr unsupported for other types");
2159 mvec.push_back(new MachineInstr((opType->isSigned()
2160 ? ((opType == Type::LongTy)? SRAX : SRA)
2161 : ((opType == Type::LongTy)? SRLX : SRL))));
2162 Set3OperandsFromInstr(mvec.back(), subtreeRoot, target);
2166 case 64: // reg: Phi(reg,reg)
2167 break; // don't forward the value
2169 #undef NEED_PHI_MACHINE_INSTRS
2170 #ifdef NEED_PHI_MACHINE_INSTRS
2171 { // This instruction has variable #operands, so resultPos is 0.
2172 Instruction* phi = subtreeRoot->getInstruction();
2173 M = new MachineInstr(PHI, 1 + phi->getNumOperands());
2174 M->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister,
2175 subtreeRoot->getValue());
2176 for (unsigned i=0, N=phi->getNumOperands(); i < N; i++)
2177 M->SetMachineOperandVal(i+1, MachineOperand::MO_VirtualRegister,
2178 phi->getOperand(i));
2182 #endif // NEED_PHI_MACHINE_INSTRS
2185 case 71: // reg: VReg
2186 case 72: // reg: Constant
2187 break; // don't forward the value
2190 assert(0 && "Unrecognized BURG rule");
2195 if (forwardOperandNum >= 0)
2196 { // We did not generate a machine instruction but need to use operand.
2197 // If user is in the same tree, replace Value in its machine operand.
2198 // If not, insert a copy instruction which should get coalesced away
2199 // by register allocation.
2200 if (subtreeRoot->parent() != NULL)
2201 ForwardOperand(subtreeRoot, subtreeRoot->parent(), forwardOperandNum);
2204 vector<MachineInstr*> minstrVec;
2205 target.getInstrInfo().CreateCopyInstructionsByType(target,
2206 subtreeRoot->getInstruction()->getParent()->getParent(),
2207 subtreeRoot->getInstruction()->getOperand(forwardOperandNum),
2208 subtreeRoot->getInstruction(), minstrVec);
2209 assert(minstrVec.size() > 0);
2210 mvec.insert(mvec.end(), minstrVec.begin(), minstrVec.end());