1 //***************************************************************************
6 // This file defines stuff that is to be private to the Sparc
7 // backend, but is shared among different portions of the backend.
8 //**************************************************************************/
11 #ifndef SPARC_INTERNALS_H
12 #define SPARC_INTERNALS_H
14 #include "llvm/Target/TargetMachine.h"
15 #include "llvm/Target/MachineSchedInfo.h"
16 #include "llvm/Target/MachineFrameInfo.h"
17 #include "llvm/Target/MachineCacheInfo.h"
18 #include "llvm/Target/MachineRegInfo.h"
19 #include "llvm/Type.h"
20 #include <sys/types.h>
27 Pass *createPrologEpilogCodeInserter(TargetMachine &TM);
29 // OpCodeMask definitions for the Sparc V9
31 const OpCodeMask Immed = 0x00002000; // immed or reg operand?
32 const OpCodeMask Annul = 0x20000000; // annul delay instr?
33 const OpCodeMask PredictTaken = 0x00080000; // predict branch taken?
36 enum SparcInstrSchedClass {
37 SPARC_NONE, /* Instructions with no scheduling restrictions */
38 SPARC_IEUN, /* Integer class that can use IEU0 or IEU1 */
39 SPARC_IEU0, /* Integer class IEU0 */
40 SPARC_IEU1, /* Integer class IEU1 */
41 SPARC_FPM, /* FP Multiply or Divide instructions */
42 SPARC_FPA, /* All other FP instructions */
43 SPARC_CTI, /* Control-transfer instructions */
44 SPARC_LD, /* Load instructions */
45 SPARC_ST, /* Store instructions */
46 SPARC_SINGLE, /* Instructions that must issue by themselves */
48 SPARC_INV, /* This should stay at the end for the next value */
49 SPARC_NUM_SCHED_CLASSES = SPARC_INV
53 //---------------------------------------------------------------------------
54 // enum SparcMachineOpCode.
55 // const MachineInstrDescriptor SparcMachineInstrDesc[]
58 // Description of UltraSparc machine instructions.
60 //---------------------------------------------------------------------------
62 enum SparcMachineOpCode {
63 #define I(ENUM, OPCODESTRING, NUMOPERANDS, RESULTPOS, MAXIMM, IMMSE, \
64 NUMDELAYSLOTS, LATENCY, SCHEDCLASS, INSTFLAGS) \
66 #include "SparcInstr.def"
68 // End-of-array marker
70 NUM_REAL_OPCODES = PHI, // number of valid opcodes
71 NUM_TOTAL_OPCODES = INVALID_OPCODE
75 // Array of machine instruction descriptions...
76 extern const MachineInstrDescriptor SparcMachineInstrDesc[];
79 //---------------------------------------------------------------------------
80 // class UltraSparcInstrInfo
83 // Information about individual instructions.
84 // Most information is stored in the SparcMachineInstrDesc array above.
85 // Other information is computed on demand, and most such functions
86 // default to member functions in base class MachineInstrInfo.
87 //---------------------------------------------------------------------------
89 class UltraSparcInstrInfo : public MachineInstrInfo {
91 /*ctor*/ UltraSparcInstrInfo(const TargetMachine& tgt);
94 // All immediate constants are in position 1 except the
95 // store instructions.
97 virtual int getImmedConstantPos(MachineOpCode opCode) const {
99 if (this->maxImmedConstant(opCode, ignore) != 0)
101 assert(! this->isStore((MachineOpCode) STB - 1)); // first store is STB
102 assert(! this->isStore((MachineOpCode) STD + 1)); // last store is STD
103 return (opCode >= STB && opCode <= STD)? 2 : 1;
109 virtual bool hasResultInterlock (MachineOpCode opCode) const
111 // All UltraSPARC instructions have interlocks (note that delay slots
112 // are not considered here).
113 // However, instructions that use the result of an FCMP produce a
114 // 9-cycle stall if they are issued less than 3 cycles after the FCMP.
115 // Force the compiler to insert a software interlock (i.e., gap of
116 // 2 other groups, including NOPs if necessary).
117 return (opCode == FCMPS || opCode == FCMPD || opCode == FCMPQ);
120 //-------------------------------------------------------------------------
121 // Code generation support for creating individual machine instructions
122 //-------------------------------------------------------------------------
124 // Create an instruction sequence to put the constant `val' into
125 // the virtual register `dest'. `val' may be a Constant or a
126 // GlobalValue, viz., the constant address of a global variable or function.
127 // The generated instructions are returned in `mvec'.
128 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
129 // Any stack space required is allocated via mcff.
131 virtual void CreateCodeToLoadConst(const TargetMachine& target,
135 std::vector<MachineInstr*>& mvec,
136 MachineCodeForInstruction& mcfi) const;
138 // Create an instruction sequence to copy an integer value `val'
139 // to a floating point value `dest' by copying to memory and back.
140 // val must be an integral type. dest must be a Float or Double.
141 // The generated instructions are returned in `mvec'.
142 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
143 // Any stack space required is allocated via mcff.
145 virtual void CreateCodeToCopyIntToFloat(const TargetMachine& target,
149 std::vector<MachineInstr*>& mvec,
150 MachineCodeForInstruction& mcfi) const;
152 // Similarly, create an instruction sequence to copy an FP value
153 // `val' to an integer value `dest' by copying to memory and back.
154 // The generated instructions are returned in `mvec'.
155 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
156 // Any stack space required is allocated via mcff.
158 virtual void CreateCodeToCopyFloatToInt(const TargetMachine& target,
162 std::vector<MachineInstr*>& mvec,
163 MachineCodeForInstruction& mcfi) const;
165 // Create instruction(s) to copy src to dest, for arbitrary types
166 // The generated instructions are returned in `mvec'.
167 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
168 // Any stack space required is allocated via mcff.
170 virtual void CreateCopyInstructionsByType(const TargetMachine& target,
174 std::vector<MachineInstr*>& mvec,
175 MachineCodeForInstruction& mcfi) const;
177 // Create instruction sequence to produce a sign-extended register value
178 // from an arbitrary sized value (sized in bits, not bytes).
179 // Any stack space required is allocated via mcff.
181 virtual void CreateSignExtensionInstructions(const TargetMachine& target,
183 Value* unsignedSrcVal,
184 unsigned int srcSizeInBits,
186 std::vector<MachineInstr*>& mvec,
187 MachineCodeForInstruction& mcfi) const;
191 //----------------------------------------------------------------------------
192 // class UltraSparcRegInfo
194 // This class implements the virtual class MachineRegInfo for Sparc.
196 //----------------------------------------------------------------------------
198 class UltraSparcRegInfo : public MachineRegInfo {
199 // The actual register classes in the Sparc
202 IntRegClassID, // Integer
203 FloatRegClassID, // Float (both single/double)
204 IntCCRegClassID, // Int Condition Code
205 FloatCCRegClassID // Float Condition code
209 // Type of registers available in Sparc. There can be several reg types
210 // in the same class. For instace, the float reg class has Single/Double
221 // **** WARNING: If the above enum order is changed, also modify
222 // getRegisterClassOfValue method below since it assumes this particular
223 // order for efficiency.
226 // reverse pointer to get info about the ultra sparc machine
228 const UltraSparc *const UltraSparcInfo;
230 // Number of registers used for passing int args (usually 6: %o0 - %o5)
232 unsigned const NumOfIntArgRegs;
234 // Number of registers used for passing float args (usually 32: %f0 - %f31)
236 unsigned const NumOfFloatArgRegs;
238 // An out of bound register number that can be used to initialize register
239 // numbers. Useful for error detection.
241 int const InvalidRegNum;
244 // ======================== Private Methods =============================
246 // The following methods are used to color special live ranges (e.g.
247 // function args and return values etc.) with specific hardware registers
248 // as required. See SparcRegInfo.cpp for the implementation.
250 void setCallOrRetArgCol(LiveRange *LR, unsigned RegNo,
251 const MachineInstr *MI,
252 std::hash_map<const MachineInstr *,
253 AddedInstrns *> &AIMap) const;
255 MachineInstr *getCopy2RegMI(const Value *SrcVal, unsigned Reg,
256 unsigned RegClassID) const;
258 void suggestReg4RetAddr(const MachineInstr *RetMI,
259 LiveRangeInfo &LRI) const;
261 void suggestReg4CallAddr(const MachineInstr *CallMI, LiveRangeInfo &LRI,
262 std::vector<RegClass *> RCList) const;
264 void InitializeOutgoingArg(const MachineInstr* CallMI, AddedInstrns *CallAI,
265 PhyRegAlloc &PRA, LiveRange* LR,
266 unsigned regType, unsigned RegClassID,
267 int UniArgReg, unsigned int argNo,
268 std::vector<MachineInstr *>& AddedInstrnsBefore)
271 // The following 4 methods are used to find the RegType (see enum above)
272 // of a LiveRange, Value and using the unified RegClassID
273 int getRegType(unsigned regClassID, const Type* type) const;
274 int getRegType(const LiveRange *LR) const;
275 int getRegType(const Value *Val) const;
276 int getRegType(int reg) const;
279 // The following methods are used to generate copy instructions to move
280 // data between condition code registers
282 MachineInstr *cpCCR2IntMI(unsigned IntReg) const;
283 MachineInstr *cpInt2CCRMI(unsigned IntReg) const;
285 // Used to generate a copy instruction based on the register class of
288 MachineInstr *cpValue2RegMI(Value *Val, unsigned DestReg,
292 // The following 2 methods are used to order the instructions addeed by
293 // the register allocator in association with function calling. See
294 // SparcRegInfo.cpp for more details
296 void moveInst2OrdVec(std::vector<MachineInstr *> &OrdVec,
297 MachineInstr *UnordInst,
298 PhyRegAlloc &PRA) const;
300 void OrderAddedInstrns(std::vector<MachineInstr *> &UnordVec,
301 std::vector<MachineInstr *> &OrdVec,
302 PhyRegAlloc &PRA) const;
305 // Compute which register can be used for an argument, if any
307 int regNumForIntArg(bool inCallee, bool isVarArgsCall,
308 unsigned argNo, unsigned intArgNo, unsigned fpArgNo,
309 unsigned& regClassId) const;
311 int regNumForFPArg(unsigned RegType, bool inCallee, bool isVarArgsCall,
312 unsigned argNo, unsigned intArgNo, unsigned fpArgNo,
313 unsigned& regClassId) const;
316 UltraSparcRegInfo(const UltraSparc &tgt);
318 // To get complete machine information structure using the machine register
321 inline const UltraSparc &getUltraSparcInfo() const {
322 return *UltraSparcInfo;
325 // To find the register class used for a specified Type
327 inline unsigned getRegClassIDOfType(const Type *type,
328 bool isCCReg = false) const {
329 Type::PrimitiveID ty = type->getPrimitiveID();
332 // FIXME: Comparing types like this isn't very safe...
333 if ((ty && ty <= Type::LongTyID) || (ty == Type::LabelTyID) ||
334 (ty == Type::FunctionTyID) || (ty == Type::PointerTyID) )
335 res = IntRegClassID; // sparc int reg (ty=0: void)
336 else if (ty <= Type::DoubleTyID)
337 res = FloatRegClassID; // sparc float reg class
339 //std::cerr << "TypeID: " << ty << "\n";
340 assert(0 && "Cannot resolve register class for type");
345 return res + 2; // corresponidng condition code regiser
350 // To find the register class of a Value
352 inline unsigned getRegClassIDOfValue(const Value *Val,
353 bool isCCReg = false) const {
354 return getRegClassIDOfType(Val->getType(), isCCReg);
359 // getZeroRegNum - returns the register that contains always zero this is the
360 // unified register number
362 virtual int getZeroRegNum() const;
364 // getCallAddressReg - returns the reg used for pushing the address when a
365 // function is called. This can be used for other purposes between calls
367 unsigned getCallAddressReg() const;
369 // Returns the register containing the return address.
370 // It should be made sure that this register contains the return
371 // value when a return instruction is reached.
373 unsigned getReturnAddressReg() const;
375 // Number of registers used for passing int args (usually 6: %o0 - %o5)
376 // and float args (usually 32: %f0 - %f31)
378 unsigned const GetNumOfIntArgRegs() const { return NumOfIntArgRegs; }
379 unsigned const GetNumOfFloatArgRegs() const { return NumOfFloatArgRegs; }
381 // The following methods are used to color special live ranges (e.g.
382 // function args and return values etc.) with specific hardware registers
383 // as required. See SparcRegInfo.cpp for the implementation for Sparc.
385 void suggestRegs4MethodArgs(const Function *Meth,
386 LiveRangeInfo& LRI) const;
388 void suggestRegs4CallArgs(const MachineInstr *CallMI,
390 std::vector<RegClass *> RCL) const;
392 void suggestReg4RetValue(const MachineInstr *RetMI,
393 LiveRangeInfo& LRI) const;
396 void colorMethodArgs(const Function *Meth, LiveRangeInfo &LRI,
397 AddedInstrns *FirstAI) const;
399 void colorCallArgs(const MachineInstr *CallMI, LiveRangeInfo &LRI,
400 AddedInstrns *CallAI, PhyRegAlloc &PRA,
401 const BasicBlock *BB) const;
403 void colorRetValue(const MachineInstr *RetI, LiveRangeInfo& LRI,
404 AddedInstrns *RetAI) const;
408 // method used for printing a register for debugging purposes
410 static void printReg(const LiveRange *LR);
412 // this method provides a unique number for each register
414 inline int getUnifiedRegNum(int RegClassID, int reg) const {
416 if( RegClassID == IntRegClassID && reg < 32 )
418 else if ( RegClassID == FloatRegClassID && reg < 64)
419 return reg + 32; // we have 32 int regs
420 else if( RegClassID == FloatCCRegClassID && reg < 4)
421 return reg + 32 + 64; // 32 int, 64 float
422 else if( RegClassID == IntCCRegClassID )
423 return reg + 4+ 32 + 64; // only int cc reg
424 else if (reg==InvalidRegNum)
425 return InvalidRegNum;
427 assert(0 && "Invalid register class or reg number");
431 // given the unified register number, this gives the name
432 // for generating assembly code or debugging.
434 virtual const std::string getUnifiedRegName(int reg) const;
437 // returns the # of bytes of stack space allocated for each register
438 // type. For Sparc, currently we allocate 8 bytes on stack for all
439 // register types. We can optimize this later if necessary to save stack
440 // space (However, should make sure that stack alignment is correct)
442 inline int getSpilledRegSize(int RegType) const {
447 // To obtain the return value and the indirect call address (if any)
448 // contained in a CALL machine instruction
450 const Value * getCallInstRetVal(const MachineInstr *CallMI) const;
451 const Value * getCallInstIndirectAddrVal(const MachineInstr *CallMI) const;
453 // The following methods are used to generate "copy" machine instructions
454 // for an architecture.
456 void cpReg2RegMI(unsigned SrcReg, unsigned DestReg,
457 int RegType, std::vector<MachineInstr*>& mvec) const;
459 void cpReg2MemMI(unsigned SrcReg, unsigned DestPtrReg,
460 int Offset, int RegType, std::vector<MachineInstr*>& mvec) const;
462 void cpMem2RegMI(unsigned SrcPtrReg, int Offset, unsigned DestReg,
463 int RegType, std::vector<MachineInstr*>& mvec) const;
465 void cpValue2Value(Value *Src, Value *Dest,
466 std::vector<MachineInstr*>& mvec) const;
468 // To see whether a register is a volatile (i.e., whehter it must be
469 // preserved acorss calls)
471 inline bool isRegVolatile(int RegClassID, int Reg) const {
472 return MachineRegClassArr[RegClassID]->isRegVolatile(Reg);
476 virtual unsigned getFramePointer() const;
477 virtual unsigned getStackPointer() const;
479 virtual int getInvalidRegNum() const {
480 return InvalidRegNum;
483 // This method inserts the caller saving code for call instructions
485 void insertCallerSavingCode(const MachineInstr *MInst,
486 const BasicBlock *BB, PhyRegAlloc &PRA ) const;
492 //---------------------------------------------------------------------------
493 // class UltraSparcSchedInfo
496 // Interface to instruction scheduling information for UltraSPARC.
497 // The parameter values above are based on UltraSPARC IIi.
498 //---------------------------------------------------------------------------
501 class UltraSparcSchedInfo: public MachineSchedInfo {
503 UltraSparcSchedInfo(const TargetMachine &tgt);
505 virtual void initializeResources();
509 //---------------------------------------------------------------------------
510 // class UltraSparcFrameInfo
513 // Interface to stack frame layout info for the UltraSPARC.
514 // Starting offsets for each area of the stack frame are aligned at
515 // a multiple of getStackFrameSizeAlignment().
516 //---------------------------------------------------------------------------
518 class UltraSparcFrameInfo: public MachineFrameInfo {
520 UltraSparcFrameInfo(const TargetMachine &tgt) : MachineFrameInfo(tgt) {}
523 int getStackFrameSizeAlignment() const { return StackFrameSizeAlignment;}
524 int getMinStackFrameSize() const { return MinStackFrameSize; }
525 int getNumFixedOutgoingArgs() const { return NumFixedOutgoingArgs; }
526 int getSizeOfEachArgOnStack() const { return SizeOfEachArgOnStack; }
527 bool argsOnStackHaveFixedSize() const { return true; }
530 // These methods compute offsets using the frame contents for a
531 // particular function. The frame contents are obtained from the
532 // MachineCodeInfoForMethod object for the given function.
534 int getFirstIncomingArgOffset (MachineCodeForMethod& mcInfo,
537 growUp = true; // arguments area grows upwards
538 return FirstIncomingArgOffsetFromFP;
540 int getFirstOutgoingArgOffset (MachineCodeForMethod& mcInfo,
543 growUp = true; // arguments area grows upwards
544 return FirstOutgoingArgOffsetFromSP;
546 int getFirstOptionalOutgoingArgOffset(MachineCodeForMethod& mcInfo,
549 growUp = true; // arguments area grows upwards
550 return FirstOptionalOutgoingArgOffsetFromSP;
553 int getFirstAutomaticVarOffset (MachineCodeForMethod& mcInfo,
555 int getRegSpillAreaOffset (MachineCodeForMethod& mcInfo,
557 int getTmpAreaOffset (MachineCodeForMethod& mcInfo,
559 int getDynamicAreaOffset (MachineCodeForMethod& mcInfo,
563 // These methods specify the base register used for each stack area
564 // (generally FP or SP)
566 virtual int getIncomingArgBaseRegNum() const {
567 return (int) target.getRegInfo().getFramePointer();
569 virtual int getOutgoingArgBaseRegNum() const {
570 return (int) target.getRegInfo().getStackPointer();
572 virtual int getOptionalOutgoingArgBaseRegNum() const {
573 return (int) target.getRegInfo().getStackPointer();
575 virtual int getAutomaticVarBaseRegNum() const {
576 return (int) target.getRegInfo().getFramePointer();
578 virtual int getRegSpillAreaBaseRegNum() const {
579 return (int) target.getRegInfo().getFramePointer();
581 virtual int getDynamicAreaBaseRegNum() const {
582 return (int) target.getRegInfo().getStackPointer();
586 // All stack addresses must be offset by 0x7ff (2047) on Sparc V9.
587 static const int OFFSET = (int) 0x7ff;
588 static const int StackFrameSizeAlignment = 16;
589 static const int MinStackFrameSize = 176;
590 static const int NumFixedOutgoingArgs = 6;
591 static const int SizeOfEachArgOnStack = 8;
592 static const int StaticAreaOffsetFromFP = 0 + OFFSET;
593 static const int FirstIncomingArgOffsetFromFP = 128 + OFFSET;
594 static const int FirstOptionalIncomingArgOffsetFromFP = 176 + OFFSET;
595 static const int FirstOutgoingArgOffsetFromSP = 128 + OFFSET;
596 static const int FirstOptionalOutgoingArgOffsetFromSP = 176 + OFFSET;
600 //---------------------------------------------------------------------------
601 // class UltraSparcCacheInfo
604 // Interface to cache parameters for the UltraSPARC.
605 // Just use defaults for now.
606 //---------------------------------------------------------------------------
608 class UltraSparcCacheInfo: public MachineCacheInfo {
610 UltraSparcCacheInfo(const TargetMachine &T) : MachineCacheInfo(T) {}
614 //---------------------------------------------------------------------------
615 // class UltraSparcMachine
618 // Primary interface to machine description for the UltraSPARC.
619 // Primarily just initializes machine-dependent parameters in
620 // class TargetMachine, and creates machine-dependent subclasses
621 // for classes such as InstrInfo, SchedInfo and RegInfo.
622 //---------------------------------------------------------------------------
624 class UltraSparc : public TargetMachine {
626 UltraSparcInstrInfo instrInfo;
627 UltraSparcSchedInfo schedInfo;
628 UltraSparcRegInfo regInfo;
629 UltraSparcFrameInfo frameInfo;
630 UltraSparcCacheInfo cacheInfo;
634 virtual const MachineInstrInfo &getInstrInfo() const { return instrInfo; }
635 virtual const MachineSchedInfo &getSchedInfo() const { return schedInfo; }
636 virtual const MachineRegInfo &getRegInfo() const { return regInfo; }
637 virtual const MachineFrameInfo &getFrameInfo() const { return frameInfo; }
638 virtual const MachineCacheInfo &getCacheInfo() const { return cacheInfo; }
641 // addPassesToEmitAssembly - Add passes to the specified pass manager to get
642 // assembly langage code emited. For sparc, we have to do ...
644 virtual void addPassesToEmitAssembly(PassManager &PM, std::ostream &Out);
647 Pass *getFunctionAsmPrinterPass(PassManager &PM, std::ostream &Out);
648 Pass *getModuleAsmPrinterPass(PassManager &PM, std::ostream &Out);
649 Pass *getEmitBytecodeToAsmPass(std::ostream &Out);