1 //===-- SparcInternals.h ----------------------------------------*- C++ -*-===//
3 // This file defines stuff that is to be private to the Sparc backend, but is
4 // shared among different portions of the backend.
6 //===----------------------------------------------------------------------===//
8 #ifndef SPARC_INTERNALS_H
9 #define SPARC_INTERNALS_H
11 #include "llvm/Target/TargetMachine.h"
12 #include "llvm/Target/MachineSchedInfo.h"
13 #include "llvm/Target/MachineFrameInfo.h"
14 #include "llvm/Target/MachineCacheInfo.h"
15 #include "llvm/Target/MachineRegInfo.h"
16 #include "llvm/Type.h"
17 #include <sys/types.h>
24 Pass *createPrologEpilogCodeInserter(TargetMachine &TM);
26 // OpCodeMask definitions for the Sparc V9
28 const OpCodeMask Immed = 0x00002000; // immed or reg operand?
29 const OpCodeMask Annul = 0x20000000; // annul delay instr?
30 const OpCodeMask PredictTaken = 0x00080000; // predict branch taken?
33 enum SparcInstrSchedClass {
34 SPARC_NONE, /* Instructions with no scheduling restrictions */
35 SPARC_IEUN, /* Integer class that can use IEU0 or IEU1 */
36 SPARC_IEU0, /* Integer class IEU0 */
37 SPARC_IEU1, /* Integer class IEU1 */
38 SPARC_FPM, /* FP Multiply or Divide instructions */
39 SPARC_FPA, /* All other FP instructions */
40 SPARC_CTI, /* Control-transfer instructions */
41 SPARC_LD, /* Load instructions */
42 SPARC_ST, /* Store instructions */
43 SPARC_SINGLE, /* Instructions that must issue by themselves */
45 SPARC_INV, /* This should stay at the end for the next value */
46 SPARC_NUM_SCHED_CLASSES = SPARC_INV
50 //---------------------------------------------------------------------------
51 // enum SparcMachineOpCode.
52 // const MachineInstrDescriptor SparcMachineInstrDesc[]
55 // Description of UltraSparc machine instructions.
57 //---------------------------------------------------------------------------
59 enum SparcMachineOpCode {
60 #define I(ENUM, OPCODESTRING, NUMOPERANDS, RESULTPOS, MAXIMM, IMMSE, \
61 NUMDELAYSLOTS, LATENCY, SCHEDCLASS, INSTFLAGS) \
63 #include "SparcInstr.def"
65 // End-of-array marker
67 NUM_REAL_OPCODES = PHI, // number of valid opcodes
68 NUM_TOTAL_OPCODES = INVALID_OPCODE
72 // Array of machine instruction descriptions...
73 extern const MachineInstrDescriptor SparcMachineInstrDesc[];
76 //---------------------------------------------------------------------------
77 // class UltraSparcInstrInfo
80 // Information about individual instructions.
81 // Most information is stored in the SparcMachineInstrDesc array above.
82 // Other information is computed on demand, and most such functions
83 // default to member functions in base class MachineInstrInfo.
84 //---------------------------------------------------------------------------
86 struct UltraSparcInstrInfo : public MachineInstrInfo {
87 UltraSparcInstrInfo(const TargetMachine& tgt);
90 // All immediate constants are in position 1 except the
91 // store instructions.
93 virtual int getImmedConstantPos(MachineOpCode opCode) const {
95 if (this->maxImmedConstant(opCode, ignore) != 0)
97 assert(! this->isStore((MachineOpCode) STB - 1)); // 1st store opcode
98 assert(! this->isStore((MachineOpCode) STXFSR+1));// last store opcode
99 return (opCode >= STB && opCode <= STXFSR)? 2 : 1;
105 virtual bool hasResultInterlock (MachineOpCode opCode) const
107 // All UltraSPARC instructions have interlocks (note that delay slots
108 // are not considered here).
109 // However, instructions that use the result of an FCMP produce a
110 // 9-cycle stall if they are issued less than 3 cycles after the FCMP.
111 // Force the compiler to insert a software interlock (i.e., gap of
112 // 2 other groups, including NOPs if necessary).
113 return (opCode == FCMPS || opCode == FCMPD || opCode == FCMPQ);
116 //-------------------------------------------------------------------------
117 // Code generation support for creating individual machine instructions
118 //-------------------------------------------------------------------------
120 // Create an instruction sequence to put the constant `val' into
121 // the virtual register `dest'. `val' may be a Constant or a
122 // GlobalValue, viz., the constant address of a global variable or function.
123 // The generated instructions are returned in `mvec'.
124 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
125 // Any stack space required is allocated via mcff.
127 virtual void CreateCodeToLoadConst(const TargetMachine& target,
131 std::vector<MachineInstr*>& mvec,
132 MachineCodeForInstruction& mcfi) const;
134 // Create an instruction sequence to copy an integer value `val'
135 // to a floating point value `dest' by copying to memory and back.
136 // val must be an integral type. dest must be a Float or Double.
137 // The generated instructions are returned in `mvec'.
138 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
139 // Any stack space required is allocated via mcff.
141 virtual void CreateCodeToCopyIntToFloat(const TargetMachine& target,
145 std::vector<MachineInstr*>& mvec,
146 MachineCodeForInstruction& mcfi) const;
148 // Similarly, create an instruction sequence to copy an FP value
149 // `val' to an integer value `dest' by copying to memory and back.
150 // The generated instructions are returned in `mvec'.
151 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
152 // Any stack space required is allocated via mcff.
154 virtual void CreateCodeToCopyFloatToInt(const TargetMachine& target,
158 std::vector<MachineInstr*>& mvec,
159 MachineCodeForInstruction& mcfi) const;
161 // Create instruction(s) to copy src to dest, for arbitrary types
162 // The generated instructions are returned in `mvec'.
163 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
164 // Any stack space required is allocated via mcff.
166 virtual void CreateCopyInstructionsByType(const TargetMachine& target,
170 std::vector<MachineInstr*>& mvec,
171 MachineCodeForInstruction& mcfi) const;
173 // Create instruction sequence to produce a sign-extended register value
174 // from an arbitrary sized value (sized in bits, not bytes).
175 // The generated instructions are appended to `mvec'.
176 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
177 // Any stack space required is allocated via mcff.
179 virtual void CreateSignExtensionInstructions(const TargetMachine& target,
182 unsigned int srcSizeInBits,
184 std::vector<MachineInstr*>& mvec,
185 MachineCodeForInstruction& mcfi) const;
187 // Create instruction sequence to produce a zero-extended register value
188 // from an arbitrary sized value (sized in bits, not bytes).
189 // The generated instructions are appended to `mvec'.
190 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
191 // Any stack space required is allocated via mcff.
193 virtual void CreateZeroExtensionInstructions(const TargetMachine& target,
196 unsigned int srcSizeInBits,
198 std::vector<MachineInstr*>& mvec,
199 MachineCodeForInstruction& mcfi) const;
203 //----------------------------------------------------------------------------
204 // class UltraSparcRegInfo
206 // This class implements the virtual class MachineRegInfo for Sparc.
208 //----------------------------------------------------------------------------
210 class UltraSparcRegInfo : public MachineRegInfo {
211 // The actual register classes in the Sparc
214 IntRegClassID, // Integer
215 FloatRegClassID, // Float (both single/double)
216 IntCCRegClassID, // Int Condition Code
217 FloatCCRegClassID // Float Condition code
221 // Type of registers available in Sparc. There can be several reg types
222 // in the same class. For instace, the float reg class has Single/Double
233 // **** WARNING: If the above enum order is changed, also modify
234 // getRegisterClassOfValue method below since it assumes this particular
235 // order for efficiency.
238 // reverse pointer to get info about the ultra sparc machine
240 const UltraSparc *const UltraSparcInfo;
242 // Number of registers used for passing int args (usually 6: %o0 - %o5)
244 unsigned const NumOfIntArgRegs;
246 // Number of registers used for passing float args (usually 32: %f0 - %f31)
248 unsigned const NumOfFloatArgRegs;
250 // An out of bound register number that can be used to initialize register
251 // numbers. Useful for error detection.
253 int const InvalidRegNum;
256 // ======================== Private Methods =============================
258 // The following methods are used to color special live ranges (e.g.
259 // function args and return values etc.) with specific hardware registers
260 // as required. See SparcRegInfo.cpp for the implementation.
262 void suggestReg4RetAddr(MachineInstr *RetMI,
263 LiveRangeInfo &LRI) const;
265 void suggestReg4CallAddr(MachineInstr *CallMI, LiveRangeInfo &LRI,
266 std::vector<RegClass *> RCList) const;
268 void InitializeOutgoingArg(MachineInstr* CallMI, AddedInstrns *CallAI,
269 PhyRegAlloc &PRA, LiveRange* LR,
270 unsigned regType, unsigned RegClassID,
271 int UniArgReg, unsigned int argNo,
272 std::vector<MachineInstr *>& AddedInstrnsBefore)
275 // The following 4 methods are used to find the RegType (see enum above)
276 // for a reg class and a given primitive type, a LiveRange, a Value,
277 // or a particular machine register.
278 // The fifth function gives the reg class of the given RegType.
280 int getRegType(unsigned regClassID, const Type* type) const;
281 int getRegType(const LiveRange *LR) const;
282 int getRegType(const Value *Val) const;
283 int getRegType(int unifiedRegNum) const;
285 // Used to generate a copy instruction based on the register class of
288 MachineInstr *cpValue2RegMI(Value *Val, unsigned DestReg,
292 // The following 2 methods are used to order the instructions addeed by
293 // the register allocator in association with function calling. See
294 // SparcRegInfo.cpp for more details
296 void moveInst2OrdVec(std::vector<MachineInstr *> &OrdVec,
297 MachineInstr *UnordInst,
298 PhyRegAlloc &PRA) const;
300 void OrderAddedInstrns(std::vector<MachineInstr *> &UnordVec,
301 std::vector<MachineInstr *> &OrdVec,
302 PhyRegAlloc &PRA) const;
305 // Compute which register can be used for an argument, if any
307 int regNumForIntArg(bool inCallee, bool isVarArgsCall,
308 unsigned argNo, unsigned intArgNo, unsigned fpArgNo,
309 unsigned& regClassId) const;
311 int regNumForFPArg(unsigned RegType, bool inCallee, bool isVarArgsCall,
312 unsigned argNo, unsigned intArgNo, unsigned fpArgNo,
313 unsigned& regClassId) const;
316 UltraSparcRegInfo(const UltraSparc &tgt);
318 // To get complete machine information structure using the machine register
321 inline const UltraSparc &getUltraSparcInfo() const {
322 return *UltraSparcInfo;
325 // To find the register class used for a specified Type
327 unsigned getRegClassIDOfType(const Type *type,
328 bool isCCReg = false) const;
330 // To find the register class of a Value
332 inline unsigned getRegClassIDOfValue(const Value *Val,
333 bool isCCReg = false) const {
334 return getRegClassIDOfType(Val->getType(), isCCReg);
337 // To find the register class to which a specified register belongs
339 unsigned getRegClassIDOfReg(int unifiedRegNum) const;
340 unsigned getRegClassIDOfRegType(int regType) const;
342 // getZeroRegNum - returns the register that contains always zero this is the
343 // unified register number
345 virtual int getZeroRegNum() const;
347 // getCallAddressReg - returns the reg used for pushing the address when a
348 // function is called. This can be used for other purposes between calls
350 unsigned getCallAddressReg() const;
352 // Returns the register containing the return address.
353 // It should be made sure that this register contains the return
354 // value when a return instruction is reached.
356 unsigned getReturnAddressReg() const;
358 // Number of registers used for passing int args (usually 6: %o0 - %o5)
359 // and float args (usually 32: %f0 - %f31)
361 unsigned const GetNumOfIntArgRegs() const { return NumOfIntArgRegs; }
362 unsigned const GetNumOfFloatArgRegs() const { return NumOfFloatArgRegs; }
364 // The following methods are used to color special live ranges (e.g.
365 // function args and return values etc.) with specific hardware registers
366 // as required. See SparcRegInfo.cpp for the implementation for Sparc.
368 void suggestRegs4MethodArgs(const Function *Meth,
369 LiveRangeInfo& LRI) const;
371 void suggestRegs4CallArgs(MachineInstr *CallMI,
373 std::vector<RegClass *> RCL) const;
375 void suggestReg4RetValue(MachineInstr *RetMI,
376 LiveRangeInfo& LRI) const;
378 void colorMethodArgs(const Function *Meth, LiveRangeInfo &LRI,
379 AddedInstrns *FirstAI) const;
381 void colorCallArgs(MachineInstr *CallMI, LiveRangeInfo &LRI,
382 AddedInstrns *CallAI, PhyRegAlloc &PRA,
383 const BasicBlock *BB) const;
385 void colorRetValue(MachineInstr *RetI, LiveRangeInfo& LRI,
386 AddedInstrns *RetAI) const;
389 // method used for printing a register for debugging purposes
391 static void printReg(const LiveRange *LR);
393 // Each register class has a seperate space for register IDs. To convert
394 // a regId in a register class to a common Id, or vice versa,
395 // we use the folloing methods.
397 // This method provides a unique number for each register
398 inline int getUnifiedRegNum(unsigned regClassID, int reg) const {
400 if (regClassID == IntRegClassID) {
401 assert(reg < 32 && "Invalid reg. number");
404 else if (regClassID == FloatRegClassID) {
405 assert(reg < 64 && "Invalid reg. number");
406 return reg + 32; // we have 32 int regs
408 else if (regClassID == FloatCCRegClassID) {
409 assert(reg < 4 && "Invalid reg. number");
410 return reg + 32 + 64; // 32 int, 64 float
412 else if (regClassID == IntCCRegClassID ) {
413 assert(reg == 0 && "Invalid reg. number");
414 return reg + 4+ 32 + 64; // only one int CC reg
416 else if (reg==InvalidRegNum) {
417 return InvalidRegNum;
420 assert(0 && "Invalid register class");
424 // This method converts the unified number to the number in its class,
425 // and returns the class ID in regClassID.
426 inline int getClassRegNum(int ureg, unsigned& regClassID) const {
427 if (ureg < 32) { regClassID = IntRegClassID; return ureg; }
428 else if (ureg < 32+64) { regClassID = FloatRegClassID; return ureg-32; }
429 else if (ureg < 4 +96) { regClassID = FloatCCRegClassID; return ureg-96; }
430 else if (ureg < 1 +100) { regClassID = IntCCRegClassID; return ureg-100;}
431 else if (ureg == InvalidRegNum) { return InvalidRegNum; }
432 else { assert(0 && "Invalid unified register number"); }
436 // Returns the assembly-language name of the specified machine register.
438 virtual const char * const getUnifiedRegName(int reg) const;
441 // returns the # of bytes of stack space allocated for each register
442 // type. For Sparc, currently we allocate 8 bytes on stack for all
443 // register types. We can optimize this later if necessary to save stack
444 // space (However, should make sure that stack alignment is correct)
446 inline int getSpilledRegSize(int RegType) const {
451 // To obtain the return value and the indirect call address (if any)
452 // contained in a CALL machine instruction
454 const Value * getCallInstRetVal(const MachineInstr *CallMI) const;
455 const Value * getCallInstIndirectAddrVal(const MachineInstr *CallMI) const;
457 // The following methods are used to generate "copy" machine instructions
458 // for an architecture.
460 // The function regTypeNeedsScratchReg() can be used to check whether a
461 // scratch register is needed to copy a register of type `regType' to
462 // or from memory. If so, such a scratch register can be provided by
463 // the caller (e.g., if it knows which regsiters are free); otherwise
464 // an arbitrary one will be chosen and spilled by the copy instructions.
466 bool regTypeNeedsScratchReg(int RegType,
467 int& scratchRegClassId) const;
469 void cpReg2RegMI(std::vector<MachineInstr*>& mvec,
470 unsigned SrcReg, unsigned DestReg,
473 void cpReg2MemMI(std::vector<MachineInstr*>& mvec,
474 unsigned SrcReg, unsigned DestPtrReg,
475 int Offset, int RegType, int scratchReg = -1) const;
477 void cpMem2RegMI(std::vector<MachineInstr*>& mvec,
478 unsigned SrcPtrReg, int Offset, unsigned DestReg,
479 int RegType, int scratchReg = -1) const;
481 void cpValue2Value(Value *Src, Value *Dest,
482 std::vector<MachineInstr*>& mvec) const;
484 // To see whether a register is a volatile (i.e., whehter it must be
485 // preserved acorss calls)
487 inline bool isRegVolatile(int RegClassID, int Reg) const {
488 return MachineRegClassArr[RegClassID]->isRegVolatile(Reg);
492 virtual unsigned getFramePointer() const;
493 virtual unsigned getStackPointer() const;
495 virtual int getInvalidRegNum() const {
496 return InvalidRegNum;
499 // This method inserts the caller saving code for call instructions
501 void insertCallerSavingCode(std::vector<MachineInstr*>& instrnsBefore,
502 std::vector<MachineInstr*>& instrnsAfter,
504 const BasicBlock *BB, PhyRegAlloc &PRA ) const;
510 //---------------------------------------------------------------------------
511 // class UltraSparcSchedInfo
514 // Interface to instruction scheduling information for UltraSPARC.
515 // The parameter values above are based on UltraSPARC IIi.
516 //---------------------------------------------------------------------------
519 class UltraSparcSchedInfo: public MachineSchedInfo {
521 UltraSparcSchedInfo(const TargetMachine &tgt);
523 virtual void initializeResources();
527 //---------------------------------------------------------------------------
528 // class UltraSparcFrameInfo
531 // Interface to stack frame layout info for the UltraSPARC.
532 // Starting offsets for each area of the stack frame are aligned at
533 // a multiple of getStackFrameSizeAlignment().
534 //---------------------------------------------------------------------------
536 class UltraSparcFrameInfo: public MachineFrameInfo {
538 UltraSparcFrameInfo(const TargetMachine &tgt) : MachineFrameInfo(tgt) {}
541 int getStackFrameSizeAlignment() const { return StackFrameSizeAlignment;}
542 int getMinStackFrameSize() const { return MinStackFrameSize; }
543 int getNumFixedOutgoingArgs() const { return NumFixedOutgoingArgs; }
544 int getSizeOfEachArgOnStack() const { return SizeOfEachArgOnStack; }
545 bool argsOnStackHaveFixedSize() const { return true; }
548 // These methods compute offsets using the frame contents for a
549 // particular function. The frame contents are obtained from the
550 // MachineCodeInfoForMethod object for the given function.
552 int getFirstIncomingArgOffset (MachineCodeForMethod& mcInfo,
555 growUp = true; // arguments area grows upwards
556 return FirstIncomingArgOffsetFromFP;
558 int getFirstOutgoingArgOffset (MachineCodeForMethod& mcInfo,
561 growUp = true; // arguments area grows upwards
562 return FirstOutgoingArgOffsetFromSP;
564 int getFirstOptionalOutgoingArgOffset(MachineCodeForMethod& mcInfo,
567 growUp = true; // arguments area grows upwards
568 return FirstOptionalOutgoingArgOffsetFromSP;
571 int getFirstAutomaticVarOffset (MachineCodeForMethod& mcInfo,
573 int getRegSpillAreaOffset (MachineCodeForMethod& mcInfo,
575 int getTmpAreaOffset (MachineCodeForMethod& mcInfo,
577 int getDynamicAreaOffset (MachineCodeForMethod& mcInfo,
581 // These methods specify the base register used for each stack area
582 // (generally FP or SP)
584 virtual int getIncomingArgBaseRegNum() const {
585 return (int) target.getRegInfo().getFramePointer();
587 virtual int getOutgoingArgBaseRegNum() const {
588 return (int) target.getRegInfo().getStackPointer();
590 virtual int getOptionalOutgoingArgBaseRegNum() const {
591 return (int) target.getRegInfo().getStackPointer();
593 virtual int getAutomaticVarBaseRegNum() const {
594 return (int) target.getRegInfo().getFramePointer();
596 virtual int getRegSpillAreaBaseRegNum() const {
597 return (int) target.getRegInfo().getFramePointer();
599 virtual int getDynamicAreaBaseRegNum() const {
600 return (int) target.getRegInfo().getStackPointer();
604 // All stack addresses must be offset by 0x7ff (2047) on Sparc V9.
605 static const int OFFSET = (int) 0x7ff;
606 static const int StackFrameSizeAlignment = 16;
607 static const int MinStackFrameSize = 176;
608 static const int NumFixedOutgoingArgs = 6;
609 static const int SizeOfEachArgOnStack = 8;
610 static const int StaticAreaOffsetFromFP = 0 + OFFSET;
611 static const int FirstIncomingArgOffsetFromFP = 128 + OFFSET;
612 static const int FirstOptionalIncomingArgOffsetFromFP = 176 + OFFSET;
613 static const int FirstOutgoingArgOffsetFromSP = 128 + OFFSET;
614 static const int FirstOptionalOutgoingArgOffsetFromSP = 176 + OFFSET;
618 //---------------------------------------------------------------------------
619 // class UltraSparcCacheInfo
622 // Interface to cache parameters for the UltraSPARC.
623 // Just use defaults for now.
624 //---------------------------------------------------------------------------
626 class UltraSparcCacheInfo: public MachineCacheInfo {
628 UltraSparcCacheInfo(const TargetMachine &T) : MachineCacheInfo(T) {}
632 //---------------------------------------------------------------------------
633 // class UltraSparcMachine
636 // Primary interface to machine description for the UltraSPARC.
637 // Primarily just initializes machine-dependent parameters in
638 // class TargetMachine, and creates machine-dependent subclasses
639 // for classes such as InstrInfo, SchedInfo and RegInfo.
640 //---------------------------------------------------------------------------
642 class UltraSparc : public TargetMachine {
644 UltraSparcInstrInfo instrInfo;
645 UltraSparcSchedInfo schedInfo;
646 UltraSparcRegInfo regInfo;
647 UltraSparcFrameInfo frameInfo;
648 UltraSparcCacheInfo cacheInfo;
652 virtual const MachineInstrInfo &getInstrInfo() const { return instrInfo; }
653 virtual const MachineSchedInfo &getSchedInfo() const { return schedInfo; }
654 virtual const MachineRegInfo &getRegInfo() const { return regInfo; }
655 virtual const MachineFrameInfo &getFrameInfo() const { return frameInfo; }
656 virtual const MachineCacheInfo &getCacheInfo() const { return cacheInfo; }
659 // addPassesToEmitAssembly - Add passes to the specified pass manager to get
660 // assembly langage code emited. For sparc, we have to do ...
662 virtual void addPassesToEmitAssembly(PassManager &PM, std::ostream &Out);
665 Pass *getFunctionAsmPrinterPass(PassManager &PM, std::ostream &Out);
666 Pass *getModuleAsmPrinterPass(PassManager &PM, std::ostream &Out);
667 Pass *getEmitBytecodeToAsmPass(std::ostream &Out);