1 //===-- SparcInternals.h ----------------------------------------*- C++ -*-===//
3 // This file defines stuff that is to be private to the Sparc backend, but is
4 // shared among different portions of the backend.
6 //===----------------------------------------------------------------------===//
8 #ifndef SPARC_INTERNALS_H
9 #define SPARC_INTERNALS_H
11 #include "llvm/Target/TargetMachine.h"
12 #include "llvm/Target/MachineSchedInfo.h"
13 #include "llvm/Target/MachineFrameInfo.h"
14 #include "llvm/Target/MachineCacheInfo.h"
15 #include "llvm/Target/MachineRegInfo.h"
16 #include "llvm/Target/MachineOptInfo.h"
17 #include "llvm/Type.h"
18 #include <sys/types.h>
25 // OpCodeMask definitions for the Sparc V9
27 const OpCodeMask Immed = 0x00002000; // immed or reg operand?
28 const OpCodeMask Annul = 0x20000000; // annul delay instr?
29 const OpCodeMask PredictTaken = 0x00080000; // predict branch taken?
32 enum SparcInstrSchedClass {
33 SPARC_NONE, /* Instructions with no scheduling restrictions */
34 SPARC_IEUN, /* Integer class that can use IEU0 or IEU1 */
35 SPARC_IEU0, /* Integer class IEU0 */
36 SPARC_IEU1, /* Integer class IEU1 */
37 SPARC_FPM, /* FP Multiply or Divide instructions */
38 SPARC_FPA, /* All other FP instructions */
39 SPARC_CTI, /* Control-transfer instructions */
40 SPARC_LD, /* Load instructions */
41 SPARC_ST, /* Store instructions */
42 SPARC_SINGLE, /* Instructions that must issue by themselves */
44 SPARC_INV, /* This should stay at the end for the next value */
45 SPARC_NUM_SCHED_CLASSES = SPARC_INV
49 //---------------------------------------------------------------------------
50 // enum SparcMachineOpCode.
51 // const MachineInstrDescriptor SparcMachineInstrDesc[]
54 // Description of UltraSparc machine instructions.
56 //---------------------------------------------------------------------------
58 enum SparcMachineOpCode {
59 #define I(ENUM, OPCODESTRING, NUMOPERANDS, RESULTPOS, MAXIMM, IMMSE, \
60 NUMDELAYSLOTS, LATENCY, SCHEDCLASS, INSTFLAGS) \
62 #include "SparcInstr.def"
64 // End-of-array marker
66 NUM_REAL_OPCODES = PHI, // number of valid opcodes
67 NUM_TOTAL_OPCODES = INVALID_OPCODE
71 // Array of machine instruction descriptions...
72 extern const MachineInstrDescriptor SparcMachineInstrDesc[];
75 //---------------------------------------------------------------------------
76 // class UltraSparcInstrInfo
79 // Information about individual instructions.
80 // Most information is stored in the SparcMachineInstrDesc array above.
81 // Other information is computed on demand, and most such functions
82 // default to member functions in base class MachineInstrInfo.
83 //---------------------------------------------------------------------------
85 struct UltraSparcInstrInfo : public MachineInstrInfo {
86 UltraSparcInstrInfo(const TargetMachine& tgt);
89 // All immediate constants are in position 1 except the
90 // store instructions and SETxx.
92 virtual int getImmedConstantPos(MachineOpCode opCode) const {
94 if (this->maxImmedConstant(opCode, ignore) != 0)
96 assert(! this->isStore((MachineOpCode) STB - 1)); // 1st store opcode
97 assert(! this->isStore((MachineOpCode) STXFSR+1));// last store opcode
98 if (opCode==SETSW || opCode==SETUW || opCode==SETX || opCode==SETHI)
100 if (opCode >= STB && opCode <= STXFSR)
108 virtual bool hasResultInterlock (MachineOpCode opCode) const
110 // All UltraSPARC instructions have interlocks (note that delay slots
111 // are not considered here).
112 // However, instructions that use the result of an FCMP produce a
113 // 9-cycle stall if they are issued less than 3 cycles after the FCMP.
114 // Force the compiler to insert a software interlock (i.e., gap of
115 // 2 other groups, including NOPs if necessary).
116 return (opCode == FCMPS || opCode == FCMPD || opCode == FCMPQ);
119 //-------------------------------------------------------------------------
120 // Queries about representation of LLVM quantities (e.g., constants)
121 //-------------------------------------------------------------------------
123 virtual bool ConstantMayNotFitInImmedField(const Constant* CV,
124 const Instruction* I) const;
126 //-------------------------------------------------------------------------
127 // Code generation support for creating individual machine instructions
128 //-------------------------------------------------------------------------
130 // Get certain common op codes for the current target. This and all the
131 // Create* methods below should be moved to a machine code generation class
133 virtual MachineOpCode getNOPOpCode() const { return NOP; }
135 // Create an instruction sequence to put the constant `val' into
136 // the virtual register `dest'. `val' may be a Constant or a
137 // GlobalValue, viz., the constant address of a global variable or function.
138 // The generated instructions are returned in `mvec'.
139 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
140 // Any stack space required is allocated via mcff.
142 virtual void CreateCodeToLoadConst(const TargetMachine& target,
146 std::vector<MachineInstr*>& mvec,
147 MachineCodeForInstruction& mcfi) const;
149 // Create an instruction sequence to copy an integer value `val'
150 // to a floating point value `dest' by copying to memory and back.
151 // val must be an integral type. dest must be a Float or Double.
152 // The generated instructions are returned in `mvec'.
153 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
154 // Any stack space required is allocated via mcff.
156 virtual void CreateCodeToCopyIntToFloat(const TargetMachine& target,
160 std::vector<MachineInstr*>& mvec,
161 MachineCodeForInstruction& mcfi) const;
163 // Similarly, create an instruction sequence to copy an FP value
164 // `val' to an integer value `dest' by copying to memory and back.
165 // The generated instructions are returned in `mvec'.
166 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
167 // Any stack space required is allocated via mcff.
169 virtual void CreateCodeToCopyFloatToInt(const TargetMachine& target,
173 std::vector<MachineInstr*>& mvec,
174 MachineCodeForInstruction& mcfi) const;
176 // Create instruction(s) to copy src to dest, for arbitrary types
177 // The generated instructions are returned in `mvec'.
178 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
179 // Any stack space required is allocated via mcff.
181 virtual void CreateCopyInstructionsByType(const TargetMachine& target,
185 std::vector<MachineInstr*>& mvec,
186 MachineCodeForInstruction& mcfi) const;
188 // Create instruction sequence to produce a sign-extended register value
189 // from an arbitrary sized value (sized in bits, not bytes).
190 // The generated instructions are appended to `mvec'.
191 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
192 // Any stack space required is allocated via mcff.
194 virtual void CreateSignExtensionInstructions(const TargetMachine& target,
198 unsigned int numLowBits,
199 std::vector<MachineInstr*>& mvec,
200 MachineCodeForInstruction& mcfi) const;
202 // Create instruction sequence to produce a zero-extended register value
203 // from an arbitrary sized value (sized in bits, not bytes).
204 // The generated instructions are appended to `mvec'.
205 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
206 // Any stack space required is allocated via mcff.
208 virtual void CreateZeroExtensionInstructions(const TargetMachine& target,
212 unsigned int numLowBits,
213 std::vector<MachineInstr*>& mvec,
214 MachineCodeForInstruction& mcfi) const;
218 //----------------------------------------------------------------------------
219 // class UltraSparcRegInfo
221 // This class implements the virtual class MachineRegInfo for Sparc.
223 //----------------------------------------------------------------------------
225 class UltraSparcRegInfo : public MachineRegInfo {
226 // The actual register classes in the Sparc
229 IntRegClassID, // Integer
230 FloatRegClassID, // Float (both single/double)
231 IntCCRegClassID, // Int Condition Code
232 FloatCCRegClassID // Float Condition code
236 // Type of registers available in Sparc. There can be several reg types
237 // in the same class. For instace, the float reg class has Single/Double
248 // **** WARNING: If the above enum order is changed, also modify
249 // getRegisterClassOfValue method below since it assumes this particular
250 // order for efficiency.
253 // Number of registers used for passing int args (usually 6: %o0 - %o5)
255 unsigned const NumOfIntArgRegs;
257 // Number of registers used for passing float args (usually 32: %f0 - %f31)
259 unsigned const NumOfFloatArgRegs;
261 // An out of bound register number that can be used to initialize register
262 // numbers. Useful for error detection.
264 int const InvalidRegNum;
267 // ======================== Private Methods =============================
269 // The following methods are used to color special live ranges (e.g.
270 // function args and return values etc.) with specific hardware registers
271 // as required. See SparcRegInfo.cpp for the implementation.
273 void suggestReg4RetAddr(MachineInstr *RetMI,
274 LiveRangeInfo &LRI) const;
276 void suggestReg4CallAddr(MachineInstr *CallMI, LiveRangeInfo &LRI) const;
278 void InitializeOutgoingArg(MachineInstr* CallMI, AddedInstrns *CallAI,
279 PhyRegAlloc &PRA, LiveRange* LR,
280 unsigned regType, unsigned RegClassID,
281 int UniArgReg, unsigned int argNo,
282 std::vector<MachineInstr *>& AddedInstrnsBefore)
285 // The following 4 methods are used to find the RegType (see enum above)
286 // for a reg class and a given primitive type, a LiveRange, a Value,
287 // or a particular machine register.
288 // The fifth function gives the reg class of the given RegType.
290 int getRegType(unsigned regClassID, const Type* type) const;
291 int getRegType(const LiveRange *LR) const;
292 int getRegType(const Value *Val) const;
293 int getRegType(int unifiedRegNum) const;
295 // Used to generate a copy instruction based on the register class of
298 MachineInstr *cpValue2RegMI(Value *Val, unsigned DestReg,
302 // The following 2 methods are used to order the instructions addeed by
303 // the register allocator in association with function calling. See
304 // SparcRegInfo.cpp for more details
306 void moveInst2OrdVec(std::vector<MachineInstr *> &OrdVec,
307 MachineInstr *UnordInst,
308 PhyRegAlloc &PRA) const;
310 void OrderAddedInstrns(std::vector<MachineInstr *> &UnordVec,
311 std::vector<MachineInstr *> &OrdVec,
312 PhyRegAlloc &PRA) const;
315 // Compute which register can be used for an argument, if any
317 int regNumForIntArg(bool inCallee, bool isVarArgsCall,
318 unsigned argNo, unsigned intArgNo, unsigned fpArgNo,
319 unsigned& regClassId) const;
321 int regNumForFPArg(unsigned RegType, bool inCallee, bool isVarArgsCall,
322 unsigned argNo, unsigned intArgNo, unsigned fpArgNo,
323 unsigned& regClassId) const;
326 UltraSparcRegInfo(const UltraSparc &tgt);
328 // To find the register class used for a specified Type
330 unsigned getRegClassIDOfType(const Type *type,
331 bool isCCReg = false) const;
333 // To find the register class of a Value
335 inline unsigned getRegClassIDOfValue(const Value *Val,
336 bool isCCReg = false) const {
337 return getRegClassIDOfType(Val->getType(), isCCReg);
340 // To find the register class to which a specified register belongs
342 unsigned getRegClassIDOfReg(int unifiedRegNum) const;
343 unsigned getRegClassIDOfRegType(int regType) const;
345 // getZeroRegNum - returns the register that contains always zero this is the
346 // unified register number
348 virtual int getZeroRegNum() const;
350 // getCallAddressReg - returns the reg used for pushing the address when a
351 // function is called. This can be used for other purposes between calls
353 unsigned getCallAddressReg() const;
355 // Returns the register containing the return address.
356 // It should be made sure that this register contains the return
357 // value when a return instruction is reached.
359 unsigned getReturnAddressReg() const;
361 // Number of registers used for passing int args (usually 6: %o0 - %o5)
362 // and float args (usually 32: %f0 - %f31)
364 unsigned const GetNumOfIntArgRegs() const { return NumOfIntArgRegs; }
365 unsigned const GetNumOfFloatArgRegs() const { return NumOfFloatArgRegs; }
367 // The following methods are used to color special live ranges (e.g.
368 // function args and return values etc.) with specific hardware registers
369 // as required. See SparcRegInfo.cpp for the implementation for Sparc.
371 void suggestRegs4MethodArgs(const Function *Meth,
372 LiveRangeInfo& LRI) const;
374 void suggestRegs4CallArgs(MachineInstr *CallMI,
375 LiveRangeInfo& LRI) const;
377 void suggestReg4RetValue(MachineInstr *RetMI,
378 LiveRangeInfo& LRI) const;
380 void colorMethodArgs(const Function *Meth, LiveRangeInfo &LRI,
381 AddedInstrns *FirstAI) const;
383 void colorCallArgs(MachineInstr *CallMI, LiveRangeInfo &LRI,
384 AddedInstrns *CallAI, PhyRegAlloc &PRA,
385 const BasicBlock *BB) const;
387 void colorRetValue(MachineInstr *RetI, LiveRangeInfo& LRI,
388 AddedInstrns *RetAI) const;
391 // method used for printing a register for debugging purposes
393 static void printReg(const LiveRange *LR);
395 // Each register class has a seperate space for register IDs. To convert
396 // a regId in a register class to a common Id, or vice versa,
397 // we use the folloing methods.
399 // This method provides a unique number for each register
400 inline int getUnifiedRegNum(unsigned regClassID, int reg) const {
402 if (regClassID == IntRegClassID) {
403 assert(reg < 32 && "Invalid reg. number");
406 else if (regClassID == FloatRegClassID) {
407 assert(reg < 64 && "Invalid reg. number");
408 return reg + 32; // we have 32 int regs
410 else if (regClassID == FloatCCRegClassID) {
411 assert(reg < 4 && "Invalid reg. number");
412 return reg + 32 + 64; // 32 int, 64 float
414 else if (regClassID == IntCCRegClassID ) {
415 assert(reg == 0 && "Invalid reg. number");
416 return reg + 4+ 32 + 64; // only one int CC reg
418 else if (reg==InvalidRegNum) {
419 return InvalidRegNum;
422 assert(0 && "Invalid register class");
426 // This method converts the unified number to the number in its class,
427 // and returns the class ID in regClassID.
428 inline int getClassRegNum(int ureg, unsigned& regClassID) const {
429 if (ureg < 32) { regClassID = IntRegClassID; return ureg; }
430 else if (ureg < 32+64) { regClassID = FloatRegClassID; return ureg-32; }
431 else if (ureg < 4 +96) { regClassID = FloatCCRegClassID; return ureg-96; }
432 else if (ureg < 1 +100) { regClassID = IntCCRegClassID; return ureg-100;}
433 else if (ureg == InvalidRegNum) { return InvalidRegNum; }
434 else { assert(0 && "Invalid unified register number"); }
438 // Returns the assembly-language name of the specified machine register.
440 virtual const char * const getUnifiedRegName(int reg) const;
443 // returns the # of bytes of stack space allocated for each register
444 // type. For Sparc, currently we allocate 8 bytes on stack for all
445 // register types. We can optimize this later if necessary to save stack
446 // space (However, should make sure that stack alignment is correct)
448 inline int getSpilledRegSize(int RegType) const {
453 // To obtain the return value and the indirect call address (if any)
454 // contained in a CALL machine instruction
456 const Value * getCallInstRetVal(const MachineInstr *CallMI) const;
457 const Value * getCallInstIndirectAddrVal(const MachineInstr *CallMI) const;
459 // The following methods are used to generate "copy" machine instructions
460 // for an architecture.
462 // The function regTypeNeedsScratchReg() can be used to check whether a
463 // scratch register is needed to copy a register of type `regType' to
464 // or from memory. If so, such a scratch register can be provided by
465 // the caller (e.g., if it knows which regsiters are free); otherwise
466 // an arbitrary one will be chosen and spilled by the copy instructions.
468 bool regTypeNeedsScratchReg(int RegType,
469 int& scratchRegClassId) const;
471 void cpReg2RegMI(std::vector<MachineInstr*>& mvec,
472 unsigned SrcReg, unsigned DestReg,
475 void cpReg2MemMI(std::vector<MachineInstr*>& mvec,
476 unsigned SrcReg, unsigned DestPtrReg,
477 int Offset, int RegType, int scratchReg = -1) const;
479 void cpMem2RegMI(std::vector<MachineInstr*>& mvec,
480 unsigned SrcPtrReg, int Offset, unsigned DestReg,
481 int RegType, int scratchReg = -1) const;
483 void cpValue2Value(Value *Src, Value *Dest,
484 std::vector<MachineInstr*>& mvec) const;
486 // To see whether a register is a volatile (i.e., whehter it must be
487 // preserved acorss calls)
489 inline bool isRegVolatile(int RegClassID, int Reg) const {
490 return MachineRegClassArr[RegClassID]->isRegVolatile(Reg);
494 virtual unsigned getFramePointer() const;
495 virtual unsigned getStackPointer() const;
497 virtual int getInvalidRegNum() const {
498 return InvalidRegNum;
501 // This method inserts the caller saving code for call instructions
503 void insertCallerSavingCode(std::vector<MachineInstr*>& instrnsBefore,
504 std::vector<MachineInstr*>& instrnsAfter,
506 const BasicBlock *BB, PhyRegAlloc &PRA ) const;
512 //---------------------------------------------------------------------------
513 // class UltraSparcSchedInfo
516 // Interface to instruction scheduling information for UltraSPARC.
517 // The parameter values above are based on UltraSPARC IIi.
518 //---------------------------------------------------------------------------
521 class UltraSparcSchedInfo: public MachineSchedInfo {
523 UltraSparcSchedInfo(const TargetMachine &tgt);
525 virtual void initializeResources();
529 //---------------------------------------------------------------------------
530 // class UltraSparcFrameInfo
533 // Interface to stack frame layout info for the UltraSPARC.
534 // Starting offsets for each area of the stack frame are aligned at
535 // a multiple of getStackFrameSizeAlignment().
536 //---------------------------------------------------------------------------
538 class UltraSparcFrameInfo: public MachineFrameInfo {
540 UltraSparcFrameInfo(const TargetMachine &tgt) : MachineFrameInfo(tgt) {}
543 // These methods provide constant parameters of the frame layout.
545 int getStackFrameSizeAlignment() const { return StackFrameSizeAlignment;}
546 int getMinStackFrameSize() const { return MinStackFrameSize; }
547 int getNumFixedOutgoingArgs() const { return NumFixedOutgoingArgs; }
548 int getSizeOfEachArgOnStack() const { return SizeOfEachArgOnStack; }
549 bool argsOnStackHaveFixedSize() const { return true; }
551 // This method adjusts a stack offset to meet alignment rules of target.
552 // The fixed OFFSET (0x7ff) must be subtracted and the result aligned.
553 virtual int adjustAlignment (int unalignedOffset,
555 unsigned int align) const {
556 return unalignedOffset + (growUp? +1:-1)*((unalignedOffset-OFFSET) % align);
559 // These methods compute offsets using the frame contents for a
560 // particular function. The frame contents are obtained from the
561 // MachineCodeInfoForMethod object for the given function.
563 int getFirstIncomingArgOffset (MachineCodeForMethod& mcInfo,
566 growUp = true; // arguments area grows upwards
567 return FirstIncomingArgOffsetFromFP;
569 int getFirstOutgoingArgOffset (MachineCodeForMethod& mcInfo,
572 growUp = true; // arguments area grows upwards
573 return FirstOutgoingArgOffsetFromSP;
575 int getFirstOptionalOutgoingArgOffset(MachineCodeForMethod& mcInfo,
578 growUp = true; // arguments area grows upwards
579 return FirstOptionalOutgoingArgOffsetFromSP;
582 int getFirstAutomaticVarOffset (MachineCodeForMethod& mcInfo,
584 int getRegSpillAreaOffset (MachineCodeForMethod& mcInfo,
586 int getTmpAreaOffset (MachineCodeForMethod& mcInfo,
588 int getDynamicAreaOffset (MachineCodeForMethod& mcInfo,
592 // These methods specify the base register used for each stack area
593 // (generally FP or SP)
595 virtual int getIncomingArgBaseRegNum() const {
596 return (int) target.getRegInfo().getFramePointer();
598 virtual int getOutgoingArgBaseRegNum() const {
599 return (int) target.getRegInfo().getStackPointer();
601 virtual int getOptionalOutgoingArgBaseRegNum() const {
602 return (int) target.getRegInfo().getStackPointer();
604 virtual int getAutomaticVarBaseRegNum() const {
605 return (int) target.getRegInfo().getFramePointer();
607 virtual int getRegSpillAreaBaseRegNum() const {
608 return (int) target.getRegInfo().getFramePointer();
610 virtual int getDynamicAreaBaseRegNum() const {
611 return (int) target.getRegInfo().getStackPointer();
615 /*----------------------------------------------------------------------
616 This diagram shows the stack frame layout used by llc on Sparc V9.
617 Note that only the location of automatic variables, spill area,
618 temporary storage, and dynamically allocated stack area are chosen
619 by us. The rest conform to the Sparc V9 ABI.
620 All stack addresses are offset by OFFSET = 0x7ff (2047).
622 Alignment assumpteions and other invariants:
623 (1) %sp+OFFSET and %fp+OFFSET are always aligned on 16-byte boundary
624 (2) Variables in automatic, spill, temporary, or dynamic regions
625 are aligned according to their size as in all memory accesses.
626 (3) Everything below the dynamically allocated stack area is only used
627 during a call to another function, so it is never needed when
628 the current function is active. This is why space can be allocated
629 dynamically by incrementing %sp any time within the function.
634 %fp+OFFSET+176 Optional extra incoming arguments# 1..N
635 %fp+OFFSET+168 Incoming argument #6
637 %fp+OFFSET+128 Incoming argument #1
639 ---%fp+OFFSET-0--------Bottom of caller's stack frame--------------------
640 %fp+OFFSET-8 Automatic variables <-- ****TOP OF STACK FRAME****
645 %sp+OFFSET+176+8N Bottom of dynamically allocated stack area
646 %sp+OFFSET+168+8N Optional extra outgoing argument# N
648 %sp+OFFSET+176 Optional extra outgoing argument# 1
649 %sp+OFFSET+168 Outgoing argument #6
651 %sp+OFFSET+128 Outgoing argument #1
652 %sp+OFFSET+120 Save area for %i7
654 %sp+OFFSET+0 Save area for %l0 <-- ****BOTTOM OF STACK FRAME****
656 *----------------------------------------------------------------------*/
658 // All stack addresses must be offset by 0x7ff (2047) on Sparc V9.
659 static const int OFFSET = (int) 0x7ff;
660 static const int StackFrameSizeAlignment = 16;
661 static const int MinStackFrameSize = 176;
662 static const int NumFixedOutgoingArgs = 6;
663 static const int SizeOfEachArgOnStack = 8;
664 static const int FirstIncomingArgOffsetFromFP = 128 + OFFSET;
665 static const int FirstOptionalIncomingArgOffsetFromFP = 176 + OFFSET;
666 static const int StaticAreaOffsetFromFP = 0 + OFFSET;
667 static const int FirstOutgoingArgOffsetFromSP = 128 + OFFSET;
668 static const int FirstOptionalOutgoingArgOffsetFromSP = 176 + OFFSET;
672 //---------------------------------------------------------------------------
673 // class UltraSparcCacheInfo
676 // Interface to cache parameters for the UltraSPARC.
677 // Just use defaults for now.
678 //---------------------------------------------------------------------------
680 class UltraSparcCacheInfo: public MachineCacheInfo {
682 UltraSparcCacheInfo(const TargetMachine &T) : MachineCacheInfo(T) {}
686 //---------------------------------------------------------------------------
687 // class UltraSparcOptInfo
690 // Interface to machine-level optimization routines for the UltraSPARC.
691 //---------------------------------------------------------------------------
693 class UltraSparcOptInfo: public MachineOptInfo {
695 UltraSparcOptInfo(const TargetMachine &T) : MachineOptInfo(T) {}
697 virtual bool IsUselessCopy (const MachineInstr* MI) const;
701 //---------------------------------------------------------------------------
702 // class UltraSparcMachine
705 // Primary interface to machine description for the UltraSPARC.
706 // Primarily just initializes machine-dependent parameters in
707 // class TargetMachine, and creates machine-dependent subclasses
708 // for classes such as InstrInfo, SchedInfo and RegInfo.
709 //---------------------------------------------------------------------------
711 class UltraSparc : public TargetMachine {
713 UltraSparcInstrInfo instrInfo;
714 UltraSparcSchedInfo schedInfo;
715 UltraSparcRegInfo regInfo;
716 UltraSparcFrameInfo frameInfo;
717 UltraSparcCacheInfo cacheInfo;
718 UltraSparcOptInfo optInfo;
722 virtual const MachineInstrInfo &getInstrInfo() const { return instrInfo; }
723 virtual const MachineSchedInfo &getSchedInfo() const { return schedInfo; }
724 virtual const MachineRegInfo &getRegInfo() const { return regInfo; }
725 virtual const MachineFrameInfo &getFrameInfo() const { return frameInfo; }
726 virtual const MachineCacheInfo &getCacheInfo() const { return cacheInfo; }
727 virtual const MachineOptInfo &getOptInfo() const { return optInfo; }
729 // getPrologEpilogCodeInserter - Inserts prolog/epilog code.
730 virtual Pass* getPrologEpilogInsertionPass();
732 // getFunctionAsmPrinterPass - Writes out machine code for a single function
733 virtual Pass* getFunctionAsmPrinterPass(std::ostream &Out);
735 // getModuleAsmPrinterPass - Writes generated machine code to assembly file.
736 virtual Pass* getModuleAsmPrinterPass(std::ostream &Out);
738 // getEmitBytecodeToAsmPass - Emits final LLVM bytecode to assembly file.
739 virtual Pass* getEmitBytecodeToAsmPass(std::ostream &Out);