1 //===-- SparcInternals.h - Header file for Sparc backend ---------*- C++ -*--=//
3 // This file defines stuff that is to be private to the Sparc backend, but is
4 // shared among different portions of the backend.
6 //===----------------------------------------------------------------------===//
8 #ifndef SPARC_INTERNALS_H
9 #define SPARC_INTERNALS_H
12 #include "SparcRegClassInfo.h"
13 #include "llvm/Target/TargetMachine.h"
14 #include "llvm/Target/MachineInstrInfo.h"
16 #include "llvm/Target/MachineSchedInfo.h"
17 #include "llvm/CodeGen/RegClass.h"
18 #include "llvm/Type.h"
20 #include <sys/types.h>
24 // OpCodeMask definitions for the Sparc V9
26 const OpCodeMask Immed = 0x00002000; // immed or reg operand?
27 const OpCodeMask Annul = 0x20000000; // annul delay instr?
28 const OpCodeMask PredictTaken = 0x00080000; // predict branch taken?
31 enum SparcInstrSchedClass {
32 SPARC_NONE, /* Instructions with no scheduling restrictions */
33 SPARC_IEUN, /* Integer class that can use IEU0 or IEU1 */
34 SPARC_IEU0, /* Integer class IEU0 */
35 SPARC_IEU1, /* Integer class IEU1 */
36 SPARC_FPM, /* FP Multiply or Divide instructions */
37 SPARC_FPA, /* All other FP instructions */
38 SPARC_CTI, /* Control-transfer instructions */
39 SPARC_LD, /* Load instructions */
40 SPARC_ST, /* Store instructions */
41 SPARC_SINGLE, /* Instructions that must issue by themselves */
43 SPARC_INV, /* This should stay at the end for the next value */
44 SPARC_NUM_SCHED_CLASSES = SPARC_INV
48 //---------------------------------------------------------------------------
49 // enum SparcMachineOpCode.
50 // const MachineInstrDescriptor SparcMachineInstrDesc[]
53 // Description of UltraSparc machine instructions.
55 //---------------------------------------------------------------------------
57 enum SparcMachineOpCode {
58 #define I(ENUM, OPCODESTRING, NUMOPERANDS, RESULTPOS, MAXIMM, IMMSE, \
59 NUMDELAYSLOTS, LATENCY, SCHEDCLASS, INSTFLAGS) \
61 #include "SparcInstr.def"
63 // End-of-array marker
65 NUM_REAL_OPCODES = RETURN+1, // number of valid opcodes
66 NUM_TOTAL_OPCODES = INVALID_OPCODE
70 // Array of machine instruction descriptions...
71 extern const MachineInstrDescriptor SparcMachineInstrDesc[];
74 //---------------------------------------------------------------------------
75 // class UltraSparcInstrInfo
78 // Information about individual instructions.
79 // Most information is stored in the SparcMachineInstrDesc array above.
80 // Other information is computed on demand, and most such functions
81 // default to member functions in base class MachineInstrInfo.
82 //---------------------------------------------------------------------------
84 class UltraSparcInstrInfo : public MachineInstrInfo {
86 /*ctor*/ UltraSparcInstrInfo();
88 virtual bool hasResultInterlock (MachineOpCode opCode)
90 // All UltraSPARC instructions have interlocks (note that delay slots
91 // are not considered here).
92 // However, instructions that use the result of an FCMP produce a
93 // 9-cycle stall if they are issued less than 3 cycles after the FCMP.
94 // Force the compiler to insert a software interlock (i.e., gap of
95 // 2 other groups, including NOPs if necessary).
96 return (opCode == FCMPS || opCode == FCMPD || opCode == FCMPQ);
112 class UltraSparcRegInfo : public MachineRegInfo
117 // The actual register classes in the Sparc
127 // Type of registers available in Sparc. There can be several reg types
128 // in the same class. For instace, the float reg class has Single/Double
139 // WARNING: If the above enum order must be changed, also modify
140 // getRegisterClassOfValue method below since it assumes this particular
141 // order for efficiency.
144 // reverse pointer to get info about the ultra sparc machine
145 const UltraSparc *const UltraSparcInfo;
147 // Both int and float rguments can be passed in 6 int regs -
148 // %o0 to %o5 (cannot be changed)
149 unsigned const NumOfIntArgRegs;
150 unsigned const NumOfFloatArgRegs;
151 unsigned const InvalidRegNum;
153 //void setCallArgColor(LiveRange *const LR, const unsigned RegNo) const;
155 void setCallOrRetArgCol(LiveRange *const LR, const unsigned RegNo,
156 const MachineInstr *MI,AddedInstrMapType &AIMap)const;
158 MachineInstr * getCopy2RegMI(const Value *SrcVal, const unsigned Reg,
159 unsigned RegClassID) const ;
161 Value *getValue4ReturnAddr( const MachineInstr * MInst ) const ;
163 int getRegType(const LiveRange *const LR) const {
167 switch( (LR->getRegClass())->getID() ) {
169 case IntRegClassID: return IntRegType;
171 case FloatRegClassID:
172 Typ = LR->getTypeID();
173 if( Typ == Type::FloatTyID )
174 return FPSingleRegType;
175 else if( Typ == Type::DoubleTyID )
176 return FPDoubleRegType;
177 else assert(0 && "Unknown type in FloatRegClass");
179 case IntCCRegClassID: return IntCCRegType;
181 case FloatCCRegClassID: return FloatCCRegType ;
183 default: assert( 0 && "Unknown reg class ID");
189 int getRegType(const Value *const Val) const {
193 switch( getRegClassIDOfValue(Val) ) {
195 case IntRegClassID: return IntRegType;
197 case FloatRegClassID:
198 Typ = (Val->getType())->getPrimitiveID();
199 if( Typ == Type::FloatTyID )
200 return FPSingleRegType;
201 else if( Typ == Type::DoubleTyID )
202 return FPDoubleRegType;
203 else assert(0 && "Unknown type in FloatRegClass");
205 case IntCCRegClassID: return IntCCRegType;
207 case FloatCCRegClassID: return FloatCCRegType ;
209 default: assert( 0 && "Unknown reg class ID");
218 MachineInstr * cpReg2RegMI(const unsigned SrcReg, const unsigned DestReg,
219 const int RegType) const;
221 MachineInstr * cpValue2RegMI(Value * Val, const unsigned DestReg,
222 const int RegType) const;
228 UltraSparcRegInfo(const UltraSparc *const USI ) : UltraSparcInfo(USI),
230 NumOfFloatArgRegs(32),
233 MachineRegClassArr.push_back( new SparcIntRegClass(IntRegClassID) );
234 MachineRegClassArr.push_back( new SparcFloatRegClass(FloatRegClassID) );
235 MachineRegClassArr.push_back( new SparcIntCCRegClass(IntCCRegClassID) );
236 MachineRegClassArr.push_back( new SparcFloatCCRegClass(FloatCCRegClassID));
238 assert( SparcFloatRegOrder::StartOfNonVolatileRegs == 32 &&
239 "32 Float regs are used for float arg passing");
243 ~UltraSparcRegInfo(void) { } // empty destructor
246 inline const UltraSparc & getUltraSparcInfo() const {
247 return *UltraSparcInfo;
252 inline unsigned getRegClassIDOfValue (const Value *const Val,
253 bool isCCReg = false) const {
255 Type::PrimitiveID ty = (Val->getType())->getPrimitiveID();
259 if( (ty && ty <= Type::LongTyID) || (ty == Type::LabelTyID) ||
260 (ty == Type::MethodTyID) || (ty == Type::PointerTyID) )
261 res = IntRegClassID; // sparc int reg (ty=0: void)
262 else if( ty <= Type::DoubleTyID)
263 res = FloatRegClassID; // sparc float reg class
265 cout << "TypeID: " << ty << endl;
266 assert(0 && "Cannot resolve register class for type");
271 return res + 2; // corresponidng condition code regiser
278 // returns the register tha contains always zero
279 // this is the unified register number
280 inline int getZeroRegNum() const { return SparcIntRegOrder::g0; }
282 // returns the reg used for pushing the address when a method is called.
283 // This can be used for other purposes between calls
284 unsigned getCallAddressReg() const { return SparcIntRegOrder::o7; }
287 // and when we return from a method. It should be made sure that this
288 // register contains the return value when a return instruction is reached.
289 unsigned getReturnAddressReg() const { return SparcIntRegOrder::i7; }
291 void suggestRegs4MethodArgs(const Method *const Meth,
292 LiveRangeInfo& LRI) const;
294 void suggestRegs4CallArgs(const CallInst *const CallI,
295 LiveRangeInfo& LRI, vector<RegClass *> RCL) const;
297 void suggestReg4RetValue(const ReturnInst *const RetI,
298 LiveRangeInfo& LRI) const;
301 void colorMethodArgs(const Method *const Meth, LiveRangeInfo& LRI,
302 AddedInstrns *const FirstAI) const;
304 void colorCallArgs(const CallInst *const CallI, LiveRangeInfo& LRI,
305 AddedInstrns *const CallAI) const;
307 void colorRetValue(const ReturnInst *const RetI, LiveRangeInfo& LRI,
308 AddedInstrns *const RetAI) const;
311 bool handleSpecialMInstr(const MachineInstr * MInst,
312 LiveRangeInfo& LRI, vector<RegClass *> RCL) const;
315 static void printReg(const LiveRange *const LR) ;
317 // this method provides a unique number for each register
318 inline int getUnifiedRegNum(int RegClassID, int reg) const {
320 if( RegClassID == IntRegClassID && reg < 32 )
322 else if ( RegClassID == FloatRegClassID && reg < 64)
323 return reg + 32; // we have 32 int regs
324 else if( RegClassID == FloatCCRegClassID && reg < 4)
325 return reg + 32 + 64; // 32 int, 64 float
326 else if( RegClassID == IntCCRegClassID )
327 return 4+ 32 + 64; // only int cc reg
328 else if (reg==1000) //****** TODO: Remove
331 assert(0 && "Invalid register class or reg number");
335 // given the unified register number, this gives the name
336 inline const string getUnifiedRegName(int reg) const {
338 return SparcIntRegOrder::getRegName(reg);
339 else if ( reg < (64 + 32) )
340 return SparcFloatRegOrder::getRegName( reg - 32);
341 else if( reg < (64+32+4) )
342 return SparcFloatCCRegOrder::getRegName( reg -32 - 64);
343 else if ( reg == 64+32+4)
344 return "xcc"; // only integer cc reg
346 else if (reg==1000) //****** TODO: Remove
349 assert(0 && "Invalid register number");
357 /*---------------------------------------------------------------------------
358 Scheduling guidelines for SPARC IIi:
360 I-Cache alignment rules (pg 326)
361 -- Align a branch target instruction so that it's entire group is within
362 the same cache line (may be 1-4 instructions).
363 ** Don't let a branch that is predicted taken be the last instruction
364 on an I-cache line: delay slot will need an entire line to be fetched
365 -- Make a FP instruction or a branch be the 4th instruction in a group.
366 For branches, there are tradeoffs in reordering to make this happen
368 ** Don't put a branch in a group that crosses a 32-byte boundary!
369 An artificial branch is inserted after every 32 bytes, and having
370 another branch will force the group to be broken into 2 groups.
373 -- Don't let a loop span two memory pages, if possible
375 Branch prediction performance:
376 -- Don't make the branch in a delay slot the target of a branch
377 -- Try not to have 2 predicted branches within a group of 4 instructions
378 (because each such group has a single branch target field).
379 -- Try to align branches in slots 0, 2, 4 or 6 of a cache line (to avoid
380 the wrong prediction bits being used in some cases).
382 D-Cache timing constraints:
383 -- Signed int loads of less than 64 bits have 3 cycle latency, not 2
384 -- All other loads that hit in D-Cache have 2 cycle latency
385 -- All loads are returned IN ORDER, so a D-Cache miss will delay a later hit
386 -- Mis-aligned loads or stores cause a trap. In particular, replace
387 mis-aligned FP double precision l/s with 2 single-precision l/s.
388 -- Simulations of integer codes show increase in avg. group size of
389 33% when code (including esp. non-faulting loads) is moved across
390 one branch, and 50% across 2 branches.
392 E-Cache timing constraints:
393 -- Scheduling for E-cache (D-Cache misses) is effective (due to load buffering)
395 Store buffer timing constraints:
396 -- Stores can be executed in same cycle as instruction producing the value
397 -- Stores are buffered and have lower priority for E-cache until
398 highwater mark is reached in the store buffer (5 stores)
400 Pipeline constraints:
401 -- Shifts can only use IEU0.
402 -- CC setting instructions can only use IEU1.
403 -- Several other instructions must only use IEU1:
404 EDGE(?), ARRAY(?), CALL, JMPL, BPr, PST, and FCMP.
405 -- Two instructions cannot store to the same register file in a single cycle
406 (single write port per file).
408 Issue and grouping constraints:
409 -- FP and branch instructions must use slot 4.
410 -- Shift instructions cannot be grouped with other IEU0-specific instructions.
411 -- CC setting instructions cannot be grouped with other IEU1-specific instrs.
412 -- Several instructions must be issued in a single-instruction group:
413 MOVcc or MOVr, MULs/x and DIVs/x, SAVE/RESTORE, many others
414 -- A CALL or JMPL breaks a group, ie, is not combined with subsequent instrs.
418 Branch delay slot scheduling rules:
419 -- A CTI couple (two back-to-back CTI instructions in the dynamic stream)
420 has a 9-instruction penalty: the entire pipeline is flushed when the
421 second instruction reaches stage 9 (W-Writeback).
422 -- Avoid putting multicycle instructions, and instructions that may cause
423 load misses, in the delay slot of an annulling branch.
424 -- Avoid putting WR, SAVE..., RESTORE and RETURN instructions in the
425 delay slot of an annulling branch.
427 *--------------------------------------------------------------------------- */
429 //---------------------------------------------------------------------------
430 // List of CPUResources for UltraSPARC IIi.
431 //---------------------------------------------------------------------------
433 const CPUResource AllIssueSlots( "All Instr Slots", 4);
434 const CPUResource IntIssueSlots( "Int Instr Slots", 3);
435 const CPUResource First3IssueSlots("Instr Slots 0-3", 3);
436 const CPUResource LSIssueSlots( "Load-Store Instr Slot", 1);
437 const CPUResource CTIIssueSlots( "Ctrl Transfer Instr Slot", 1);
438 const CPUResource FPAIssueSlots( "Int Instr Slot 1", 1);
439 const CPUResource FPMIssueSlots( "Int Instr Slot 1", 1);
441 // IEUN instructions can use either Alu and should use IAluN.
442 // IEU0 instructions must use Alu 1 and should use both IAluN and IAlu0.
443 // IEU1 instructions must use Alu 2 and should use both IAluN and IAlu1.
444 const CPUResource IAluN("Int ALU 1or2", 2);
445 const CPUResource IAlu0("Int ALU 1", 1);
446 const CPUResource IAlu1("Int ALU 2", 1);
448 const CPUResource LSAluC1("Load/Store Unit Addr Cycle", 1);
449 const CPUResource LSAluC2("Load/Store Unit Issue Cycle", 1);
450 const CPUResource LdReturn("Load Return Unit", 1);
452 const CPUResource FPMAluC1("FP Mul/Div Alu Cycle 1", 1);
453 const CPUResource FPMAluC2("FP Mul/Div Alu Cycle 2", 1);
454 const CPUResource FPMAluC3("FP Mul/Div Alu Cycle 3", 1);
456 const CPUResource FPAAluC1("FP Other Alu Cycle 1", 1);
457 const CPUResource FPAAluC2("FP Other Alu Cycle 2", 1);
458 const CPUResource FPAAluC3("FP Other Alu Cycle 3", 1);
460 const CPUResource IRegReadPorts("Int Reg ReadPorts", INT_MAX); // CHECK
461 const CPUResource IRegWritePorts("Int Reg WritePorts", 2); // CHECK
462 const CPUResource FPRegReadPorts("FP Reg Read Ports", INT_MAX); // CHECK
463 const CPUResource FPRegWritePorts("FP Reg Write Ports", 1); // CHECK
465 const CPUResource CTIDelayCycle( "CTI delay cycle", 1);
466 const CPUResource FCMPDelayCycle("FCMP delay cycle", 1);
469 //---------------------------------------------------------------------------
470 // const InstrClassRUsage SparcRUsageDesc[]
473 // Resource usage information for instruction in each scheduling class.
474 // The InstrRUsage Objects for individual classes are specified first.
475 // Note that fetch and decode are decoupled from the execution pipelines
476 // via an instr buffer, so they are not included in the cycles below.
477 //---------------------------------------------------------------------------
479 const InstrClassRUsage NoneClassRUsage = {
484 /* isSingleIssue */ false,
485 /* breaksGroup */ false,
489 /* feasibleSlots[] */ { 0, 1, 2, 3 },
503 const InstrClassRUsage IEUNClassRUsage = {
508 /* isSingleIssue */ false,
509 /* breaksGroup */ false,
513 /* feasibleSlots[] */ { 0, 1, 2 },
517 /*Cycle G */ { AllIssueSlots.rid, 0, 1 },
518 { IntIssueSlots.rid, 0, 1 },
519 /*Cycle E */ { IAluN.rid, 1, 1 },
524 /*Cycle W */ { IRegWritePorts.rid, 6, 1 }
528 const InstrClassRUsage IEU0ClassRUsage = {
533 /* isSingleIssue */ false,
534 /* breaksGroup */ false,
538 /* feasibleSlots[] */ { 0, 1, 2 },
542 /*Cycle G */ { AllIssueSlots.rid, 0, 1 },
543 { IntIssueSlots.rid, 0, 1 },
544 /*Cycle E */ { IAluN.rid, 1, 1 },
550 /*Cycle W */ { IRegWritePorts.rid, 6, 1 }
554 const InstrClassRUsage IEU1ClassRUsage = {
559 /* isSingleIssue */ false,
560 /* breaksGroup */ false,
564 /* feasibleSlots[] */ { 0, 1, 2 },
568 /*Cycle G */ { AllIssueSlots.rid, 0, 1 },
569 { IntIssueSlots.rid, 0, 1 },
570 /*Cycle E */ { IAluN.rid, 1, 1 },
576 /*Cycle W */ { IRegWritePorts.rid, 6, 1 }
580 const InstrClassRUsage FPMClassRUsage = {
585 /* isSingleIssue */ false,
586 /* breaksGroup */ false,
590 /* feasibleSlots[] */ { 0, 1, 2, 3 },
594 /*Cycle G */ { AllIssueSlots.rid, 0, 1 },
595 { FPMIssueSlots.rid, 0, 1 },
596 /*Cycle E */ { FPRegReadPorts.rid, 1, 1 },
597 /*Cycle C */ { FPMAluC1.rid, 2, 1 },
598 /*Cycle N1*/ { FPMAluC2.rid, 3, 1 },
599 /*Cycle N1*/ { FPMAluC3.rid, 4, 1 },
601 /*Cycle W */ { FPRegWritePorts.rid, 6, 1 }
605 const InstrClassRUsage FPAClassRUsage = {
610 /* isSingleIssue */ false,
611 /* breaksGroup */ false,
615 /* feasibleSlots[] */ { 0, 1, 2, 3 },
619 /*Cycle G */ { AllIssueSlots.rid, 0, 1 },
620 { FPAIssueSlots.rid, 0, 1 },
621 /*Cycle E */ { FPRegReadPorts.rid, 1, 1 },
622 /*Cycle C */ { FPAAluC1.rid, 2, 1 },
623 /*Cycle N1*/ { FPAAluC2.rid, 3, 1 },
624 /*Cycle N1*/ { FPAAluC3.rid, 4, 1 },
626 /*Cycle W */ { FPRegWritePorts.rid, 6, 1 }
630 const InstrClassRUsage LDClassRUsage = {
635 /* isSingleIssue */ false,
636 /* breaksGroup */ false,
640 /* feasibleSlots[] */ { 0, 1, 2, },
644 /*Cycle G */ { AllIssueSlots.rid, 0, 1 },
645 { First3IssueSlots.rid, 0, 1 },
646 { LSIssueSlots.rid, 0, 1 },
647 /*Cycle E */ { LSAluC1.rid, 1, 1 },
648 /*Cycle C */ { LSAluC2.rid, 2, 1 },
649 { LdReturn.rid, 2, 1 },
653 /*Cycle W */ { IRegWritePorts.rid, 6, 1 }
657 const InstrClassRUsage STClassRUsage = {
662 /* isSingleIssue */ false,
663 /* breaksGroup */ false,
667 /* feasibleSlots[] */ { 0, 1, 2 },
671 /*Cycle G */ { AllIssueSlots.rid, 0, 1 },
672 { First3IssueSlots.rid, 0, 1 },
673 { LSIssueSlots.rid, 0, 1 },
674 /*Cycle E */ { LSAluC1.rid, 1, 1 },
675 /*Cycle C */ { LSAluC2.rid, 2, 1 }
683 const InstrClassRUsage CTIClassRUsage = {
688 /* isSingleIssue */ false,
689 /* breaksGroup */ false,
693 /* feasibleSlots[] */ { 0, 1, 2, 3 },
697 /*Cycle G */ { AllIssueSlots.rid, 0, 1 },
698 { CTIIssueSlots.rid, 0, 1 },
699 /*Cycle E */ { IAlu0.rid, 1, 1 },
700 /*Cycles E-C */ { CTIDelayCycle.rid, 1, 2 }
709 const InstrClassRUsage SingleClassRUsage = {
714 /* isSingleIssue */ true,
715 /* breaksGroup */ false,
719 /* feasibleSlots[] */ { 0 },
723 /*Cycle G */ { AllIssueSlots.rid, 0, 1 },
724 { AllIssueSlots.rid, 0, 1 },
725 { AllIssueSlots.rid, 0, 1 },
726 { AllIssueSlots.rid, 0, 1 },
727 /*Cycle E */ { IAlu0.rid, 1, 1 }
737 const InstrClassRUsage SparcRUsageDesc[] = {
751 //---------------------------------------------------------------------------
752 // const InstrIssueDelta SparcInstrIssueDeltas[]
755 // Changes to issue restrictions information in InstrClassRUsage for
756 // instructions that differ from other instructions in their class.
757 //---------------------------------------------------------------------------
759 const InstrIssueDelta SparcInstrIssueDeltas[] = {
761 // opCode, isSingleIssue, breaksGroup, numBubbles
763 // Special cases for single-issue only
764 // Other single issue cases are below.
765 //{ LDDA, true, true, 0 },
766 //{ STDA, true, true, 0 },
767 //{ LDDF, true, true, 0 },
768 //{ LDDFA, true, true, 0 },
769 { ADDC, true, true, 0 },
770 { ADDCcc, true, true, 0 },
771 { SUBC, true, true, 0 },
772 { SUBCcc, true, true, 0 },
773 //{ SAVE, true, true, 0 },
774 //{ RESTORE, true, true, 0 },
775 //{ LDSTUB, true, true, 0 },
776 //{ SWAP, true, true, 0 },
777 //{ SWAPA, true, true, 0 },
778 //{ CAS, true, true, 0 },
779 //{ CASA, true, true, 0 },
780 //{ CASX, true, true, 0 },
781 //{ CASXA, true, true, 0 },
782 //{ LDFSR, true, true, 0 },
783 //{ LDFSRA, true, true, 0 },
784 //{ LDXFSR, true, true, 0 },
785 //{ LDXFSRA, true, true, 0 },
786 //{ STFSR, true, true, 0 },
787 //{ STFSRA, true, true, 0 },
788 //{ STXFSR, true, true, 0 },
789 //{ STXFSRA, true, true, 0 },
790 //{ SAVED, true, true, 0 },
791 //{ RESTORED, true, true, 0 },
792 //{ FLUSH, true, true, 9 },
793 //{ FLUSHW, true, true, 9 },
794 //{ ALIGNADDR, true, true, 0 },
795 { RETURN, true, true, 0 },
796 //{ DONE, true, true, 0 },
797 //{ RETRY, true, true, 0 },
798 //{ WR, true, true, 0 },
799 //{ WRPR, true, true, 4 },
800 //{ RD, true, true, 0 },
801 //{ RDPR, true, true, 0 },
802 //{ TCC, true, true, 0 },
803 //{ SHUTDOWN, true, true, 0 },
805 // Special cases for breaking group *before*
806 // CURRENTLY NOT SUPPORTED!
807 { CALL, false, false, 0 },
808 { JMPL, false, false, 0 },
810 // Special cases for breaking the group *after*
811 { MULX, true, true, (4+34)/2 },
812 { FDIVS, false, true, 0 },
813 { FDIVD, false, true, 0 },
814 { FDIVQ, false, true, 0 },
815 { FSQRTS, false, true, 0 },
816 { FSQRTD, false, true, 0 },
817 { FSQRTQ, false, true, 0 },
818 //{ FCMP{LE,GT,NE,EQ}, false, true, 0 },
820 // Instructions that introduce bubbles
821 //{ MULScc, true, true, 2 },
822 //{ SMULcc, true, true, (4+18)/2 },
823 //{ UMULcc, true, true, (4+19)/2 },
824 { SDIVX, true, true, 68 },
825 { UDIVX, true, true, 68 },
826 //{ SDIVcc, true, true, 36 },
827 //{ UDIVcc, true, true, 37 },
828 //{ WR, false, false, 4 },
829 //{ WRPR, false, false, 4 },
833 //---------------------------------------------------------------------------
834 // const InstrRUsageDelta SparcInstrUsageDeltas[]
837 // Changes to resource usage information in InstrClassRUsage for
838 // instructions that differ from other instructions in their class.
839 //---------------------------------------------------------------------------
841 const InstrRUsageDelta SparcInstrUsageDeltas[] = {
843 // MachineOpCode, Resource, Start cycle, Num cycles
846 // JMPL counts as a load/store instruction for issue!
848 { JMPL, LSIssueSlots.rid, 0, 1 },
851 // Many instructions cannot issue for the next 2 cycles after an FCMP
852 // We model that with a fake resource FCMPDelayCycle.
854 { FCMPS, FCMPDelayCycle.rid, 1, 3 },
855 { FCMPD, FCMPDelayCycle.rid, 1, 3 },
856 { FCMPQ, FCMPDelayCycle.rid, 1, 3 },
858 { MULX, FCMPDelayCycle.rid, 1, 1 },
859 { SDIVX, FCMPDelayCycle.rid, 1, 1 },
860 { UDIVX, FCMPDelayCycle.rid, 1, 1 },
861 //{ SMULcc, FCMPDelayCycle.rid, 1, 1 },
862 //{ UMULcc, FCMPDelayCycle.rid, 1, 1 },
863 //{ SDIVcc, FCMPDelayCycle.rid, 1, 1 },
864 //{ UDIVcc, FCMPDelayCycle.rid, 1, 1 },
865 { STD, FCMPDelayCycle.rid, 1, 1 },
866 { FMOVRSZ, FCMPDelayCycle.rid, 1, 1 },
867 { FMOVRSLEZ,FCMPDelayCycle.rid, 1, 1 },
868 { FMOVRSLZ, FCMPDelayCycle.rid, 1, 1 },
869 { FMOVRSNZ, FCMPDelayCycle.rid, 1, 1 },
870 { FMOVRSGZ, FCMPDelayCycle.rid, 1, 1 },
871 { FMOVRSGEZ,FCMPDelayCycle.rid, 1, 1 },
874 // Some instructions are stalled in the GROUP stage if a CTI is in
877 { LDD, CTIDelayCycle.rid, 1, 1 },
878 //{ LDDA, CTIDelayCycle.rid, 1, 1 },
879 //{ LDDSTUB, CTIDelayCycle.rid, 1, 1 },
880 //{ LDDSTUBA, CTIDelayCycle.rid, 1, 1 },
881 //{ SWAP, CTIDelayCycle.rid, 1, 1 },
882 //{ SWAPA, CTIDelayCycle.rid, 1, 1 },
883 //{ CAS, CTIDelayCycle.rid, 1, 1 },
884 //{ CASA, CTIDelayCycle.rid, 1, 1 },
885 //{ CASX, CTIDelayCycle.rid, 1, 1 },
886 //{ CASXA, CTIDelayCycle.rid, 1, 1 },
889 // Signed int loads of less than dword size return data in cycle N1 (not C)
890 // and put all loads in consecutive cycles into delayed load return mode.
892 { LDSB, LdReturn.rid, 2, -1 },
893 { LDSB, LdReturn.rid, 3, 1 },
895 { LDSH, LdReturn.rid, 2, -1 },
896 { LDSH, LdReturn.rid, 3, 1 },
898 { LDSW, LdReturn.rid, 2, -1 },
899 { LDSW, LdReturn.rid, 3, 1 },
902 #undef EXPLICIT_BUBBLES_NEEDED
903 #ifdef EXPLICIT_BUBBLES_NEEDED
905 // MULScc inserts one bubble.
906 // This means it breaks the current group (captured in UltraSparcSchedInfo)
907 // *and occupies all issue slots for the next cycle
909 //{ MULScc, AllIssueSlots.rid, 2, 2-1 },
910 //{ MULScc, AllIssueSlots.rid, 2, 2-1 },
911 //{ MULScc, AllIssueSlots.rid, 2, 2-1 },
912 //{ MULScc, AllIssueSlots.rid, 2, 2-1 },
915 // SMULcc inserts between 4 and 18 bubbles, depending on #leading 0s in rs1.
916 // We just model this with a simple average.
918 //{ SMULcc, AllIssueSlots.rid, 2, ((4+18)/2)-1 },
919 //{ SMULcc, AllIssueSlots.rid, 2, ((4+18)/2)-1 },
920 //{ SMULcc, AllIssueSlots.rid, 2, ((4+18)/2)-1 },
921 //{ SMULcc, AllIssueSlots.rid, 2, ((4+18)/2)-1 },
923 // SMULcc inserts between 4 and 19 bubbles, depending on #leading 0s in rs1.
924 //{ UMULcc, AllIssueSlots.rid, 2, ((4+19)/2)-1 },
925 //{ UMULcc, AllIssueSlots.rid, 2, ((4+19)/2)-1 },
926 //{ UMULcc, AllIssueSlots.rid, 2, ((4+19)/2)-1 },
927 //{ UMULcc, AllIssueSlots.rid, 2, ((4+19)/2)-1 },
930 // MULX inserts between 4 and 34 bubbles, depending on #leading 0s in rs1.
932 { MULX, AllIssueSlots.rid, 2, ((4+34)/2)-1 },
933 { MULX, AllIssueSlots.rid, 2, ((4+34)/2)-1 },
934 { MULX, AllIssueSlots.rid, 2, ((4+34)/2)-1 },
935 { MULX, AllIssueSlots.rid, 2, ((4+34)/2)-1 },
938 // SDIVcc inserts 36 bubbles.
940 //{ SDIVcc, AllIssueSlots.rid, 2, 36-1 },
941 //{ SDIVcc, AllIssueSlots.rid, 2, 36-1 },
942 //{ SDIVcc, AllIssueSlots.rid, 2, 36-1 },
943 //{ SDIVcc, AllIssueSlots.rid, 2, 36-1 },
945 // UDIVcc inserts 37 bubbles.
946 //{ UDIVcc, AllIssueSlots.rid, 2, 37-1 },
947 //{ UDIVcc, AllIssueSlots.rid, 2, 37-1 },
948 //{ UDIVcc, AllIssueSlots.rid, 2, 37-1 },
949 //{ UDIVcc, AllIssueSlots.rid, 2, 37-1 },
952 // SDIVX inserts 68 bubbles.
954 { SDIVX, AllIssueSlots.rid, 2, 68-1 },
955 { SDIVX, AllIssueSlots.rid, 2, 68-1 },
956 { SDIVX, AllIssueSlots.rid, 2, 68-1 },
957 { SDIVX, AllIssueSlots.rid, 2, 68-1 },
960 // UDIVX inserts 68 bubbles.
962 { UDIVX, AllIssueSlots.rid, 2, 68-1 },
963 { UDIVX, AllIssueSlots.rid, 2, 68-1 },
964 { UDIVX, AllIssueSlots.rid, 2, 68-1 },
965 { UDIVX, AllIssueSlots.rid, 2, 68-1 },
968 // WR inserts 4 bubbles.
970 //{ WR, AllIssueSlots.rid, 2, 68-1 },
971 //{ WR, AllIssueSlots.rid, 2, 68-1 },
972 //{ WR, AllIssueSlots.rid, 2, 68-1 },
973 //{ WR, AllIssueSlots.rid, 2, 68-1 },
976 // WRPR inserts 4 bubbles.
978 //{ WRPR, AllIssueSlots.rid, 2, 68-1 },
979 //{ WRPR, AllIssueSlots.rid, 2, 68-1 },
980 //{ WRPR, AllIssueSlots.rid, 2, 68-1 },
981 //{ WRPR, AllIssueSlots.rid, 2, 68-1 },
984 // DONE inserts 9 bubbles.
986 //{ DONE, AllIssueSlots.rid, 2, 9-1 },
987 //{ DONE, AllIssueSlots.rid, 2, 9-1 },
988 //{ DONE, AllIssueSlots.rid, 2, 9-1 },
989 //{ DONE, AllIssueSlots.rid, 2, 9-1 },
992 // RETRY inserts 9 bubbles.
994 //{ RETRY, AllIssueSlots.rid, 2, 9-1 },
995 //{ RETRY, AllIssueSlots.rid, 2, 9-1 },
996 //{ RETRY, AllIssueSlots.rid, 2, 9-1 },
997 //{ RETRY, AllIssueSlots.rid, 2, 9-1 },
999 #endif EXPLICIT_BUBBLES_NEEDED
1004 // Additional delays to be captured in code:
1005 // 1. RDPR from several state registers (page 349)
1006 // 2. RD from *any* register (page 349)
1007 // 3. Writes to TICK, PSTATE, TL registers and FLUSH{W} instr (page 349)
1008 // 4. Integer store can be in same group as instr producing value to store.
1009 // 5. BICC and BPICC can be in the same group as instr producing CC (pg 350)
1010 // 6. FMOVr cannot be in the same or next group as an IEU instr (pg 351).
1011 // 7. The second instr. of a CTI group inserts 9 bubbles (pg 351)
1012 // 8. WR{PR}, SVAE, SAVED, RESTORE, RESTORED, RETURN, RETRY, and DONE that
1013 // follow an annulling branch cannot be issued in the same group or in
1014 // the 3 groups following the branch.
1015 // 9. A predicted annulled load does not stall dependent instructions.
1016 // Other annulled delay slot instructions *do* stall dependents, so
1017 // nothing special needs to be done for them during scheduling.
1018 //10. Do not put a load use that may be annulled in the same group as the
1019 // branch. The group will stall until the load returns.
1020 //11. Single-prec. FP loads lock 2 registers, for dependency checking.
1023 // Additional delays we cannot or will not capture:
1024 // 1. If DCTI is last word of cache line, it is delayed until next line can be
1025 // fetched. Also, other DCTI alignment-related delays (pg 352)
1026 // 2. Load-after-store is delayed by 7 extra cycles if load hits in D-Cache.
1027 // Also, several other store-load and load-store conflicts (pg 358)
1028 // 3. MEMBAR, LD{X}FSR, LDD{A} and a bunch of other load stalls (pg 358)
1029 // 4. There can be at most 8 outstanding buffered store instructions
1030 // (including some others like MEMBAR, LDSTUB, CAS{AX}, and FLUSH)
1034 //---------------------------------------------------------------------------
1035 // class UltraSparcSchedInfo
1038 // Interface to instruction scheduling information for UltraSPARC.
1039 // The parameter values above are based on UltraSPARC IIi.
1040 //---------------------------------------------------------------------------
1043 class UltraSparcSchedInfo: public MachineSchedInfo {
1045 /*ctor*/ UltraSparcSchedInfo (const MachineInstrInfo* mii);
1046 /*dtor*/ virtual ~UltraSparcSchedInfo () {}
1048 virtual void initializeResources ();
1052 //---------------------------------------------------------------------------
1053 // class UltraSparcMachine
1056 // Primary interface to machine description for the UltraSPARC.
1057 // Primarily just initializes machine-dependent parameters in
1058 // class TargetMachine, and creates machine-dependent subclasses
1059 // for classes such as InstrInfo, SchedInfo and RegInfo.
1060 //---------------------------------------------------------------------------
1062 class UltraSparc : public TargetMachine {
1064 UltraSparcInstrInfo instrInfo;
1065 UltraSparcSchedInfo schedInfo;
1066 UltraSparcRegInfo regInfo;
1069 virtual ~UltraSparc() {}
1071 virtual const MachineInstrInfo &getInstrInfo() const { return instrInfo; }
1072 virtual const MachineSchedInfo &getSchedInfo() const { return schedInfo; }
1073 virtual const MachineRegInfo &getRegInfo() const { return regInfo; }
1075 // compileMethod - For the sparc, we do instruction selection, followed by
1076 // delay slot scheduling, then register allocation.
1078 virtual bool compileMethod(Method *M);
1081 // emitAssembly - Output assembly language code (a .s file) for the specified
1082 // module. The specified module must have been compiled before this may be
1085 virtual void emitAssembly(const Module *M, ostream &OutStr);