1 //===-- SparcInternals.h ----------------------------------------*- C++ -*-===//
3 // This file defines stuff that is to be private to the Sparc backend, but is
4 // shared among different portions of the backend.
6 //===----------------------------------------------------------------------===//
8 #ifndef SPARC_INTERNALS_H
9 #define SPARC_INTERNALS_H
11 #include "llvm/Target/TargetMachine.h"
12 #include "llvm/Target/MachineSchedInfo.h"
13 #include "llvm/Target/MachineFrameInfo.h"
14 #include "llvm/Target/MachineCacheInfo.h"
15 #include "llvm/Target/MachineRegInfo.h"
16 #include "llvm/Type.h"
17 #include <sys/types.h>
24 // OpCodeMask definitions for the Sparc V9
26 const OpCodeMask Immed = 0x00002000; // immed or reg operand?
27 const OpCodeMask Annul = 0x20000000; // annul delay instr?
28 const OpCodeMask PredictTaken = 0x00080000; // predict branch taken?
31 enum SparcInstrSchedClass {
32 SPARC_NONE, /* Instructions with no scheduling restrictions */
33 SPARC_IEUN, /* Integer class that can use IEU0 or IEU1 */
34 SPARC_IEU0, /* Integer class IEU0 */
35 SPARC_IEU1, /* Integer class IEU1 */
36 SPARC_FPM, /* FP Multiply or Divide instructions */
37 SPARC_FPA, /* All other FP instructions */
38 SPARC_CTI, /* Control-transfer instructions */
39 SPARC_LD, /* Load instructions */
40 SPARC_ST, /* Store instructions */
41 SPARC_SINGLE, /* Instructions that must issue by themselves */
43 SPARC_INV, /* This should stay at the end for the next value */
44 SPARC_NUM_SCHED_CLASSES = SPARC_INV
48 //---------------------------------------------------------------------------
49 // enum SparcMachineOpCode.
50 // const MachineInstrDescriptor SparcMachineInstrDesc[]
53 // Description of UltraSparc machine instructions.
55 //---------------------------------------------------------------------------
57 enum SparcMachineOpCode {
58 #define I(ENUM, OPCODESTRING, NUMOPERANDS, RESULTPOS, MAXIMM, IMMSE, \
59 NUMDELAYSLOTS, LATENCY, SCHEDCLASS, INSTFLAGS) \
61 #include "SparcInstr.def"
63 // End-of-array marker
65 NUM_REAL_OPCODES = PHI, // number of valid opcodes
66 NUM_TOTAL_OPCODES = INVALID_OPCODE
70 // Array of machine instruction descriptions...
71 extern const MachineInstrDescriptor SparcMachineInstrDesc[];
74 //---------------------------------------------------------------------------
75 // class UltraSparcInstrInfo
78 // Information about individual instructions.
79 // Most information is stored in the SparcMachineInstrDesc array above.
80 // Other information is computed on demand, and most such functions
81 // default to member functions in base class MachineInstrInfo.
82 //---------------------------------------------------------------------------
84 struct UltraSparcInstrInfo : public MachineInstrInfo {
85 UltraSparcInstrInfo(const TargetMachine& tgt);
88 // All immediate constants are in position 1 except the
89 // store instructions and SETxx.
91 virtual int getImmedConstantPos(MachineOpCode opCode) const {
93 if (this->maxImmedConstant(opCode, ignore) != 0)
95 assert(! this->isStore((MachineOpCode) STB - 1)); // 1st store opcode
96 assert(! this->isStore((MachineOpCode) STXFSR+1));// last store opcode
97 if (opCode==SETSW || opCode==SETUW || opCode==SETX || opCode==SETHI)
99 if (opCode >= STB && opCode <= STXFSR)
107 virtual bool hasResultInterlock (MachineOpCode opCode) const
109 // All UltraSPARC instructions have interlocks (note that delay slots
110 // are not considered here).
111 // However, instructions that use the result of an FCMP produce a
112 // 9-cycle stall if they are issued less than 3 cycles after the FCMP.
113 // Force the compiler to insert a software interlock (i.e., gap of
114 // 2 other groups, including NOPs if necessary).
115 return (opCode == FCMPS || opCode == FCMPD || opCode == FCMPQ);
118 //-------------------------------------------------------------------------
119 // Queries about representation of LLVM quantities (e.g., constants)
120 //-------------------------------------------------------------------------
122 virtual bool ConstantMayNotFitInImmedField(const Constant* CV,
123 const Instruction* I) const;
125 //-------------------------------------------------------------------------
126 // Code generation support for creating individual machine instructions
127 //-------------------------------------------------------------------------
129 // Create an instruction sequence to put the constant `val' into
130 // the virtual register `dest'. `val' may be a Constant or a
131 // GlobalValue, viz., the constant address of a global variable or function.
132 // The generated instructions are returned in `mvec'.
133 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
134 // Any stack space required is allocated via mcff.
136 virtual void CreateCodeToLoadConst(const TargetMachine& target,
140 std::vector<MachineInstr*>& mvec,
141 MachineCodeForInstruction& mcfi) const;
143 // Create an instruction sequence to copy an integer value `val'
144 // to a floating point value `dest' by copying to memory and back.
145 // val must be an integral type. dest must be a Float or Double.
146 // The generated instructions are returned in `mvec'.
147 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
148 // Any stack space required is allocated via mcff.
150 virtual void CreateCodeToCopyIntToFloat(const TargetMachine& target,
154 std::vector<MachineInstr*>& mvec,
155 MachineCodeForInstruction& mcfi) const;
157 // Similarly, create an instruction sequence to copy an FP value
158 // `val' to an integer value `dest' by copying to memory and back.
159 // The generated instructions are returned in `mvec'.
160 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
161 // Any stack space required is allocated via mcff.
163 virtual void CreateCodeToCopyFloatToInt(const TargetMachine& target,
167 std::vector<MachineInstr*>& mvec,
168 MachineCodeForInstruction& mcfi) const;
170 // Create instruction(s) to copy src to dest, for arbitrary types
171 // The generated instructions are returned in `mvec'.
172 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
173 // Any stack space required is allocated via mcff.
175 virtual void CreateCopyInstructionsByType(const TargetMachine& target,
179 std::vector<MachineInstr*>& mvec,
180 MachineCodeForInstruction& mcfi) const;
182 // Create instruction sequence to produce a sign-extended register value
183 // from an arbitrary sized value (sized in bits, not bytes).
184 // The generated instructions are appended to `mvec'.
185 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
186 // Any stack space required is allocated via mcff.
188 virtual void CreateSignExtensionInstructions(const TargetMachine& target,
191 unsigned int srcSizeInBits,
193 std::vector<MachineInstr*>& mvec,
194 MachineCodeForInstruction& mcfi) const;
196 // Create instruction sequence to produce a zero-extended register value
197 // from an arbitrary sized value (sized in bits, not bytes).
198 // The generated instructions are appended to `mvec'.
199 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
200 // Any stack space required is allocated via mcff.
202 virtual void CreateZeroExtensionInstructions(const TargetMachine& target,
205 unsigned int srcSizeInBits,
207 std::vector<MachineInstr*>& mvec,
208 MachineCodeForInstruction& mcfi) const;
212 //----------------------------------------------------------------------------
213 // class UltraSparcRegInfo
215 // This class implements the virtual class MachineRegInfo for Sparc.
217 //----------------------------------------------------------------------------
219 class UltraSparcRegInfo : public MachineRegInfo {
220 // The actual register classes in the Sparc
223 IntRegClassID, // Integer
224 FloatRegClassID, // Float (both single/double)
225 IntCCRegClassID, // Int Condition Code
226 FloatCCRegClassID // Float Condition code
230 // Type of registers available in Sparc. There can be several reg types
231 // in the same class. For instace, the float reg class has Single/Double
242 // **** WARNING: If the above enum order is changed, also modify
243 // getRegisterClassOfValue method below since it assumes this particular
244 // order for efficiency.
247 // reverse pointer to get info about the ultra sparc machine
249 const UltraSparc *const UltraSparcInfo;
251 // Number of registers used for passing int args (usually 6: %o0 - %o5)
253 unsigned const NumOfIntArgRegs;
255 // Number of registers used for passing float args (usually 32: %f0 - %f31)
257 unsigned const NumOfFloatArgRegs;
259 // An out of bound register number that can be used to initialize register
260 // numbers. Useful for error detection.
262 int const InvalidRegNum;
265 // ======================== Private Methods =============================
267 // The following methods are used to color special live ranges (e.g.
268 // function args and return values etc.) with specific hardware registers
269 // as required. See SparcRegInfo.cpp for the implementation.
271 void suggestReg4RetAddr(MachineInstr *RetMI,
272 LiveRangeInfo &LRI) const;
274 void suggestReg4CallAddr(MachineInstr *CallMI, LiveRangeInfo &LRI,
275 std::vector<RegClass *> RCList) const;
277 void InitializeOutgoingArg(MachineInstr* CallMI, AddedInstrns *CallAI,
278 PhyRegAlloc &PRA, LiveRange* LR,
279 unsigned regType, unsigned RegClassID,
280 int UniArgReg, unsigned int argNo,
281 std::vector<MachineInstr *>& AddedInstrnsBefore)
284 // The following 4 methods are used to find the RegType (see enum above)
285 // for a reg class and a given primitive type, a LiveRange, a Value,
286 // or a particular machine register.
287 // The fifth function gives the reg class of the given RegType.
289 int getRegType(unsigned regClassID, const Type* type) const;
290 int getRegType(const LiveRange *LR) const;
291 int getRegType(const Value *Val) const;
292 int getRegType(int unifiedRegNum) const;
294 // Used to generate a copy instruction based on the register class of
297 MachineInstr *cpValue2RegMI(Value *Val, unsigned DestReg,
301 // The following 2 methods are used to order the instructions addeed by
302 // the register allocator in association with function calling. See
303 // SparcRegInfo.cpp for more details
305 void moveInst2OrdVec(std::vector<MachineInstr *> &OrdVec,
306 MachineInstr *UnordInst,
307 PhyRegAlloc &PRA) const;
309 void OrderAddedInstrns(std::vector<MachineInstr *> &UnordVec,
310 std::vector<MachineInstr *> &OrdVec,
311 PhyRegAlloc &PRA) const;
314 // Compute which register can be used for an argument, if any
316 int regNumForIntArg(bool inCallee, bool isVarArgsCall,
317 unsigned argNo, unsigned intArgNo, unsigned fpArgNo,
318 unsigned& regClassId) const;
320 int regNumForFPArg(unsigned RegType, bool inCallee, bool isVarArgsCall,
321 unsigned argNo, unsigned intArgNo, unsigned fpArgNo,
322 unsigned& regClassId) const;
325 UltraSparcRegInfo(const UltraSparc &tgt);
327 // To get complete machine information structure using the machine register
330 inline const UltraSparc &getUltraSparcInfo() const {
331 return *UltraSparcInfo;
334 // To find the register class used for a specified Type
336 unsigned getRegClassIDOfType(const Type *type,
337 bool isCCReg = false) const;
339 // To find the register class of a Value
341 inline unsigned getRegClassIDOfValue(const Value *Val,
342 bool isCCReg = false) const {
343 return getRegClassIDOfType(Val->getType(), isCCReg);
346 // To find the register class to which a specified register belongs
348 unsigned getRegClassIDOfReg(int unifiedRegNum) const;
349 unsigned getRegClassIDOfRegType(int regType) const;
351 // getZeroRegNum - returns the register that contains always zero this is the
352 // unified register number
354 virtual int getZeroRegNum() const;
356 // getCallAddressReg - returns the reg used for pushing the address when a
357 // function is called. This can be used for other purposes between calls
359 unsigned getCallAddressReg() const;
361 // Returns the register containing the return address.
362 // It should be made sure that this register contains the return
363 // value when a return instruction is reached.
365 unsigned getReturnAddressReg() const;
367 // Number of registers used for passing int args (usually 6: %o0 - %o5)
368 // and float args (usually 32: %f0 - %f31)
370 unsigned const GetNumOfIntArgRegs() const { return NumOfIntArgRegs; }
371 unsigned const GetNumOfFloatArgRegs() const { return NumOfFloatArgRegs; }
373 // The following methods are used to color special live ranges (e.g.
374 // function args and return values etc.) with specific hardware registers
375 // as required. See SparcRegInfo.cpp for the implementation for Sparc.
377 void suggestRegs4MethodArgs(const Function *Meth,
378 LiveRangeInfo& LRI) const;
380 void suggestRegs4CallArgs(MachineInstr *CallMI,
382 std::vector<RegClass *> RCL) const;
384 void suggestReg4RetValue(MachineInstr *RetMI,
385 LiveRangeInfo& LRI) const;
387 void colorMethodArgs(const Function *Meth, LiveRangeInfo &LRI,
388 AddedInstrns *FirstAI) const;
390 void colorCallArgs(MachineInstr *CallMI, LiveRangeInfo &LRI,
391 AddedInstrns *CallAI, PhyRegAlloc &PRA,
392 const BasicBlock *BB) const;
394 void colorRetValue(MachineInstr *RetI, LiveRangeInfo& LRI,
395 AddedInstrns *RetAI) const;
398 // method used for printing a register for debugging purposes
400 static void printReg(const LiveRange *LR);
402 // Each register class has a seperate space for register IDs. To convert
403 // a regId in a register class to a common Id, or vice versa,
404 // we use the folloing methods.
406 // This method provides a unique number for each register
407 inline int getUnifiedRegNum(unsigned regClassID, int reg) const {
409 if (regClassID == IntRegClassID) {
410 assert(reg < 32 && "Invalid reg. number");
413 else if (regClassID == FloatRegClassID) {
414 assert(reg < 64 && "Invalid reg. number");
415 return reg + 32; // we have 32 int regs
417 else if (regClassID == FloatCCRegClassID) {
418 assert(reg < 4 && "Invalid reg. number");
419 return reg + 32 + 64; // 32 int, 64 float
421 else if (regClassID == IntCCRegClassID ) {
422 assert(reg == 0 && "Invalid reg. number");
423 return reg + 4+ 32 + 64; // only one int CC reg
425 else if (reg==InvalidRegNum) {
426 return InvalidRegNum;
429 assert(0 && "Invalid register class");
433 // This method converts the unified number to the number in its class,
434 // and returns the class ID in regClassID.
435 inline int getClassRegNum(int ureg, unsigned& regClassID) const {
436 if (ureg < 32) { regClassID = IntRegClassID; return ureg; }
437 else if (ureg < 32+64) { regClassID = FloatRegClassID; return ureg-32; }
438 else if (ureg < 4 +96) { regClassID = FloatCCRegClassID; return ureg-96; }
439 else if (ureg < 1 +100) { regClassID = IntCCRegClassID; return ureg-100;}
440 else if (ureg == InvalidRegNum) { return InvalidRegNum; }
441 else { assert(0 && "Invalid unified register number"); }
445 // Returns the assembly-language name of the specified machine register.
447 virtual const char * const getUnifiedRegName(int reg) const;
450 // returns the # of bytes of stack space allocated for each register
451 // type. For Sparc, currently we allocate 8 bytes on stack for all
452 // register types. We can optimize this later if necessary to save stack
453 // space (However, should make sure that stack alignment is correct)
455 inline int getSpilledRegSize(int RegType) const {
460 // To obtain the return value and the indirect call address (if any)
461 // contained in a CALL machine instruction
463 const Value * getCallInstRetVal(const MachineInstr *CallMI) const;
464 const Value * getCallInstIndirectAddrVal(const MachineInstr *CallMI) const;
466 // The following methods are used to generate "copy" machine instructions
467 // for an architecture.
469 // The function regTypeNeedsScratchReg() can be used to check whether a
470 // scratch register is needed to copy a register of type `regType' to
471 // or from memory. If so, such a scratch register can be provided by
472 // the caller (e.g., if it knows which regsiters are free); otherwise
473 // an arbitrary one will be chosen and spilled by the copy instructions.
475 bool regTypeNeedsScratchReg(int RegType,
476 int& scratchRegClassId) const;
478 void cpReg2RegMI(std::vector<MachineInstr*>& mvec,
479 unsigned SrcReg, unsigned DestReg,
482 void cpReg2MemMI(std::vector<MachineInstr*>& mvec,
483 unsigned SrcReg, unsigned DestPtrReg,
484 int Offset, int RegType, int scratchReg = -1) const;
486 void cpMem2RegMI(std::vector<MachineInstr*>& mvec,
487 unsigned SrcPtrReg, int Offset, unsigned DestReg,
488 int RegType, int scratchReg = -1) const;
490 void cpValue2Value(Value *Src, Value *Dest,
491 std::vector<MachineInstr*>& mvec) const;
493 // To see whether a register is a volatile (i.e., whehter it must be
494 // preserved acorss calls)
496 inline bool isRegVolatile(int RegClassID, int Reg) const {
497 return MachineRegClassArr[RegClassID]->isRegVolatile(Reg);
501 virtual unsigned getFramePointer() const;
502 virtual unsigned getStackPointer() const;
504 virtual int getInvalidRegNum() const {
505 return InvalidRegNum;
508 // This method inserts the caller saving code for call instructions
510 void insertCallerSavingCode(std::vector<MachineInstr*>& instrnsBefore,
511 std::vector<MachineInstr*>& instrnsAfter,
513 const BasicBlock *BB, PhyRegAlloc &PRA ) const;
519 //---------------------------------------------------------------------------
520 // class UltraSparcSchedInfo
523 // Interface to instruction scheduling information for UltraSPARC.
524 // The parameter values above are based on UltraSPARC IIi.
525 //---------------------------------------------------------------------------
528 class UltraSparcSchedInfo: public MachineSchedInfo {
530 UltraSparcSchedInfo(const TargetMachine &tgt);
532 virtual void initializeResources();
536 //---------------------------------------------------------------------------
537 // class UltraSparcFrameInfo
540 // Interface to stack frame layout info for the UltraSPARC.
541 // Starting offsets for each area of the stack frame are aligned at
542 // a multiple of getStackFrameSizeAlignment().
543 //---------------------------------------------------------------------------
545 class UltraSparcFrameInfo: public MachineFrameInfo {
547 UltraSparcFrameInfo(const TargetMachine &tgt) : MachineFrameInfo(tgt) {}
550 // These methods provide constant parameters of the frame layout.
552 int getStackFrameSizeAlignment() const { return StackFrameSizeAlignment;}
553 int getMinStackFrameSize() const { return MinStackFrameSize; }
554 int getNumFixedOutgoingArgs() const { return NumFixedOutgoingArgs; }
555 int getSizeOfEachArgOnStack() const { return SizeOfEachArgOnStack; }
556 bool argsOnStackHaveFixedSize() const { return true; }
558 // This method adjusts a stack offset to meet alignment rules of target.
559 // The fixed OFFSET (0x7ff) must be subtracted and the result aligned.
560 virtual int adjustAlignment (int unalignedOffset,
562 unsigned int align) const {
563 return unalignedOffset + (growUp? +1:-1)*((unalignedOffset-OFFSET) % align);
566 // These methods compute offsets using the frame contents for a
567 // particular function. The frame contents are obtained from the
568 // MachineCodeInfoForMethod object for the given function.
570 int getFirstIncomingArgOffset (MachineCodeForMethod& mcInfo,
573 growUp = true; // arguments area grows upwards
574 return FirstIncomingArgOffsetFromFP;
576 int getFirstOutgoingArgOffset (MachineCodeForMethod& mcInfo,
579 growUp = true; // arguments area grows upwards
580 return FirstOutgoingArgOffsetFromSP;
582 int getFirstOptionalOutgoingArgOffset(MachineCodeForMethod& mcInfo,
585 growUp = true; // arguments area grows upwards
586 return FirstOptionalOutgoingArgOffsetFromSP;
589 int getFirstAutomaticVarOffset (MachineCodeForMethod& mcInfo,
591 int getRegSpillAreaOffset (MachineCodeForMethod& mcInfo,
593 int getTmpAreaOffset (MachineCodeForMethod& mcInfo,
595 int getDynamicAreaOffset (MachineCodeForMethod& mcInfo,
599 // These methods specify the base register used for each stack area
600 // (generally FP or SP)
602 virtual int getIncomingArgBaseRegNum() const {
603 return (int) target.getRegInfo().getFramePointer();
605 virtual int getOutgoingArgBaseRegNum() const {
606 return (int) target.getRegInfo().getStackPointer();
608 virtual int getOptionalOutgoingArgBaseRegNum() const {
609 return (int) target.getRegInfo().getStackPointer();
611 virtual int getAutomaticVarBaseRegNum() const {
612 return (int) target.getRegInfo().getFramePointer();
614 virtual int getRegSpillAreaBaseRegNum() const {
615 return (int) target.getRegInfo().getFramePointer();
617 virtual int getDynamicAreaBaseRegNum() const {
618 return (int) target.getRegInfo().getStackPointer();
622 /*----------------------------------------------------------------------
623 This diagram shows the stack frame layout used by llc on Sparc V9.
624 Note that only the location of automatic variables, spill area,
625 temporary storage, and dynamically allocated stack area are chosen
626 by us. The rest conform to the Sparc V9 ABI.
627 All stack addresses are offset by OFFSET = 0x7ff (2047).
629 Alignment assumpteions and other invariants:
630 (1) %sp+OFFSET and %fp+OFFSET are always aligned on 16-byte boundary
631 (2) Variables in automatic, spill, temporary, or dynamic regions
632 are aligned according to their size as in all memory accesses.
633 (3) Everything below the dynamically allocated stack area is only used
634 during a call to another function, so it is never needed when
635 the current function is active. This is why space can be allocated
636 dynamically by incrementing %sp any time within the function.
641 %fp+OFFSET+176 Optional extra incoming arguments# 1..N
642 %fp+OFFSET+168 Incoming argument #6
644 %fp+OFFSET+128 Incoming argument #1
646 ---%fp+OFFSET-0--------Bottom of caller's stack frame--------------------
647 %fp+OFFSET-8 Automatic variables <-- ****TOP OF STACK FRAME****
652 %sp+OFFSET+176+8N Bottom of dynamically allocated stack area
653 %sp+OFFSET+168+8N Optional extra outgoing argument# N
655 %sp+OFFSET+176 Optional extra outgoing argument# 1
656 %sp+OFFSET+168 Outgoing argument #6
658 %sp+OFFSET+128 Outgoing argument #1
659 %sp+OFFSET+120 Save area for %i7
661 %sp+OFFSET+0 Save area for %l0 <-- ****BOTTOM OF STACK FRAME****
663 *----------------------------------------------------------------------*/
665 // All stack addresses must be offset by 0x7ff (2047) on Sparc V9.
666 static const int OFFSET = (int) 0x7ff;
667 static const int StackFrameSizeAlignment = 16;
668 static const int MinStackFrameSize = 176;
669 static const int NumFixedOutgoingArgs = 6;
670 static const int SizeOfEachArgOnStack = 8;
671 static const int FirstIncomingArgOffsetFromFP = 128 + OFFSET;
672 static const int FirstOptionalIncomingArgOffsetFromFP = 176 + OFFSET;
673 static const int StaticAreaOffsetFromFP = 0 + OFFSET;
674 static const int FirstOutgoingArgOffsetFromSP = 128 + OFFSET;
675 static const int FirstOptionalOutgoingArgOffsetFromSP = 176 + OFFSET;
679 //---------------------------------------------------------------------------
680 // class UltraSparcCacheInfo
683 // Interface to cache parameters for the UltraSPARC.
684 // Just use defaults for now.
685 //---------------------------------------------------------------------------
687 class UltraSparcCacheInfo: public MachineCacheInfo {
689 UltraSparcCacheInfo(const TargetMachine &T) : MachineCacheInfo(T) {}
693 //---------------------------------------------------------------------------
694 // class UltraSparcMachine
697 // Primary interface to machine description for the UltraSPARC.
698 // Primarily just initializes machine-dependent parameters in
699 // class TargetMachine, and creates machine-dependent subclasses
700 // for classes such as InstrInfo, SchedInfo and RegInfo.
701 //---------------------------------------------------------------------------
703 class UltraSparc : public TargetMachine {
705 UltraSparcInstrInfo instrInfo;
706 UltraSparcSchedInfo schedInfo;
707 UltraSparcRegInfo regInfo;
708 UltraSparcFrameInfo frameInfo;
709 UltraSparcCacheInfo cacheInfo;
713 virtual const MachineInstrInfo &getInstrInfo() const { return instrInfo; }
714 virtual const MachineSchedInfo &getSchedInfo() const { return schedInfo; }
715 virtual const MachineRegInfo &getRegInfo() const { return regInfo; }
716 virtual const MachineFrameInfo &getFrameInfo() const { return frameInfo; }
717 virtual const MachineCacheInfo &getCacheInfo() const { return cacheInfo; }
719 // getPrologEpilogCodeInserter - Inserts prolog/epilog code.
720 virtual Pass* getPrologEpilogInsertionPass();
722 // getFunctionAsmPrinterPass - Writes out machine code for a single function
723 virtual Pass* getFunctionAsmPrinterPass(std::ostream &Out);
725 // getModuleAsmPrinterPass - Writes generated machine code to assembly file.
726 virtual Pass* getModuleAsmPrinterPass(std::ostream &Out);
728 // getEmitBytecodeToAsmPass - Emits final LLVM bytecode to assembly file.
729 virtual Pass* getEmitBytecodeToAsmPass(std::ostream &Out);