1 //===-- SparcInternals.h ----------------------------------------*- C++ -*-===//
3 // This file defines stuff that is to be private to the Sparc backend, but is
4 // shared among different portions of the backend.
6 //===----------------------------------------------------------------------===//
8 #ifndef SPARC_INTERNALS_H
9 #define SPARC_INTERNALS_H
11 #include "llvm/Target/TargetMachine.h"
12 #include "llvm/Target/TargetSchedInfo.h"
13 #include "llvm/Target/TargetFrameInfo.h"
14 #include "llvm/Target/TargetCacheInfo.h"
15 #include "llvm/Target/TargetRegInfo.h"
16 #include "llvm/Target/TargetOptInfo.h"
17 #include "llvm/Type.h"
18 #include <sys/types.h>
25 enum SparcInstrSchedClass {
26 SPARC_NONE, /* Instructions with no scheduling restrictions */
27 SPARC_IEUN, /* Integer class that can use IEU0 or IEU1 */
28 SPARC_IEU0, /* Integer class IEU0 */
29 SPARC_IEU1, /* Integer class IEU1 */
30 SPARC_FPM, /* FP Multiply or Divide instructions */
31 SPARC_FPA, /* All other FP instructions */
32 SPARC_CTI, /* Control-transfer instructions */
33 SPARC_LD, /* Load instructions */
34 SPARC_ST, /* Store instructions */
35 SPARC_SINGLE, /* Instructions that must issue by themselves */
37 SPARC_INV, /* This should stay at the end for the next value */
38 SPARC_NUM_SCHED_CLASSES = SPARC_INV
42 //---------------------------------------------------------------------------
43 // enum SparcMachineOpCode.
44 // const TargetInstrDescriptor SparcMachineInstrDesc[]
47 // Description of UltraSparc machine instructions.
49 //---------------------------------------------------------------------------
51 enum SparcMachineOpCode {
52 #define I(ENUM, OPCODESTRING, NUMOPERANDS, RESULTPOS, MAXIMM, IMMSE, \
53 NUMDELAYSLOTS, LATENCY, SCHEDCLASS, INSTFLAGS) \
55 #include "SparcInstr.def"
57 // End-of-array marker
59 NUM_REAL_OPCODES = PHI, // number of valid opcodes
60 NUM_TOTAL_OPCODES = INVALID_OPCODE
64 // Array of machine instruction descriptions...
65 extern const TargetInstrDescriptor SparcMachineInstrDesc[];
68 //---------------------------------------------------------------------------
69 // class UltraSparcInstrInfo
72 // Information about individual instructions.
73 // Most information is stored in the SparcMachineInstrDesc array above.
74 // Other information is computed on demand, and most such functions
75 // default to member functions in base class TargetInstrInfo.
76 //---------------------------------------------------------------------------
78 struct UltraSparcInstrInfo : public TargetInstrInfo {
79 UltraSparcInstrInfo();
82 // All immediate constants are in position 1 except the
83 // store instructions and SETxx.
85 virtual int getImmedConstantPos(MachineOpCode opCode) const {
87 if (this->maxImmedConstant(opCode, ignore) != 0)
89 assert(! this->isStore((MachineOpCode) STB - 1)); // 1st store opcode
90 assert(! this->isStore((MachineOpCode) STXFSR+1));// last store opcode
91 if (opCode==SETSW || opCode==SETUW || opCode==SETX || opCode==SETHI)
93 if (opCode >= STB && opCode <= STXFSR)
101 virtual bool hasResultInterlock (MachineOpCode opCode) const
103 // All UltraSPARC instructions have interlocks (note that delay slots
104 // are not considered here).
105 // However, instructions that use the result of an FCMP produce a
106 // 9-cycle stall if they are issued less than 3 cycles after the FCMP.
107 // Force the compiler to insert a software interlock (i.e., gap of
108 // 2 other groups, including NOPs if necessary).
109 return (opCode == FCMPS || opCode == FCMPD || opCode == FCMPQ);
112 //-------------------------------------------------------------------------
113 // Queries about representation of LLVM quantities (e.g., constants)
114 //-------------------------------------------------------------------------
116 virtual bool ConstantMayNotFitInImmedField(const Constant* CV,
117 const Instruction* I) const;
119 //-------------------------------------------------------------------------
120 // Code generation support for creating individual machine instructions
121 //-------------------------------------------------------------------------
123 // Get certain common op codes for the current target. This and all the
124 // Create* methods below should be moved to a machine code generation class
126 virtual MachineOpCode getNOPOpCode() const { return NOP; }
128 // Create an instruction sequence to put the constant `val' into
129 // the virtual register `dest'. `val' may be a Constant or a
130 // GlobalValue, viz., the constant address of a global variable or function.
131 // The generated instructions are returned in `mvec'.
132 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
133 // Any stack space required is allocated via mcff.
135 virtual void CreateCodeToLoadConst(const TargetMachine& target,
139 std::vector<MachineInstr*>& mvec,
140 MachineCodeForInstruction& mcfi) const;
142 // Create an instruction sequence to copy an integer value `val'
143 // to a floating point value `dest' by copying to memory and back.
144 // val must be an integral type. dest must be a Float or Double.
145 // The generated instructions are returned in `mvec'.
146 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
147 // Any stack space required is allocated via mcff.
149 virtual void CreateCodeToCopyIntToFloat(const TargetMachine& target,
153 std::vector<MachineInstr*>& mvec,
154 MachineCodeForInstruction& mcfi) const;
156 // Similarly, create an instruction sequence to copy an FP value
157 // `val' to an integer value `dest' by copying to memory and back.
158 // The generated instructions are returned in `mvec'.
159 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
160 // Any stack space required is allocated via mcff.
162 virtual void CreateCodeToCopyFloatToInt(const TargetMachine& target,
166 std::vector<MachineInstr*>& mvec,
167 MachineCodeForInstruction& mcfi) const;
169 // Create instruction(s) to copy src to dest, for arbitrary types
170 // The generated instructions are returned in `mvec'.
171 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
172 // Any stack space required is allocated via mcff.
174 virtual void CreateCopyInstructionsByType(const TargetMachine& target,
178 std::vector<MachineInstr*>& mvec,
179 MachineCodeForInstruction& mcfi) const;
181 // Create instruction sequence to produce a sign-extended register value
182 // from an arbitrary sized value (sized in bits, not bytes).
183 // The generated instructions are appended to `mvec'.
184 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
185 // Any stack space required is allocated via mcff.
187 virtual void CreateSignExtensionInstructions(const TargetMachine& target,
191 unsigned int numLowBits,
192 std::vector<MachineInstr*>& mvec,
193 MachineCodeForInstruction& mcfi) const;
195 // Create instruction sequence to produce a zero-extended register value
196 // from an arbitrary sized value (sized in bits, not bytes).
197 // The generated instructions are appended to `mvec'.
198 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
199 // Any stack space required is allocated via mcff.
201 virtual void CreateZeroExtensionInstructions(const TargetMachine& target,
205 unsigned int numLowBits,
206 std::vector<MachineInstr*>& mvec,
207 MachineCodeForInstruction& mcfi) const;
211 //----------------------------------------------------------------------------
212 // class UltraSparcRegInfo
214 // This class implements the virtual class TargetRegInfo for Sparc.
216 //----------------------------------------------------------------------------
218 class UltraSparcRegInfo : public TargetRegInfo {
219 // The actual register classes in the Sparc
222 IntRegClassID, // Integer
223 FloatRegClassID, // Float (both single/double)
224 IntCCRegClassID, // Int Condition Code
225 FloatCCRegClassID // Float Condition code
229 // Type of registers available in Sparc. There can be several reg types
230 // in the same class. For instace, the float reg class has Single/Double
241 // **** WARNING: If the above enum order is changed, also modify
242 // getRegisterClassOfValue method below since it assumes this particular
243 // order for efficiency.
246 // Number of registers used for passing int args (usually 6: %o0 - %o5)
248 unsigned const NumOfIntArgRegs;
250 // Number of registers used for passing float args (usually 32: %f0 - %f31)
252 unsigned const NumOfFloatArgRegs;
254 // An out of bound register number that can be used to initialize register
255 // numbers. Useful for error detection.
257 int const InvalidRegNum;
260 // ======================== Private Methods =============================
262 // The following methods are used to color special live ranges (e.g.
263 // function args and return values etc.) with specific hardware registers
264 // as required. See SparcRegInfo.cpp for the implementation.
266 void suggestReg4RetAddr(MachineInstr *RetMI,
267 LiveRangeInfo &LRI) const;
269 void suggestReg4CallAddr(MachineInstr *CallMI, LiveRangeInfo &LRI) const;
271 void InitializeOutgoingArg(MachineInstr* CallMI, AddedInstrns *CallAI,
272 PhyRegAlloc &PRA, LiveRange* LR,
273 unsigned regType, unsigned RegClassID,
274 int UniArgReg, unsigned int argNo,
275 std::vector<MachineInstr *>& AddedInstrnsBefore)
278 int getRegType(const Type* type) const;
279 int getRegType(const LiveRange *LR) const;
280 int getRegType(int unifiedRegNum) const;
282 // Used to generate a copy instruction based on the register class of
285 MachineInstr *cpValue2RegMI(Value *Val, unsigned DestReg,
289 // The following 2 methods are used to order the instructions addeed by
290 // the register allocator in association with function calling. See
291 // SparcRegInfo.cpp for more details
293 void moveInst2OrdVec(std::vector<MachineInstr *> &OrdVec,
294 MachineInstr *UnordInst,
295 PhyRegAlloc &PRA) const;
297 void OrderAddedInstrns(std::vector<MachineInstr *> &UnordVec,
298 std::vector<MachineInstr *> &OrdVec,
299 PhyRegAlloc &PRA) const;
302 // Compute which register can be used for an argument, if any
304 int regNumForIntArg(bool inCallee, bool isVarArgsCall,
305 unsigned argNo, unsigned intArgNo, unsigned fpArgNo,
306 unsigned& regClassId) const;
308 int regNumForFPArg(unsigned RegType, bool inCallee, bool isVarArgsCall,
309 unsigned argNo, unsigned intArgNo, unsigned fpArgNo,
310 unsigned& regClassId) const;
313 UltraSparcRegInfo(const UltraSparc &tgt);
315 // To find the register class used for a specified Type
317 unsigned getRegClassIDOfType(const Type *type,
318 bool isCCReg = false) const;
320 // To find the register class to which a specified register belongs
322 unsigned getRegClassIDOfReg(int unifiedRegNum) const;
323 unsigned getRegClassIDOfRegType(int regType) const;
325 // getZeroRegNum - returns the register that contains always zero this is the
326 // unified register number
328 virtual int getZeroRegNum() const;
330 // getCallAddressReg - returns the reg used for pushing the address when a
331 // function is called. This can be used for other purposes between calls
333 unsigned getCallAddressReg() const;
335 // Returns the register containing the return address.
336 // It should be made sure that this register contains the return
337 // value when a return instruction is reached.
339 unsigned getReturnAddressReg() const;
341 // Number of registers used for passing int args (usually 6: %o0 - %o5)
342 // and float args (usually 32: %f0 - %f31)
344 unsigned const GetNumOfIntArgRegs() const { return NumOfIntArgRegs; }
345 unsigned const GetNumOfFloatArgRegs() const { return NumOfFloatArgRegs; }
347 // The following methods are used to color special live ranges (e.g.
348 // function args and return values etc.) with specific hardware registers
349 // as required. See SparcRegInfo.cpp for the implementation for Sparc.
351 void suggestRegs4MethodArgs(const Function *Meth,
352 LiveRangeInfo& LRI) const;
354 void suggestRegs4CallArgs(MachineInstr *CallMI,
355 LiveRangeInfo& LRI) const;
357 void suggestReg4RetValue(MachineInstr *RetMI,
358 LiveRangeInfo& LRI) const;
360 void colorMethodArgs(const Function *Meth, LiveRangeInfo &LRI,
361 AddedInstrns *FirstAI) const;
363 void colorCallArgs(MachineInstr *CallMI, LiveRangeInfo &LRI,
364 AddedInstrns *CallAI, PhyRegAlloc &PRA,
365 const BasicBlock *BB) const;
367 void colorRetValue(MachineInstr *RetI, LiveRangeInfo& LRI,
368 AddedInstrns *RetAI) const;
371 // method used for printing a register for debugging purposes
373 static void printReg(const LiveRange *LR);
375 // Each register class has a seperate space for register IDs. To convert
376 // a regId in a register class to a common Id, or vice versa,
377 // we use the folloing methods.
379 // This method provides a unique number for each register
380 inline int getUnifiedRegNum(unsigned regClassID, int reg) const {
382 if (regClassID == IntRegClassID) {
383 assert(reg < 32 && "Invalid reg. number");
386 else if (regClassID == FloatRegClassID) {
387 assert(reg < 64 && "Invalid reg. number");
388 return reg + 32; // we have 32 int regs
390 else if (regClassID == FloatCCRegClassID) {
391 assert(reg < 4 && "Invalid reg. number");
392 return reg + 32 + 64; // 32 int, 64 float
394 else if (regClassID == IntCCRegClassID ) {
395 assert(reg == 0 && "Invalid reg. number");
396 return reg + 4+ 32 + 64; // only one int CC reg
398 else if (reg==InvalidRegNum) {
399 return InvalidRegNum;
402 assert(0 && "Invalid register class");
406 // This method converts the unified number to the number in its class,
407 // and returns the class ID in regClassID.
408 inline int getClassRegNum(int ureg, unsigned& regClassID) const {
409 if (ureg < 32) { regClassID = IntRegClassID; return ureg; }
410 else if (ureg < 32+64) { regClassID = FloatRegClassID; return ureg-32; }
411 else if (ureg < 4 +96) { regClassID = FloatCCRegClassID; return ureg-96; }
412 else if (ureg < 1 +100) { regClassID = IntCCRegClassID; return ureg-100;}
413 else if (ureg == InvalidRegNum) { return InvalidRegNum; }
414 else { assert(0 && "Invalid unified register number"); }
418 // Returns the assembly-language name of the specified machine register.
420 virtual const char * const getUnifiedRegName(int reg) const;
423 // returns the # of bytes of stack space allocated for each register
424 // type. For Sparc, currently we allocate 8 bytes on stack for all
425 // register types. We can optimize this later if necessary to save stack
426 // space (However, should make sure that stack alignment is correct)
428 inline int getSpilledRegSize(int RegType) const {
433 // To obtain the return value and the indirect call address (if any)
434 // contained in a CALL machine instruction
436 const Value * getCallInstRetVal(const MachineInstr *CallMI) const;
437 const Value * getCallInstIndirectAddrVal(const MachineInstr *CallMI) const;
439 // The following methods are used to generate "copy" machine instructions
440 // for an architecture.
442 // The function regTypeNeedsScratchReg() can be used to check whether a
443 // scratch register is needed to copy a register of type `regType' to
444 // or from memory. If so, such a scratch register can be provided by
445 // the caller (e.g., if it knows which regsiters are free); otherwise
446 // an arbitrary one will be chosen and spilled by the copy instructions.
448 bool regTypeNeedsScratchReg(int RegType,
449 int& scratchRegClassId) const;
451 void cpReg2RegMI(std::vector<MachineInstr*>& mvec,
452 unsigned SrcReg, unsigned DestReg,
455 void cpReg2MemMI(std::vector<MachineInstr*>& mvec,
456 unsigned SrcReg, unsigned DestPtrReg,
457 int Offset, int RegType, int scratchReg = -1) const;
459 void cpMem2RegMI(std::vector<MachineInstr*>& mvec,
460 unsigned SrcPtrReg, int Offset, unsigned DestReg,
461 int RegType, int scratchReg = -1) const;
463 void cpValue2Value(Value *Src, Value *Dest,
464 std::vector<MachineInstr*>& mvec) const;
466 // To see whether a register is a volatile (i.e., whehter it must be
467 // preserved acorss calls)
469 inline bool isRegVolatile(int RegClassID, int Reg) const {
470 return MachineRegClassArr[RegClassID]->isRegVolatile(Reg);
474 virtual unsigned getFramePointer() const;
475 virtual unsigned getStackPointer() const;
477 virtual int getInvalidRegNum() const {
478 return InvalidRegNum;
481 // This method inserts the caller saving code for call instructions
483 void insertCallerSavingCode(std::vector<MachineInstr*>& instrnsBefore,
484 std::vector<MachineInstr*>& instrnsAfter,
486 const BasicBlock *BB, PhyRegAlloc &PRA ) const;
492 //---------------------------------------------------------------------------
493 // class UltraSparcSchedInfo
496 // Interface to instruction scheduling information for UltraSPARC.
497 // The parameter values above are based on UltraSPARC IIi.
498 //---------------------------------------------------------------------------
501 class UltraSparcSchedInfo: public TargetSchedInfo {
503 UltraSparcSchedInfo(const TargetMachine &tgt);
505 virtual void initializeResources();
509 //---------------------------------------------------------------------------
510 // class UltraSparcFrameInfo
513 // Interface to stack frame layout info for the UltraSPARC.
514 // Starting offsets for each area of the stack frame are aligned at
515 // a multiple of getStackFrameSizeAlignment().
516 //---------------------------------------------------------------------------
518 class UltraSparcFrameInfo: public TargetFrameInfo {
519 const TargetMachine ⌖
521 UltraSparcFrameInfo(const TargetMachine &TM)
522 : TargetFrameInfo(StackGrowsDown, StackFrameSizeAlignment, 0), target(TM) {}
525 // These methods provide constant parameters of the frame layout.
527 int getStackFrameSizeAlignment() const { return StackFrameSizeAlignment;}
528 int getMinStackFrameSize() const { return MinStackFrameSize; }
529 int getNumFixedOutgoingArgs() const { return NumFixedOutgoingArgs; }
530 int getSizeOfEachArgOnStack() const { return SizeOfEachArgOnStack; }
531 bool argsOnStackHaveFixedSize() const { return true; }
533 // This method adjusts a stack offset to meet alignment rules of target.
534 // The fixed OFFSET (0x7ff) must be subtracted and the result aligned.
535 virtual int adjustAlignment (int unalignedOffset,
537 unsigned int align) const {
538 return unalignedOffset + (growUp? +1:-1)*((unalignedOffset-OFFSET) % align);
541 // These methods compute offsets using the frame contents for a
542 // particular function. The frame contents are obtained from the
543 // MachineCodeInfoForMethod object for the given function.
545 int getFirstIncomingArgOffset (MachineFunction& mcInfo,
548 growUp = true; // arguments area grows upwards
549 return FirstIncomingArgOffsetFromFP;
551 int getFirstOutgoingArgOffset (MachineFunction& mcInfo,
554 growUp = true; // arguments area grows upwards
555 return FirstOutgoingArgOffsetFromSP;
557 int getFirstOptionalOutgoingArgOffset(MachineFunction& mcInfo,
560 growUp = true; // arguments area grows upwards
561 return FirstOptionalOutgoingArgOffsetFromSP;
564 int getFirstAutomaticVarOffset (MachineFunction& mcInfo,
566 int getRegSpillAreaOffset (MachineFunction& mcInfo,
568 int getTmpAreaOffset (MachineFunction& mcInfo,
570 int getDynamicAreaOffset (MachineFunction& mcInfo,
574 // These methods specify the base register used for each stack area
575 // (generally FP or SP)
577 virtual int getIncomingArgBaseRegNum() const {
578 return (int) target.getRegInfo().getFramePointer();
580 virtual int getOutgoingArgBaseRegNum() const {
581 return (int) target.getRegInfo().getStackPointer();
583 virtual int getOptionalOutgoingArgBaseRegNum() const {
584 return (int) target.getRegInfo().getStackPointer();
586 virtual int getAutomaticVarBaseRegNum() const {
587 return (int) target.getRegInfo().getFramePointer();
589 virtual int getRegSpillAreaBaseRegNum() const {
590 return (int) target.getRegInfo().getFramePointer();
592 virtual int getDynamicAreaBaseRegNum() const {
593 return (int) target.getRegInfo().getStackPointer();
596 virtual int getIncomingArgOffset(MachineFunction& mcInfo,
597 unsigned argNum) const {
598 assert(argsOnStackHaveFixedSize());
600 unsigned relativeOffset = argNum * getSizeOfEachArgOnStack();
601 bool growUp; // do args grow up or down
602 int firstArg = getFirstIncomingArgOffset(mcInfo, growUp);
603 return growUp ? firstArg + relativeOffset : firstArg - relativeOffset;
606 virtual int getOutgoingArgOffset(MachineFunction& mcInfo,
607 unsigned argNum) const {
608 assert(argsOnStackHaveFixedSize());
609 //assert(((int) argNum - this->getNumFixedOutgoingArgs())
610 // <= (int) mcInfo.getInfo()->getMaxOptionalNumArgs());
612 unsigned relativeOffset = argNum * getSizeOfEachArgOnStack();
613 bool growUp; // do args grow up or down
614 int firstArg = getFirstOutgoingArgOffset(mcInfo, growUp);
615 return growUp ? firstArg + relativeOffset : firstArg - relativeOffset;
619 /*----------------------------------------------------------------------
620 This diagram shows the stack frame layout used by llc on Sparc V9.
621 Note that only the location of automatic variables, spill area,
622 temporary storage, and dynamically allocated stack area are chosen
623 by us. The rest conform to the Sparc V9 ABI.
624 All stack addresses are offset by OFFSET = 0x7ff (2047).
626 Alignment assumptions and other invariants:
627 (1) %sp+OFFSET and %fp+OFFSET are always aligned on 16-byte boundary
628 (2) Variables in automatic, spill, temporary, or dynamic regions
629 are aligned according to their size as in all memory accesses.
630 (3) Everything below the dynamically allocated stack area is only used
631 during a call to another function, so it is never needed when
632 the current function is active. This is why space can be allocated
633 dynamically by incrementing %sp any time within the function.
638 %fp+OFFSET+176 Optional extra incoming arguments# 1..N
639 %fp+OFFSET+168 Incoming argument #6
641 %fp+OFFSET+128 Incoming argument #1
643 ---%fp+OFFSET-0--------Bottom of caller's stack frame--------------------
644 %fp+OFFSET-8 Automatic variables <-- ****TOP OF STACK FRAME****
649 %sp+OFFSET+176+8N Bottom of dynamically allocated stack area
650 %sp+OFFSET+168+8N Optional extra outgoing argument# N
652 %sp+OFFSET+176 Optional extra outgoing argument# 1
653 %sp+OFFSET+168 Outgoing argument #6
655 %sp+OFFSET+128 Outgoing argument #1
656 %sp+OFFSET+120 Save area for %i7
658 %sp+OFFSET+0 Save area for %l0 <-- ****BOTTOM OF STACK FRAME****
660 *----------------------------------------------------------------------*/
662 // All stack addresses must be offset by 0x7ff (2047) on Sparc V9.
663 static const int OFFSET = (int) 0x7ff;
664 static const int StackFrameSizeAlignment = 16;
665 static const int MinStackFrameSize = 176;
666 static const int NumFixedOutgoingArgs = 6;
667 static const int SizeOfEachArgOnStack = 8;
668 static const int FirstIncomingArgOffsetFromFP = 128 + OFFSET;
669 static const int FirstOptionalIncomingArgOffsetFromFP = 176 + OFFSET;
670 static const int StaticAreaOffsetFromFP = 0 + OFFSET;
671 static const int FirstOutgoingArgOffsetFromSP = 128 + OFFSET;
672 static const int FirstOptionalOutgoingArgOffsetFromSP = 176 + OFFSET;
676 //---------------------------------------------------------------------------
677 // class UltraSparcCacheInfo
680 // Interface to cache parameters for the UltraSPARC.
681 // Just use defaults for now.
682 //---------------------------------------------------------------------------
684 struct UltraSparcCacheInfo: public TargetCacheInfo {
685 UltraSparcCacheInfo(const TargetMachine &T) : TargetCacheInfo(T) {}
689 //---------------------------------------------------------------------------
690 // class UltraSparcOptInfo
693 // Interface to machine-level optimization routines for the UltraSPARC.
694 //---------------------------------------------------------------------------
696 struct UltraSparcOptInfo: public TargetOptInfo {
697 UltraSparcOptInfo(const TargetMachine &T) : TargetOptInfo(T) {}
699 virtual bool IsUselessCopy (const MachineInstr* MI) const;
703 //---------------------------------------------------------------------------
704 // class UltraSparcMachine
707 // Primary interface to machine description for the UltraSPARC.
708 // Primarily just initializes machine-dependent parameters in
709 // class TargetMachine, and creates machine-dependent subclasses
710 // for classes such as InstrInfo, SchedInfo and RegInfo.
711 //---------------------------------------------------------------------------
713 class UltraSparc : public TargetMachine {
714 UltraSparcInstrInfo instrInfo;
715 UltraSparcSchedInfo schedInfo;
716 UltraSparcRegInfo regInfo;
717 UltraSparcFrameInfo frameInfo;
718 UltraSparcCacheInfo cacheInfo;
719 UltraSparcOptInfo optInfo;
723 virtual const TargetInstrInfo &getInstrInfo() const { return instrInfo; }
724 virtual const TargetSchedInfo &getSchedInfo() const { return schedInfo; }
725 virtual const TargetRegInfo &getRegInfo() const { return regInfo; }
726 virtual const TargetFrameInfo &getFrameInfo() const { return frameInfo; }
727 virtual const TargetCacheInfo &getCacheInfo() const { return cacheInfo; }
728 virtual const TargetOptInfo &getOptInfo() const { return optInfo; }
730 virtual bool addPassesToEmitAssembly(PassManager &PM, std::ostream &Out);
732 // getPrologEpilogInsertionPass - Inserts prolog/epilog code.
733 Pass* getPrologEpilogInsertionPass();
735 // getFunctionAsmPrinterPass - Writes out machine code for a single function
736 Pass* getFunctionAsmPrinterPass(std::ostream &Out);
738 // getModuleAsmPrinterPass - Writes generated machine code to assembly file.
739 Pass* getModuleAsmPrinterPass(std::ostream &Out);
741 // getEmitBytecodeToAsmPass - Emits final LLVM bytecode to assembly file.
742 Pass* getEmitBytecodeToAsmPass(std::ostream &Out);
745 int64_t GetConstantValueAsSignedInt(const Value *V, bool &isValidConstant);