1 //===-- SparcInternals.h ----------------------------------------*- C++ -*-===//
3 // This file defines stuff that is to be private to the Sparc backend, but is
4 // shared among different portions of the backend.
6 //===----------------------------------------------------------------------===//
8 #ifndef SPARC_INTERNALS_H
9 #define SPARC_INTERNALS_H
11 #include "llvm/Target/TargetMachine.h"
12 #include "llvm/Target/MachineSchedInfo.h"
13 #include "llvm/Target/MachineFrameInfo.h"
14 #include "llvm/Target/MachineCacheInfo.h"
15 #include "llvm/Target/MachineRegInfo.h"
16 #include "llvm/Type.h"
17 #include <sys/types.h>
24 Pass *createPrologEpilogCodeInserter(TargetMachine &TM);
26 // OpCodeMask definitions for the Sparc V9
28 const OpCodeMask Immed = 0x00002000; // immed or reg operand?
29 const OpCodeMask Annul = 0x20000000; // annul delay instr?
30 const OpCodeMask PredictTaken = 0x00080000; // predict branch taken?
33 enum SparcInstrSchedClass {
34 SPARC_NONE, /* Instructions with no scheduling restrictions */
35 SPARC_IEUN, /* Integer class that can use IEU0 or IEU1 */
36 SPARC_IEU0, /* Integer class IEU0 */
37 SPARC_IEU1, /* Integer class IEU1 */
38 SPARC_FPM, /* FP Multiply or Divide instructions */
39 SPARC_FPA, /* All other FP instructions */
40 SPARC_CTI, /* Control-transfer instructions */
41 SPARC_LD, /* Load instructions */
42 SPARC_ST, /* Store instructions */
43 SPARC_SINGLE, /* Instructions that must issue by themselves */
45 SPARC_INV, /* This should stay at the end for the next value */
46 SPARC_NUM_SCHED_CLASSES = SPARC_INV
50 //---------------------------------------------------------------------------
51 // enum SparcMachineOpCode.
52 // const MachineInstrDescriptor SparcMachineInstrDesc[]
55 // Description of UltraSparc machine instructions.
57 //---------------------------------------------------------------------------
59 enum SparcMachineOpCode {
60 #define I(ENUM, OPCODESTRING, NUMOPERANDS, RESULTPOS, MAXIMM, IMMSE, \
61 NUMDELAYSLOTS, LATENCY, SCHEDCLASS, INSTFLAGS) \
63 #include "SparcInstr.def"
65 // End-of-array marker
67 NUM_REAL_OPCODES = PHI, // number of valid opcodes
68 NUM_TOTAL_OPCODES = INVALID_OPCODE
72 // Array of machine instruction descriptions...
73 extern const MachineInstrDescriptor SparcMachineInstrDesc[];
76 //---------------------------------------------------------------------------
77 // class UltraSparcInstrInfo
80 // Information about individual instructions.
81 // Most information is stored in the SparcMachineInstrDesc array above.
82 // Other information is computed on demand, and most such functions
83 // default to member functions in base class MachineInstrInfo.
84 //---------------------------------------------------------------------------
86 struct UltraSparcInstrInfo : public MachineInstrInfo {
87 UltraSparcInstrInfo(const TargetMachine& tgt);
90 // All immediate constants are in position 1 except the
91 // store instructions.
93 virtual int getImmedConstantPos(MachineOpCode opCode) const {
95 if (this->maxImmedConstant(opCode, ignore) != 0)
97 assert(! this->isStore((MachineOpCode) STB - 1)); // 1st store opcode
98 assert(! this->isStore((MachineOpCode) STXFSR+1));// last store opcode
99 return (opCode >= STB && opCode <= STXFSR)? 2 : 1;
105 virtual bool hasResultInterlock (MachineOpCode opCode) const
107 // All UltraSPARC instructions have interlocks (note that delay slots
108 // are not considered here).
109 // However, instructions that use the result of an FCMP produce a
110 // 9-cycle stall if they are issued less than 3 cycles after the FCMP.
111 // Force the compiler to insert a software interlock (i.e., gap of
112 // 2 other groups, including NOPs if necessary).
113 return (opCode == FCMPS || opCode == FCMPD || opCode == FCMPQ);
116 //-------------------------------------------------------------------------
117 // Code generation support for creating individual machine instructions
118 //-------------------------------------------------------------------------
120 // Create an instruction sequence to put the constant `val' into
121 // the virtual register `dest'. `val' may be a Constant or a
122 // GlobalValue, viz., the constant address of a global variable or function.
123 // The generated instructions are returned in `mvec'.
124 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
125 // Any stack space required is allocated via mcff.
127 virtual void CreateCodeToLoadConst(const TargetMachine& target,
131 std::vector<MachineInstr*>& mvec,
132 MachineCodeForInstruction& mcfi) const;
134 // Create an instruction sequence to copy an integer value `val'
135 // to a floating point value `dest' by copying to memory and back.
136 // val must be an integral type. dest must be a Float or Double.
137 // The generated instructions are returned in `mvec'.
138 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
139 // Any stack space required is allocated via mcff.
141 virtual void CreateCodeToCopyIntToFloat(const TargetMachine& target,
145 std::vector<MachineInstr*>& mvec,
146 MachineCodeForInstruction& mcfi) const;
148 // Similarly, create an instruction sequence to copy an FP value
149 // `val' to an integer value `dest' by copying to memory and back.
150 // The generated instructions are returned in `mvec'.
151 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
152 // Any stack space required is allocated via mcff.
154 virtual void CreateCodeToCopyFloatToInt(const TargetMachine& target,
158 std::vector<MachineInstr*>& mvec,
159 MachineCodeForInstruction& mcfi) const;
161 // Create instruction(s) to copy src to dest, for arbitrary types
162 // The generated instructions are returned in `mvec'.
163 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
164 // Any stack space required is allocated via mcff.
166 virtual void CreateCopyInstructionsByType(const TargetMachine& target,
170 std::vector<MachineInstr*>& mvec,
171 MachineCodeForInstruction& mcfi) const;
173 // Create instruction sequence to produce a sign-extended register value
174 // from an arbitrary sized value (sized in bits, not bytes).
175 // Any stack space required is allocated via mcff.
177 virtual void CreateSignExtensionInstructions(const TargetMachine& target,
179 Value* unsignedSrcVal,
180 unsigned int srcSizeInBits,
182 std::vector<MachineInstr*>& mvec,
183 MachineCodeForInstruction& mcfi) const;
187 //----------------------------------------------------------------------------
188 // class UltraSparcRegInfo
190 // This class implements the virtual class MachineRegInfo for Sparc.
192 //----------------------------------------------------------------------------
194 class UltraSparcRegInfo : public MachineRegInfo {
195 // The actual register classes in the Sparc
198 IntRegClassID, // Integer
199 FloatRegClassID, // Float (both single/double)
200 IntCCRegClassID, // Int Condition Code
201 FloatCCRegClassID // Float Condition code
205 // Type of registers available in Sparc. There can be several reg types
206 // in the same class. For instace, the float reg class has Single/Double
217 // **** WARNING: If the above enum order is changed, also modify
218 // getRegisterClassOfValue method below since it assumes this particular
219 // order for efficiency.
222 // reverse pointer to get info about the ultra sparc machine
224 const UltraSparc *const UltraSparcInfo;
226 // Number of registers used for passing int args (usually 6: %o0 - %o5)
228 unsigned const NumOfIntArgRegs;
230 // Number of registers used for passing float args (usually 32: %f0 - %f31)
232 unsigned const NumOfFloatArgRegs;
234 // An out of bound register number that can be used to initialize register
235 // numbers. Useful for error detection.
237 int const InvalidRegNum;
240 // ======================== Private Methods =============================
242 // The following methods are used to color special live ranges (e.g.
243 // function args and return values etc.) with specific hardware registers
244 // as required. See SparcRegInfo.cpp for the implementation.
246 void suggestReg4RetAddr(MachineInstr *RetMI,
247 LiveRangeInfo &LRI) const;
249 void suggestReg4CallAddr(MachineInstr *CallMI, LiveRangeInfo &LRI,
250 std::vector<RegClass *> RCList) const;
252 void InitializeOutgoingArg(MachineInstr* CallMI, AddedInstrns *CallAI,
253 PhyRegAlloc &PRA, LiveRange* LR,
254 unsigned regType, unsigned RegClassID,
255 int UniArgReg, unsigned int argNo,
256 std::vector<MachineInstr *>& AddedInstrnsBefore)
259 // The following 4 methods are used to find the RegType (see enum above)
260 // for a reg class and a given primitive type, a LiveRange, a Value,
261 // or a particular machine register.
262 // The fifth function gives the reg class of the given RegType.
264 int getRegType(unsigned regClassID, const Type* type) const;
265 int getRegType(const LiveRange *LR) const;
266 int getRegType(const Value *Val) const;
267 int getRegType(int unifiedRegNum) const;
269 // Used to generate a copy instruction based on the register class of
272 MachineInstr *cpValue2RegMI(Value *Val, unsigned DestReg,
276 // The following 2 methods are used to order the instructions addeed by
277 // the register allocator in association with function calling. See
278 // SparcRegInfo.cpp for more details
280 void moveInst2OrdVec(std::vector<MachineInstr *> &OrdVec,
281 MachineInstr *UnordInst,
282 PhyRegAlloc &PRA) const;
284 void OrderAddedInstrns(std::vector<MachineInstr *> &UnordVec,
285 std::vector<MachineInstr *> &OrdVec,
286 PhyRegAlloc &PRA) const;
289 // Compute which register can be used for an argument, if any
291 int regNumForIntArg(bool inCallee, bool isVarArgsCall,
292 unsigned argNo, unsigned intArgNo, unsigned fpArgNo,
293 unsigned& regClassId) const;
295 int regNumForFPArg(unsigned RegType, bool inCallee, bool isVarArgsCall,
296 unsigned argNo, unsigned intArgNo, unsigned fpArgNo,
297 unsigned& regClassId) const;
300 UltraSparcRegInfo(const UltraSparc &tgt);
302 // To get complete machine information structure using the machine register
305 inline const UltraSparc &getUltraSparcInfo() const {
306 return *UltraSparcInfo;
309 // To find the register class used for a specified Type
311 unsigned getRegClassIDOfType(const Type *type,
312 bool isCCReg = false) const;
314 // To find the register class of a Value
316 inline unsigned getRegClassIDOfValue(const Value *Val,
317 bool isCCReg = false) const {
318 return getRegClassIDOfType(Val->getType(), isCCReg);
321 // To find the register class to which a specified register belongs
323 unsigned getRegClassIDOfReg(int unifiedRegNum) const;
324 unsigned getRegClassIDOfRegType(int regType) const;
326 // getZeroRegNum - returns the register that contains always zero this is the
327 // unified register number
329 virtual int getZeroRegNum() const;
331 // getCallAddressReg - returns the reg used for pushing the address when a
332 // function is called. This can be used for other purposes between calls
334 unsigned getCallAddressReg() const;
336 // Returns the register containing the return address.
337 // It should be made sure that this register contains the return
338 // value when a return instruction is reached.
340 unsigned getReturnAddressReg() const;
342 // Number of registers used for passing int args (usually 6: %o0 - %o5)
343 // and float args (usually 32: %f0 - %f31)
345 unsigned const GetNumOfIntArgRegs() const { return NumOfIntArgRegs; }
346 unsigned const GetNumOfFloatArgRegs() const { return NumOfFloatArgRegs; }
348 // The following methods are used to color special live ranges (e.g.
349 // function args and return values etc.) with specific hardware registers
350 // as required. See SparcRegInfo.cpp for the implementation for Sparc.
352 void suggestRegs4MethodArgs(const Function *Meth,
353 LiveRangeInfo& LRI) const;
355 void suggestRegs4CallArgs(MachineInstr *CallMI,
357 std::vector<RegClass *> RCL) const;
359 void suggestReg4RetValue(MachineInstr *RetMI,
360 LiveRangeInfo& LRI) const;
362 void colorMethodArgs(const Function *Meth, LiveRangeInfo &LRI,
363 AddedInstrns *FirstAI) const;
365 void colorCallArgs(MachineInstr *CallMI, LiveRangeInfo &LRI,
366 AddedInstrns *CallAI, PhyRegAlloc &PRA,
367 const BasicBlock *BB) const;
369 void colorRetValue(MachineInstr *RetI, LiveRangeInfo& LRI,
370 AddedInstrns *RetAI) const;
373 // method used for printing a register for debugging purposes
375 static void printReg(const LiveRange *LR);
377 // Each register class has a seperate space for register IDs. To convert
378 // a regId in a register class to a common Id, or vice versa,
379 // we use the folloing methods.
381 // This method provides a unique number for each register
382 inline int getUnifiedRegNum(unsigned regClassID, int reg) const {
384 if (regClassID == IntRegClassID) {
385 assert(reg < 32 && "Invalid reg. number");
388 else if (regClassID == FloatRegClassID) {
389 assert(reg < 64 && "Invalid reg. number");
390 return reg + 32; // we have 32 int regs
392 else if (regClassID == FloatCCRegClassID) {
393 assert(reg < 4 && "Invalid reg. number");
394 return reg + 32 + 64; // 32 int, 64 float
396 else if (regClassID == IntCCRegClassID ) {
397 assert(reg == 0 && "Invalid reg. number");
398 return reg + 4+ 32 + 64; // only one int CC reg
400 else if (reg==InvalidRegNum) {
401 return InvalidRegNum;
404 assert(0 && "Invalid register class");
408 // This method converts the unified number to the number in its class,
409 // and returns the class ID in regClassID.
410 inline int getClassRegNum(int ureg, unsigned& regClassID) const {
411 if (ureg < 32) { regClassID = IntRegClassID; return ureg; }
412 else if (ureg < 32+64) { regClassID = FloatRegClassID; return ureg-32; }
413 else if (ureg < 4 +96) { regClassID = FloatCCRegClassID; return ureg-96; }
414 else if (ureg < 1 +100) { regClassID = IntCCRegClassID; return ureg-100;}
415 else if (ureg == InvalidRegNum) { return InvalidRegNum; }
416 else { assert(0 && "Invalid unified register number"); }
420 // Returns the assembly-language name of the specified machine register.
422 virtual const char * const getUnifiedRegName(int reg) const;
425 // returns the # of bytes of stack space allocated for each register
426 // type. For Sparc, currently we allocate 8 bytes on stack for all
427 // register types. We can optimize this later if necessary to save stack
428 // space (However, should make sure that stack alignment is correct)
430 inline int getSpilledRegSize(int RegType) const {
435 // To obtain the return value and the indirect call address (if any)
436 // contained in a CALL machine instruction
438 const Value * getCallInstRetVal(const MachineInstr *CallMI) const;
439 const Value * getCallInstIndirectAddrVal(const MachineInstr *CallMI) const;
441 // The following methods are used to generate "copy" machine instructions
442 // for an architecture.
444 // The function regTypeNeedsScratchReg() can be used to check whether a
445 // scratch register is needed to copy a register of type `regType' to
446 // or from memory. If so, such a scratch register can be provided by
447 // the caller (e.g., if it knows which regsiters are free); otherwise
448 // an arbitrary one will be chosen and spilled by the copy instructions.
450 bool regTypeNeedsScratchReg(int RegType,
451 int& scratchRegClassId) const;
453 void cpReg2RegMI(std::vector<MachineInstr*>& mvec,
454 unsigned SrcReg, unsigned DestReg,
457 void cpReg2MemMI(std::vector<MachineInstr*>& mvec,
458 unsigned SrcReg, unsigned DestPtrReg,
459 int Offset, int RegType, int scratchReg = -1) const;
461 void cpMem2RegMI(std::vector<MachineInstr*>& mvec,
462 unsigned SrcPtrReg, int Offset, unsigned DestReg,
463 int RegType, int scratchReg = -1) const;
465 void cpValue2Value(Value *Src, Value *Dest,
466 std::vector<MachineInstr*>& mvec) const;
468 // To see whether a register is a volatile (i.e., whehter it must be
469 // preserved acorss calls)
471 inline bool isRegVolatile(int RegClassID, int Reg) const {
472 return MachineRegClassArr[RegClassID]->isRegVolatile(Reg);
476 virtual unsigned getFramePointer() const;
477 virtual unsigned getStackPointer() const;
479 virtual int getInvalidRegNum() const {
480 return InvalidRegNum;
483 // This method inserts the caller saving code for call instructions
485 void insertCallerSavingCode(std::vector<MachineInstr*>& instrnsBefore,
486 std::vector<MachineInstr*>& instrnsAfter,
488 const BasicBlock *BB, PhyRegAlloc &PRA ) const;
494 //---------------------------------------------------------------------------
495 // class UltraSparcSchedInfo
498 // Interface to instruction scheduling information for UltraSPARC.
499 // The parameter values above are based on UltraSPARC IIi.
500 //---------------------------------------------------------------------------
503 class UltraSparcSchedInfo: public MachineSchedInfo {
505 UltraSparcSchedInfo(const TargetMachine &tgt);
507 virtual void initializeResources();
511 //---------------------------------------------------------------------------
512 // class UltraSparcFrameInfo
515 // Interface to stack frame layout info for the UltraSPARC.
516 // Starting offsets for each area of the stack frame are aligned at
517 // a multiple of getStackFrameSizeAlignment().
518 //---------------------------------------------------------------------------
520 class UltraSparcFrameInfo: public MachineFrameInfo {
522 UltraSparcFrameInfo(const TargetMachine &tgt) : MachineFrameInfo(tgt) {}
525 int getStackFrameSizeAlignment() const { return StackFrameSizeAlignment;}
526 int getMinStackFrameSize() const { return MinStackFrameSize; }
527 int getNumFixedOutgoingArgs() const { return NumFixedOutgoingArgs; }
528 int getSizeOfEachArgOnStack() const { return SizeOfEachArgOnStack; }
529 bool argsOnStackHaveFixedSize() const { return true; }
532 // These methods compute offsets using the frame contents for a
533 // particular function. The frame contents are obtained from the
534 // MachineCodeInfoForMethod object for the given function.
536 int getFirstIncomingArgOffset (MachineCodeForMethod& mcInfo,
539 growUp = true; // arguments area grows upwards
540 return FirstIncomingArgOffsetFromFP;
542 int getFirstOutgoingArgOffset (MachineCodeForMethod& mcInfo,
545 growUp = true; // arguments area grows upwards
546 return FirstOutgoingArgOffsetFromSP;
548 int getFirstOptionalOutgoingArgOffset(MachineCodeForMethod& mcInfo,
551 growUp = true; // arguments area grows upwards
552 return FirstOptionalOutgoingArgOffsetFromSP;
555 int getFirstAutomaticVarOffset (MachineCodeForMethod& mcInfo,
557 int getRegSpillAreaOffset (MachineCodeForMethod& mcInfo,
559 int getTmpAreaOffset (MachineCodeForMethod& mcInfo,
561 int getDynamicAreaOffset (MachineCodeForMethod& mcInfo,
565 // These methods specify the base register used for each stack area
566 // (generally FP or SP)
568 virtual int getIncomingArgBaseRegNum() const {
569 return (int) target.getRegInfo().getFramePointer();
571 virtual int getOutgoingArgBaseRegNum() const {
572 return (int) target.getRegInfo().getStackPointer();
574 virtual int getOptionalOutgoingArgBaseRegNum() const {
575 return (int) target.getRegInfo().getStackPointer();
577 virtual int getAutomaticVarBaseRegNum() const {
578 return (int) target.getRegInfo().getFramePointer();
580 virtual int getRegSpillAreaBaseRegNum() const {
581 return (int) target.getRegInfo().getFramePointer();
583 virtual int getDynamicAreaBaseRegNum() const {
584 return (int) target.getRegInfo().getStackPointer();
588 // All stack addresses must be offset by 0x7ff (2047) on Sparc V9.
589 static const int OFFSET = (int) 0x7ff;
590 static const int StackFrameSizeAlignment = 16;
591 static const int MinStackFrameSize = 176;
592 static const int NumFixedOutgoingArgs = 6;
593 static const int SizeOfEachArgOnStack = 8;
594 static const int StaticAreaOffsetFromFP = 0 + OFFSET;
595 static const int FirstIncomingArgOffsetFromFP = 128 + OFFSET;
596 static const int FirstOptionalIncomingArgOffsetFromFP = 176 + OFFSET;
597 static const int FirstOutgoingArgOffsetFromSP = 128 + OFFSET;
598 static const int FirstOptionalOutgoingArgOffsetFromSP = 176 + OFFSET;
602 //---------------------------------------------------------------------------
603 // class UltraSparcCacheInfo
606 // Interface to cache parameters for the UltraSPARC.
607 // Just use defaults for now.
608 //---------------------------------------------------------------------------
610 class UltraSparcCacheInfo: public MachineCacheInfo {
612 UltraSparcCacheInfo(const TargetMachine &T) : MachineCacheInfo(T) {}
616 //---------------------------------------------------------------------------
617 // class UltraSparcMachine
620 // Primary interface to machine description for the UltraSPARC.
621 // Primarily just initializes machine-dependent parameters in
622 // class TargetMachine, and creates machine-dependent subclasses
623 // for classes such as InstrInfo, SchedInfo and RegInfo.
624 //---------------------------------------------------------------------------
626 class UltraSparc : public TargetMachine {
628 UltraSparcInstrInfo instrInfo;
629 UltraSparcSchedInfo schedInfo;
630 UltraSparcRegInfo regInfo;
631 UltraSparcFrameInfo frameInfo;
632 UltraSparcCacheInfo cacheInfo;
636 virtual const MachineInstrInfo &getInstrInfo() const { return instrInfo; }
637 virtual const MachineSchedInfo &getSchedInfo() const { return schedInfo; }
638 virtual const MachineRegInfo &getRegInfo() const { return regInfo; }
639 virtual const MachineFrameInfo &getFrameInfo() const { return frameInfo; }
640 virtual const MachineCacheInfo &getCacheInfo() const { return cacheInfo; }
643 // addPassesToEmitAssembly - Add passes to the specified pass manager to get
644 // assembly langage code emited. For sparc, we have to do ...
646 virtual void addPassesToEmitAssembly(PassManager &PM, std::ostream &Out);
649 Pass *getFunctionAsmPrinterPass(PassManager &PM, std::ostream &Out);
650 Pass *getModuleAsmPrinterPass(PassManager &PM, std::ostream &Out);
651 Pass *getEmitBytecodeToAsmPass(std::ostream &Out);