2 //***************************************************************************
7 // This file defines stuff that is to be private to the Sparc
8 // backend, but is shared among different portions of the backend.
9 //**************************************************************************/
12 #ifndef SPARC_INTERNALS_H
13 #define SPARC_INTERNALS_H
15 #include "llvm/Target/TargetMachine.h"
16 #include "llvm/Target/MachineSchedInfo.h"
17 #include "llvm/Target/MachineFrameInfo.h"
18 #include "llvm/Target/MachineCacheInfo.h"
19 #include "llvm/Target/MachineRegInfo.h"
20 #include "llvm/Type.h"
21 #include <sys/types.h>
28 Pass *createPrologEpilogCodeInserter(TargetMachine &TM);
30 // OpCodeMask definitions for the Sparc V9
32 const OpCodeMask Immed = 0x00002000; // immed or reg operand?
33 const OpCodeMask Annul = 0x20000000; // annul delay instr?
34 const OpCodeMask PredictTaken = 0x00080000; // predict branch taken?
37 enum SparcInstrSchedClass {
38 SPARC_NONE, /* Instructions with no scheduling restrictions */
39 SPARC_IEUN, /* Integer class that can use IEU0 or IEU1 */
40 SPARC_IEU0, /* Integer class IEU0 */
41 SPARC_IEU1, /* Integer class IEU1 */
42 SPARC_FPM, /* FP Multiply or Divide instructions */
43 SPARC_FPA, /* All other FP instructions */
44 SPARC_CTI, /* Control-transfer instructions */
45 SPARC_LD, /* Load instructions */
46 SPARC_ST, /* Store instructions */
47 SPARC_SINGLE, /* Instructions that must issue by themselves */
49 SPARC_INV, /* This should stay at the end for the next value */
50 SPARC_NUM_SCHED_CLASSES = SPARC_INV
54 //---------------------------------------------------------------------------
55 // enum SparcMachineOpCode.
56 // const MachineInstrDescriptor SparcMachineInstrDesc[]
59 // Description of UltraSparc machine instructions.
61 //---------------------------------------------------------------------------
63 enum SparcMachineOpCode {
64 #define I(ENUM, OPCODESTRING, NUMOPERANDS, RESULTPOS, MAXIMM, IMMSE, \
65 NUMDELAYSLOTS, LATENCY, SCHEDCLASS, INSTFLAGS) \
67 #include "SparcInstr.def"
69 // End-of-array marker
71 NUM_REAL_OPCODES = PHI, // number of valid opcodes
72 NUM_TOTAL_OPCODES = INVALID_OPCODE
76 // Array of machine instruction descriptions...
77 extern const MachineInstrDescriptor SparcMachineInstrDesc[];
80 //---------------------------------------------------------------------------
81 // class UltraSparcInstrInfo
84 // Information about individual instructions.
85 // Most information is stored in the SparcMachineInstrDesc array above.
86 // Other information is computed on demand, and most such functions
87 // default to member functions in base class MachineInstrInfo.
88 //---------------------------------------------------------------------------
90 class UltraSparcInstrInfo : public MachineInstrInfo {
92 /*ctor*/ UltraSparcInstrInfo(const TargetMachine& tgt);
95 // All immediate constants are in position 1 except the
96 // store instructions.
98 virtual int getImmedConstantPos(MachineOpCode opCode) const {
100 if (this->maxImmedConstant(opCode, ignore) != 0)
102 assert(! this->isStore((MachineOpCode) STB - 1)); // first store is STB
103 assert(! this->isStore((MachineOpCode) STD + 1)); // last store is STD
104 return (opCode >= STB && opCode <= STD)? 2 : 1;
110 virtual bool hasResultInterlock (MachineOpCode opCode) const
112 // All UltraSPARC instructions have interlocks (note that delay slots
113 // are not considered here).
114 // However, instructions that use the result of an FCMP produce a
115 // 9-cycle stall if they are issued less than 3 cycles after the FCMP.
116 // Force the compiler to insert a software interlock (i.e., gap of
117 // 2 other groups, including NOPs if necessary).
118 return (opCode == FCMPS || opCode == FCMPD || opCode == FCMPQ);
121 //-------------------------------------------------------------------------
122 // Code generation support for creating individual machine instructions
123 //-------------------------------------------------------------------------
125 // Create an instruction sequence to put the constant `val' into
126 // the virtual register `dest'. `val' may be a Constant or a
127 // GlobalValue, viz., the constant address of a global variable or function.
128 // The generated instructions are returned in `mvec'.
129 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
130 // Any stack space required is allocated via mcff.
132 virtual void CreateCodeToLoadConst(const TargetMachine& target,
136 std::vector<MachineInstr*>& mvec,
137 MachineCodeForInstruction& mcfi) const;
139 // Create an instruction sequence to copy an integer value `val'
140 // to a floating point value `dest' by copying to memory and back.
141 // val must be an integral type. dest must be a Float or Double.
142 // The generated instructions are returned in `mvec'.
143 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
144 // Any stack space required is allocated via mcff.
146 virtual void CreateCodeToCopyIntToFloat(const TargetMachine& target,
150 std::vector<MachineInstr*>& mvec,
151 MachineCodeForInstruction& mcfi) const;
153 // Similarly, create an instruction sequence to copy an FP value
154 // `val' to an integer value `dest' by copying to memory and back.
155 // The generated instructions are returned in `mvec'.
156 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
157 // Any stack space required is allocated via mcff.
159 virtual void CreateCodeToCopyFloatToInt(const TargetMachine& target,
163 std::vector<MachineInstr*>& mvec,
164 MachineCodeForInstruction& mcfi) const;
166 // Create instruction(s) to copy src to dest, for arbitrary types
167 // The generated instructions are returned in `mvec'.
168 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
169 // Any stack space required is allocated via mcff.
171 virtual void CreateCopyInstructionsByType(const TargetMachine& target,
175 std::vector<MachineInstr*>& mvec,
176 MachineCodeForInstruction& mcfi) const;
178 // Create instruction sequence to produce a sign-extended register value
179 // from an arbitrary sized value (sized in bits, not bytes).
180 // Any stack space required is allocated via mcff.
182 virtual void CreateSignExtensionInstructions(const TargetMachine& target,
184 Value* unsignedSrcVal,
185 unsigned int srcSizeInBits,
187 std::vector<MachineInstr*>& mvec,
188 MachineCodeForInstruction& mcfi) const;
192 //----------------------------------------------------------------------------
193 // class UltraSparcRegInfo
195 // This class implements the virtual class MachineRegInfo for Sparc.
197 //----------------------------------------------------------------------------
199 class UltraSparcRegInfo : public MachineRegInfo {
200 // The actual register classes in the Sparc
203 IntRegClassID, // Integer
204 FloatRegClassID, // Float (both single/double)
205 IntCCRegClassID, // Int Condition Code
206 FloatCCRegClassID // Float Condition code
210 // Type of registers available in Sparc. There can be several reg types
211 // in the same class. For instace, the float reg class has Single/Double
222 // **** WARNING: If the above enum order is changed, also modify
223 // getRegisterClassOfValue method below since it assumes this particular
224 // order for efficiency.
227 // reverse pointer to get info about the ultra sparc machine
229 const UltraSparc *const UltraSparcInfo;
231 // Number of registers used for passing int args (usually 6: %o0 - %o5)
233 unsigned const NumOfIntArgRegs;
235 // Number of registers used for passing float args (usually 32: %f0 - %f31)
237 unsigned const NumOfFloatArgRegs;
239 // An out of bound register number that can be used to initialize register
240 // numbers. Useful for error detection.
242 int const InvalidRegNum;
245 // ======================== Private Methods =============================
247 // The following methods are used to color special live ranges (e.g.
248 // function args and return values etc.) with specific hardware registers
249 // as required. See SparcRegInfo.cpp for the implementation.
251 void setCallOrRetArgCol(LiveRange *LR, unsigned RegNo,
252 const MachineInstr *MI,
253 std::hash_map<const MachineInstr *,
254 AddedInstrns *> &AIMap) const;
256 MachineInstr *getCopy2RegMI(const Value *SrcVal, unsigned Reg,
257 unsigned RegClassID) const;
259 void suggestReg4RetAddr(const MachineInstr *RetMI,
260 LiveRangeInfo &LRI) const;
262 void suggestReg4CallAddr(const MachineInstr *CallMI, LiveRangeInfo &LRI,
263 std::vector<RegClass *> RCList) const;
265 void InitializeOutgoingArg(const MachineInstr* CallMI, AddedInstrns *CallAI,
266 PhyRegAlloc &PRA, LiveRange* LR,
267 unsigned regType, unsigned RegClassID,
268 int UniArgReg, unsigned int argNo,
269 std::vector<MachineInstr *>& AddedInstrnsBefore)
272 // The following 4 methods are used to find the RegType (see enum above)
273 // of a LiveRange, Value and using the unified RegClassID
274 int getRegType(unsigned regClassID, const Type* type) const;
275 int getRegType(const LiveRange *LR) const;
276 int getRegType(const Value *Val) const;
277 int getRegType(int reg) const;
280 // The following methods are used to generate copy instructions to move
281 // data between condition code registers
283 MachineInstr *cpCCR2IntMI(unsigned IntReg) const;
284 MachineInstr *cpInt2CCRMI(unsigned IntReg) const;
286 // Used to generate a copy instruction based on the register class of
289 MachineInstr *cpValue2RegMI(Value *Val, unsigned DestReg,
293 // The following 2 methods are used to order the instructions addeed by
294 // the register allocator in association with function calling. See
295 // SparcRegInfo.cpp for more details
297 void moveInst2OrdVec(std::vector<MachineInstr *> &OrdVec,
298 MachineInstr *UnordInst,
299 PhyRegAlloc &PRA) const;
301 void OrderAddedInstrns(std::vector<MachineInstr *> &UnordVec,
302 std::vector<MachineInstr *> &OrdVec,
303 PhyRegAlloc &PRA) const;
306 // Compute which register can be used for an argument, if any
308 int regNumForIntArg(bool inCallee, bool isVarArgsCall,
309 unsigned argNo, unsigned intArgNo, unsigned fpArgNo,
310 unsigned& regClassId) const;
312 int regNumForFPArg(unsigned RegType, bool inCallee, bool isVarArgsCall,
313 unsigned argNo, unsigned intArgNo, unsigned fpArgNo,
314 unsigned& regClassId) const;
317 UltraSparcRegInfo(const UltraSparc &tgt);
319 // To get complete machine information structure using the machine register
322 inline const UltraSparc &getUltraSparcInfo() const {
323 return *UltraSparcInfo;
326 // To find the register class used for a specified Type
328 inline unsigned getRegClassIDOfType(const Type *type,
329 bool isCCReg = false) const {
330 Type::PrimitiveID ty = type->getPrimitiveID();
333 // FIXME: Comparing types like this isn't very safe...
334 if ((ty && ty <= Type::LongTyID) || (ty == Type::LabelTyID) ||
335 (ty == Type::FunctionTyID) || (ty == Type::PointerTyID) )
336 res = IntRegClassID; // sparc int reg (ty=0: void)
337 else if (ty <= Type::DoubleTyID)
338 res = FloatRegClassID; // sparc float reg class
340 //std::cerr << "TypeID: " << ty << "\n";
341 assert(0 && "Cannot resolve register class for type");
346 return res + 2; // corresponidng condition code regiser
351 // To find the register class of a Value
353 inline unsigned getRegClassIDOfValue(const Value *Val,
354 bool isCCReg = false) const {
355 return getRegClassIDOfType(Val->getType(), isCCReg);
360 // getZeroRegNum - returns the register that contains always zero this is the
361 // unified register number
363 virtual int getZeroRegNum() const;
365 // getCallAddressReg - returns the reg used for pushing the address when a
366 // function is called. This can be used for other purposes between calls
368 unsigned getCallAddressReg() const;
370 // Returns the register containing the return address.
371 // It should be made sure that this register contains the return
372 // value when a return instruction is reached.
374 unsigned getReturnAddressReg() const;
376 // Number of registers used for passing int args (usually 6: %o0 - %o5)
377 // and float args (usually 32: %f0 - %f31)
379 unsigned const GetNumOfIntArgRegs() const { return NumOfIntArgRegs; }
380 unsigned const GetNumOfFloatArgRegs() const { return NumOfFloatArgRegs; }
382 // The following methods are used to color special live ranges (e.g.
383 // function args and return values etc.) with specific hardware registers
384 // as required. See SparcRegInfo.cpp for the implementation for Sparc.
386 void suggestRegs4MethodArgs(const Function *Meth,
387 LiveRangeInfo& LRI) const;
389 void suggestRegs4CallArgs(const MachineInstr *CallMI,
391 std::vector<RegClass *> RCL) const;
393 void suggestReg4RetValue(const MachineInstr *RetMI,
394 LiveRangeInfo& LRI) const;
397 void colorMethodArgs(const Function *Meth, LiveRangeInfo &LRI,
398 AddedInstrns *FirstAI) const;
400 void colorCallArgs(const MachineInstr *CallMI, LiveRangeInfo &LRI,
401 AddedInstrns *CallAI, PhyRegAlloc &PRA,
402 const BasicBlock *BB) const;
404 void colorRetValue(const MachineInstr *RetI, LiveRangeInfo& LRI,
405 AddedInstrns *RetAI) const;
409 // method used for printing a register for debugging purposes
411 static void printReg(const LiveRange *LR);
413 // this method provides a unique number for each register
415 inline int getUnifiedRegNum(int RegClassID, int reg) const {
417 if( RegClassID == IntRegClassID && reg < 32 )
419 else if ( RegClassID == FloatRegClassID && reg < 64)
420 return reg + 32; // we have 32 int regs
421 else if( RegClassID == FloatCCRegClassID && reg < 4)
422 return reg + 32 + 64; // 32 int, 64 float
423 else if( RegClassID == IntCCRegClassID )
424 return reg + 4+ 32 + 64; // only int cc reg
425 else if (reg==InvalidRegNum)
426 return InvalidRegNum;
428 assert(0 && "Invalid register class or reg number");
432 // given the unified register number, this gives the name
433 // for generating assembly code or debugging.
435 virtual const std::string getUnifiedRegName(int reg) const;
438 // returns the # of bytes of stack space allocated for each register
439 // type. For Sparc, currently we allocate 8 bytes on stack for all
440 // register types. We can optimize this later if necessary to save stack
441 // space (However, should make sure that stack alignment is correct)
443 inline int getSpilledRegSize(int RegType) const {
448 // To obtain the return value and the indirect call address (if any)
449 // contained in a CALL machine instruction
451 const Value * getCallInstRetVal(const MachineInstr *CallMI) const;
452 const Value * getCallInstIndirectAddrVal(const MachineInstr *CallMI) const;
454 // The following methods are used to generate "copy" machine instructions
455 // for an architecture.
457 void cpReg2RegMI(unsigned SrcReg, unsigned DestReg,
458 int RegType, vector<MachineInstr*>& mvec) const;
460 void cpReg2MemMI(unsigned SrcReg, unsigned DestPtrReg,
461 int Offset, int RegType, vector<MachineInstr*>& mvec) const;
463 void cpMem2RegMI(unsigned SrcPtrReg, int Offset, unsigned DestReg,
464 int RegType, vector<MachineInstr*>& mvec) const;
466 void cpValue2Value(Value *Src, Value *Dest,
467 vector<MachineInstr*>& mvec) const;
469 // To see whether a register is a volatile (i.e., whehter it must be
470 // preserved acorss calls)
472 inline bool isRegVolatile(int RegClassID, int Reg) const {
473 return MachineRegClassArr[RegClassID]->isRegVolatile(Reg);
477 virtual unsigned getFramePointer() const;
478 virtual unsigned getStackPointer() const;
480 virtual int getInvalidRegNum() const {
481 return InvalidRegNum;
484 // This method inserts the caller saving code for call instructions
486 void insertCallerSavingCode(const MachineInstr *MInst,
487 const BasicBlock *BB, PhyRegAlloc &PRA ) const;
493 //---------------------------------------------------------------------------
494 // class UltraSparcSchedInfo
497 // Interface to instruction scheduling information for UltraSPARC.
498 // The parameter values above are based on UltraSPARC IIi.
499 //---------------------------------------------------------------------------
502 class UltraSparcSchedInfo: public MachineSchedInfo {
504 UltraSparcSchedInfo(const TargetMachine &tgt);
506 virtual void initializeResources();
510 //---------------------------------------------------------------------------
511 // class UltraSparcFrameInfo
514 // Interface to stack frame layout info for the UltraSPARC.
515 // Starting offsets for each area of the stack frame are aligned at
516 // a multiple of getStackFrameSizeAlignment().
517 //---------------------------------------------------------------------------
519 class UltraSparcFrameInfo: public MachineFrameInfo {
521 UltraSparcFrameInfo(const TargetMachine &tgt) : MachineFrameInfo(tgt) {}
524 int getStackFrameSizeAlignment() const { return StackFrameSizeAlignment;}
525 int getMinStackFrameSize() const { return MinStackFrameSize; }
526 int getNumFixedOutgoingArgs() const { return NumFixedOutgoingArgs; }
527 int getSizeOfEachArgOnStack() const { return SizeOfEachArgOnStack; }
528 bool argsOnStackHaveFixedSize() const { return true; }
531 // These methods compute offsets using the frame contents for a
532 // particular function. The frame contents are obtained from the
533 // MachineCodeInfoForMethod object for the given function.
535 int getFirstIncomingArgOffset (MachineCodeForMethod& mcInfo,
538 growUp = true; // arguments area grows upwards
539 return FirstIncomingArgOffsetFromFP;
541 int getFirstOutgoingArgOffset (MachineCodeForMethod& mcInfo,
544 growUp = true; // arguments area grows upwards
545 return FirstOutgoingArgOffsetFromSP;
547 int getFirstOptionalOutgoingArgOffset(MachineCodeForMethod& mcInfo,
550 growUp = true; // arguments area grows upwards
551 return FirstOptionalOutgoingArgOffsetFromSP;
554 int getFirstAutomaticVarOffset (MachineCodeForMethod& mcInfo,
556 int getRegSpillAreaOffset (MachineCodeForMethod& mcInfo,
558 int getTmpAreaOffset (MachineCodeForMethod& mcInfo,
560 int getDynamicAreaOffset (MachineCodeForMethod& mcInfo,
564 // These methods specify the base register used for each stack area
565 // (generally FP or SP)
567 virtual int getIncomingArgBaseRegNum() const {
568 return (int) target.getRegInfo().getFramePointer();
570 virtual int getOutgoingArgBaseRegNum() const {
571 return (int) target.getRegInfo().getStackPointer();
573 virtual int getOptionalOutgoingArgBaseRegNum() const {
574 return (int) target.getRegInfo().getStackPointer();
576 virtual int getAutomaticVarBaseRegNum() const {
577 return (int) target.getRegInfo().getFramePointer();
579 virtual int getRegSpillAreaBaseRegNum() const {
580 return (int) target.getRegInfo().getFramePointer();
582 virtual int getDynamicAreaBaseRegNum() const {
583 return (int) target.getRegInfo().getStackPointer();
587 // All stack addresses must be offset by 0x7ff (2047) on Sparc V9.
588 static const int OFFSET = (int) 0x7ff;
589 static const int StackFrameSizeAlignment = 16;
590 static const int MinStackFrameSize = 176;
591 static const int NumFixedOutgoingArgs = 6;
592 static const int SizeOfEachArgOnStack = 8;
593 static const int StaticAreaOffsetFromFP = 0 + OFFSET;
594 static const int FirstIncomingArgOffsetFromFP = 128 + OFFSET;
595 static const int FirstOptionalIncomingArgOffsetFromFP = 176 + OFFSET;
596 static const int FirstOutgoingArgOffsetFromSP = 128 + OFFSET;
597 static const int FirstOptionalOutgoingArgOffsetFromSP = 176 + OFFSET;
601 //---------------------------------------------------------------------------
602 // class UltraSparcCacheInfo
605 // Interface to cache parameters for the UltraSPARC.
606 // Just use defaults for now.
607 //---------------------------------------------------------------------------
609 class UltraSparcCacheInfo: public MachineCacheInfo {
611 UltraSparcCacheInfo(const TargetMachine &T) : MachineCacheInfo(T) {}
615 //---------------------------------------------------------------------------
616 // class UltraSparcMachine
619 // Primary interface to machine description for the UltraSPARC.
620 // Primarily just initializes machine-dependent parameters in
621 // class TargetMachine, and creates machine-dependent subclasses
622 // for classes such as InstrInfo, SchedInfo and RegInfo.
623 //---------------------------------------------------------------------------
625 class UltraSparc : public TargetMachine {
627 UltraSparcInstrInfo instrInfo;
628 UltraSparcSchedInfo schedInfo;
629 UltraSparcRegInfo regInfo;
630 UltraSparcFrameInfo frameInfo;
631 UltraSparcCacheInfo cacheInfo;
635 virtual const MachineInstrInfo &getInstrInfo() const { return instrInfo; }
636 virtual const MachineSchedInfo &getSchedInfo() const { return schedInfo; }
637 virtual const MachineRegInfo &getRegInfo() const { return regInfo; }
638 virtual const MachineFrameInfo &getFrameInfo() const { return frameInfo; }
639 virtual const MachineCacheInfo &getCacheInfo() const { return cacheInfo; }
642 // addPassesToEmitAssembly - Add passes to the specified pass manager to get
643 // assembly langage code emited. For sparc, we have to do ...
645 virtual void addPassesToEmitAssembly(PassManager &PM, std::ostream &Out);
648 Pass *getFunctionAsmPrinterPass(PassManager &PM, std::ostream &Out);
649 Pass *getModuleAsmPrinterPass(PassManager &PM, std::ostream &Out);
650 Pass *getEmitBytecodeToAsmPass(std::ostream &Out);